https://github.com/jofrn updated https://github.com/llvm/llvm-project/pull/199520
>From 12e5a0f73d256c2702c38e3613c1357208da2bae Mon Sep 17 00:00:00 2001 From: jofrn <[email protected]> Date: Mon, 25 May 2026 04:27:25 -0700 Subject: [PATCH] [X86] Remove shouldCastAtomicLoadInIR; use DAG combine instead Remove X86's shouldCastAtomicLoadInIR override that cast FP atomic loads to integer at the IR level. Instead, handle this in a pre-legalize DAG combine (combineAtomicLoad) that rewrites FP/FP-vector atomic loads to integer atomic loads plus a bitcast. This depends on #199310 which adds the necessary cmpxchg support for non-integer atomic loads in AtomicExpand. --- llvm/lib/Target/X86/X86ISelLowering.cpp | 32 +++++++++++++++---- llvm/lib/Target/X86/X86ISelLowering.h | 2 -- .../X86/expand-atomic-non-integer.ll | 6 ++-- 3 files changed, 27 insertions(+), 13 deletions(-) diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index ce3811cbcaf2d..29e34c082fe0e 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -2785,6 +2785,7 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM, ISD::FMINNUM, ISD::FMAXNUM, ISD::SUB, + ISD::ATOMIC_LOAD, ISD::LOAD, ISD::LRINT, ISD::LLRINT, @@ -33096,13 +33097,6 @@ X86TargetLowering::shouldExpandAtomicRMWInIR(const AtomicRMWInst *AI) const { } } -TargetLowering::AtomicExpansionKind -X86TargetLowering::shouldCastAtomicLoadInIR(LoadInst *LI) const { - if (LI->getType()->getScalarType()->isFloatingPointTy()) - return AtomicExpansionKind::CastToInteger; - return AtomicExpansionKind::None; -} - LoadInst * X86TargetLowering::lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const { unsigned NativeWidth = Subtarget.is64Bit() ? 64 : 32; @@ -54226,6 +54220,29 @@ static SDValue combineConstantPoolLoads(SDNode *N, const SDLoc &dl, return SDValue(); } +static SDValue combineAtomicLoad(SDNode *N, SelectionDAG &DAG, + TargetLowering::DAGCombinerInfo &DCI) { + if (!DCI.isBeforeLegalize()) + return SDValue(); + + auto *AN = cast<AtomicSDNode>(N); + EVT VT = AN->getValueType(0); + if (!VT.getScalarType().isFloatingPoint()) + return SDValue(); + + unsigned BitWidth = VT.getStoreSizeInBits(); + if (BitWidth != VT.getSizeInBits()) + return SDValue(); + + SDLoc DL(N); + EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), BitWidth); + SDValue IntLoad = DAG.getAtomic( + ISD::ATOMIC_LOAD, DL, IntVT, DAG.getVTList(IntVT, MVT::Other), + {AN->getChain(), AN->getBasePtr()}, AN->getMemOperand()); + SDValue Cast = DAG.getBitcast(VT, IntLoad); + return DAG.getMergeValues({Cast, IntLoad.getValue(1)}, DL); +} + static SDValue combineLoad(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget &Subtarget) { @@ -63004,6 +63021,7 @@ SDValue X86TargetLowering::PerformDAGCombine(SDNode *N, case ISD::AVGCEILU: case ISD::AVGFLOORS: case ISD::AVGFLOORU: return combineAVG(N, DAG, DCI, Subtarget); + case ISD::ATOMIC_LOAD: return combineAtomicLoad(N, DAG, DCI); case ISD::LOAD: return combineLoad(N, DAG, DCI, Subtarget); case ISD::MLOAD: return combineMaskedLoad(N, DAG, DCI, Subtarget); case ISD::STORE: return combineStore(N, DAG, DCI, Subtarget); diff --git a/llvm/lib/Target/X86/X86ISelLowering.h b/llvm/lib/Target/X86/X86ISelLowering.h index 9a958525057b6..0d05c5772a707 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.h +++ b/llvm/lib/Target/X86/X86ISelLowering.h @@ -892,8 +892,6 @@ namespace llvm { shouldExpandAtomicRMWInIR(const AtomicRMWInst *AI) const override; TargetLoweringBase::AtomicExpansionKind shouldExpandLogicAtomicRMWInIR(const AtomicRMWInst *AI) const; - TargetLoweringBase::AtomicExpansionKind - shouldCastAtomicLoadInIR(LoadInst *LI) const override; void emitBitTestAtomicRMWIntrinsic(AtomicRMWInst *AI) const override; void emitCmpArithAtomicRMWIntrinsic(AtomicRMWInst *AI) const override; diff --git a/llvm/test/Transforms/AtomicExpand/X86/expand-atomic-non-integer.ll b/llvm/test/Transforms/AtomicExpand/X86/expand-atomic-non-integer.ll index 825e3964e98c2..bb1cb5a0eaee6 100644 --- a/llvm/test/Transforms/AtomicExpand/X86/expand-atomic-non-integer.ll +++ b/llvm/test/Transforms/AtomicExpand/X86/expand-atomic-non-integer.ll @@ -437,14 +437,12 @@ define <2 x i16> @atomic_vec2_i16(ptr %x) nounwind { define <2 x half> @atomic_vec2_half(ptr %x) nounwind { ; CHECK-LABEL: define <2 x half> @atomic_vec2_half( ; CHECK-SAME: ptr [[X:%.*]]) #[[ATTR0]] { -; CHECK-NEXT: [[TMP1:%.*]] = load atomic i32, ptr [[X]] acquire, align 8 -; CHECK-NEXT: [[RET:%.*]] = bitcast i32 [[TMP1]] to <2 x half> +; CHECK-NEXT: [[RET:%.*]] = load atomic <2 x half>, ptr [[X]] acquire, align 8 ; CHECK-NEXT: ret <2 x half> [[RET]] ; ; CX16-LABEL: define <2 x half> @atomic_vec2_half( ; CX16-SAME: ptr [[X:%.*]]) #[[ATTR1]] { -; CX16-NEXT: [[TMP1:%.*]] = load atomic i32, ptr [[X]] acquire, align 8 -; CX16-NEXT: [[TMP2:%.*]] = bitcast i32 [[TMP1]] to <2 x half> +; CX16-NEXT: [[TMP2:%.*]] = load atomic <2 x half>, ptr [[X]] acquire, align 8 ; CX16-NEXT: ret <2 x half> [[TMP2]] ; %ret = load atomic <2 x half>, ptr %x acquire, align 8 _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
