https://github.com/easyonaadit updated https://github.com/llvm/llvm-project/pull/194809
>From 8d890859ae3f8a424bb2922e69885179faf8167e Mon Sep 17 00:00:00 2001 From: Aaditya <[email protected]> Date: Tue, 28 Apr 2026 13:32:36 +0530 Subject: [PATCH 1/2] [AMDGPU] Support Wave Reduction for true-16 types - 1 Supporting true-16 versions of the reduction intrinsics Supported Ops: `min`, `umin`, `max`, `umax`. Supports only the iterative stratergy, DPP is yet to be supported. --- llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 1 - llvm/lib/Target/AMDGPU/SIInstructions.td | 3 +- .../CodeGen/AMDGPU/llvm.amdgcn.reduce.max.ll | 91 +++++--- .../CodeGen/AMDGPU/llvm.amdgcn.reduce.min.ll | 92 +++++--- .../CodeGen/AMDGPU/llvm.amdgcn.reduce.umax.ll | 215 +++++++++++++----- .../CodeGen/AMDGPU/llvm.amdgcn.reduce.umin.ll | 198 ++++++++++------ 6 files changed, 424 insertions(+), 176 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index db3f86dca4256..487a66eb63145 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -6125,7 +6125,6 @@ static MachineBasicBlock *lowerWaveReduce(MachineInstr &MI, AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel) != -1; bool hasOMod = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::omod) != -1; - BuildMI(*ComputeLoop, I, DL, TII->get(AMDGPU::V_READLANE_B32), LaneValueReg) .addReg(SrcReg) diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td index 3f89ebc55fc83..7c5fbe488916d 100644 --- a/llvm/lib/Target/AMDGPU/SIInstructions.td +++ b/llvm/lib/Target/AMDGPU/SIInstructions.td @@ -351,7 +351,8 @@ def : GCNPat<(i32 (int_amdgcn_set_inactive_chain_arg i32:$src, i32:$inactive)), multiclass AMDGPUWaveReducePseudoGenerator<string Op, string DataType, ValueType ty, RegisterClass RetReg, SrcRegOrImm9 Reg> { - let usesCustomInserter = 1, hasSideEffects = 0, mayLoad = 0, mayStore = 0, UseNamedOperandTable = 1, Uses = [EXEC] in { + let usesCustomInserter = 1, hasSideEffects = 0, mayLoad = 0, mayStore = 0, + UseNamedOperandTable = 1, Uses = [EXEC] in { def !toupper(Op) #"_PSEUDO_" #DataType : VPseudoInstSI<(outs RetReg : $sdst), (ins Reg : $src, i32imm : $strategy), diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.max.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.max.ll index 7e68bc46877d8..96402193efd5e 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.max.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.max.ll @@ -7,10 +7,14 @@ ; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX10GISEL,GFX1064GISEL %s ; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=0 < %s | FileCheck -check-prefixes=GFX10DAGISEL,GFX1032DAGISEL %s ; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX10GISEL,GFX1032GISEL %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -global-isel=0 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1164DAGISEL %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1164GISEL %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -global-isel=0 < %s | FileCheck -check-prefixes=GFX1132DAGISEL %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX1132GISEL %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -global-isel=0 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1164DAGISEL,GFX1164DAGISEL-FAKE16 %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1164GISEL,GFX1164GISEL-FAKE16 %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -global-isel=0 < %s | FileCheck -check-prefixes=GFX1132DAGISEL,GFX1132DAGISEL-FAKE16 %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX1132GISEL,GFX1132GISEL-FAKE16 %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -global-isel=0 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1164DAGISEL,GFX1164DAGISEL-TRUE16 %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1164GISEL,GFX1164GISEL-TRUE16 %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -global-isel=0 < %s | FileCheck -check-prefixes=GFX1132DAGISEL,GFX1132DAGISEL-TRUE16 %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX1132GISEL,GFX1132GISEL-TRUE16 %s define amdgpu_kernel void @uniform_value_i16(ptr addrspace(1) %out, i16 %in) { ; GFX8DAGISEL-LABEL: uniform_value_i16: @@ -96,18 +100,18 @@ define amdgpu_kernel void @uniform_value_i16(ptr addrspace(1) %out, i16 %in) { ; GFX1164DAGISEL-NEXT: global_store_b16 v0, v1, s[0:1] ; GFX1164DAGISEL-NEXT: s_endpgm ; -; GFX1164GISEL-LABEL: uniform_value_i16: -; GFX1164GISEL: ; %bb.0: ; %entry -; GFX1164GISEL-NEXT: s_clause 0x1 -; GFX1164GISEL-NEXT: s_load_b32 s2, s[4:5], 0x2c -; GFX1164GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 -; GFX1164GISEL-NEXT: v_mov_b32_e32 v1, 0 -; GFX1164GISEL-NEXT: s_waitcnt lgkmcnt(0) -; GFX1164GISEL-NEXT: s_sext_i32_i16 s2, s2 -; GFX1164GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX1164GISEL-NEXT: v_mov_b32_e32 v0, s2 -; GFX1164GISEL-NEXT: global_store_b16 v1, v0, s[0:1] -; GFX1164GISEL-NEXT: s_endpgm +; GFX1164GISEL-FAKE16-LABEL: uniform_value_i16: +; GFX1164GISEL-FAKE16: ; %bb.0: ; %entry +; GFX1164GISEL-FAKE16-NEXT: s_clause 0x1 +; GFX1164GISEL-FAKE16-NEXT: s_load_b32 s2, s[4:5], 0x2c +; GFX1164GISEL-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 +; GFX1164GISEL-FAKE16-NEXT: v_mov_b32_e32 v1, 0 +; GFX1164GISEL-FAKE16-NEXT: s_waitcnt lgkmcnt(0) +; GFX1164GISEL-FAKE16-NEXT: s_sext_i32_i16 s2, s2 +; GFX1164GISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX1164GISEL-FAKE16-NEXT: v_mov_b32_e32 v0, s2 +; GFX1164GISEL-FAKE16-NEXT: global_store_b16 v1, v0, s[0:1] +; GFX1164GISEL-FAKE16-NEXT: s_endpgm ; ; GFX1132DAGISEL-LABEL: uniform_value_i16: ; GFX1132DAGISEL: ; %bb.0: ; %entry @@ -121,18 +125,44 @@ define amdgpu_kernel void @uniform_value_i16(ptr addrspace(1) %out, i16 %in) { ; GFX1132DAGISEL-NEXT: global_store_b16 v0, v1, s[0:1] ; GFX1132DAGISEL-NEXT: s_endpgm ; -; GFX1132GISEL-LABEL: uniform_value_i16: -; GFX1132GISEL: ; %bb.0: ; %entry -; GFX1132GISEL-NEXT: s_clause 0x1 -; GFX1132GISEL-NEXT: s_load_b32 s2, s[4:5], 0x2c -; GFX1132GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 -; GFX1132GISEL-NEXT: v_mov_b32_e32 v1, 0 -; GFX1132GISEL-NEXT: s_waitcnt lgkmcnt(0) -; GFX1132GISEL-NEXT: s_sext_i32_i16 s2, s2 -; GFX1132GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX1132GISEL-NEXT: v_mov_b32_e32 v0, s2 -; GFX1132GISEL-NEXT: global_store_b16 v1, v0, s[0:1] -; GFX1132GISEL-NEXT: s_endpgm +; GFX1132GISEL-FAKE16-LABEL: uniform_value_i16: +; GFX1132GISEL-FAKE16: ; %bb.0: ; %entry +; GFX1132GISEL-FAKE16-NEXT: s_clause 0x1 +; GFX1132GISEL-FAKE16-NEXT: s_load_b32 s2, s[4:5], 0x2c +; GFX1132GISEL-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 +; GFX1132GISEL-FAKE16-NEXT: v_mov_b32_e32 v1, 0 +; GFX1132GISEL-FAKE16-NEXT: s_waitcnt lgkmcnt(0) +; GFX1132GISEL-FAKE16-NEXT: s_sext_i32_i16 s2, s2 +; GFX1132GISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX1132GISEL-FAKE16-NEXT: v_mov_b32_e32 v0, s2 +; GFX1132GISEL-FAKE16-NEXT: global_store_b16 v1, v0, s[0:1] +; GFX1132GISEL-FAKE16-NEXT: s_endpgm +; +; GFX1164GISEL-TRUE16-LABEL: uniform_value_i16: +; GFX1164GISEL-TRUE16: ; %bb.0: ; %entry +; GFX1164GISEL-TRUE16-NEXT: s_clause 0x1 +; GFX1164GISEL-TRUE16-NEXT: s_load_b32 s2, s[4:5], 0x2c +; GFX1164GISEL-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 +; GFX1164GISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 0 +; GFX1164GISEL-TRUE16-NEXT: s_waitcnt lgkmcnt(0) +; GFX1164GISEL-TRUE16-NEXT: s_sext_i32_i16 s2, s2 +; GFX1164GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX1164GISEL-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2 +; GFX1164GISEL-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1] +; GFX1164GISEL-TRUE16-NEXT: s_endpgm +; +; GFX1132GISEL-TRUE16-LABEL: uniform_value_i16: +; GFX1132GISEL-TRUE16: ; %bb.0: ; %entry +; GFX1132GISEL-TRUE16-NEXT: s_clause 0x1 +; GFX1132GISEL-TRUE16-NEXT: s_load_b32 s2, s[4:5], 0x2c +; GFX1132GISEL-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 +; GFX1132GISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 0 +; GFX1132GISEL-TRUE16-NEXT: s_waitcnt lgkmcnt(0) +; GFX1132GISEL-TRUE16-NEXT: s_sext_i32_i16 s2, s2 +; GFX1132GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX1132GISEL-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2 +; GFX1132GISEL-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1] +; GFX1132GISEL-TRUE16-NEXT: s_endpgm entry: %result = call i16 @llvm.amdgcn.wave.reduce.max.i16(i16 %in, i32 1) store i16 %result, ptr addrspace(1) %out @@ -3691,3 +3721,8 @@ endif: store i64 %combine, ptr addrspace(1) %out ret void } +;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: +; GFX1132DAGISEL-FAKE16: {{.*}} +; GFX1132DAGISEL-TRUE16: {{.*}} +; GFX1164DAGISEL-FAKE16: {{.*}} +; GFX1164DAGISEL-TRUE16: {{.*}} diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.min.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.min.ll index beacaa08840f3..d0f49a0e0b28c 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.min.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.min.ll @@ -7,11 +7,14 @@ ; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX10GISEL,GFX1064GISEL %s ; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=0 < %s | FileCheck -check-prefixes=GFX10DAGISEL,GFX1032DAGISEL %s ; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX10GISEL,GFX1032GISEL %s -; RUN: llc -mtriple=amdgcn -mattr=-real-true16 -mcpu=gfx1100 -global-isel=0 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1164DAGISEL %s -; RUN: llc -mtriple=amdgcn -mattr=-real-true16 -mcpu=gfx1100 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1164GISEL %s -; RUN: llc -mtriple=amdgcn -mattr=-real-true16 -mcpu=gfx1100 -global-isel=0 < %s | FileCheck -check-prefixes=GFX1132DAGISEL %s -; RUN: llc -mtriple=amdgcn -mattr=-real-true16 -mcpu=gfx1100 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX1132GISEL %s - +; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -global-isel=0 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1164DAGISEL,GFX1164DAGISEL-FAKE16 %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1164GISEL,GFX1164GISEL-FAKE16 %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -global-isel=0 < %s | FileCheck -check-prefixes=GFX1132DAGISEL,GFX1132DAGISEL-FAKE16 %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX1132GISEL,GFX1132GISEL-FAKE16 %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -global-isel=0 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1164DAGISEL,GFX1164DAGISEL-TRUE16 %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1164GISEL,GFX1164GISEL-TRUE16 %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -global-isel=0 < %s | FileCheck -check-prefixes=GFX1132DAGISEL,GFX1132DAGISEL-TRUE16 %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX1132GISEL,GFX1132GISEL-TRUE16 %s define amdgpu_kernel void @uniform_value_i16(ptr addrspace(1) %out, i16 %in) { ; GFX8DAGISEL-LABEL: uniform_value_i16: ; GFX8DAGISEL: ; %bb.0: ; %entry @@ -96,18 +99,18 @@ define amdgpu_kernel void @uniform_value_i16(ptr addrspace(1) %out, i16 %in) { ; GFX1164DAGISEL-NEXT: global_store_b16 v0, v1, s[0:1] ; GFX1164DAGISEL-NEXT: s_endpgm ; -; GFX1164GISEL-LABEL: uniform_value_i16: -; GFX1164GISEL: ; %bb.0: ; %entry -; GFX1164GISEL-NEXT: s_clause 0x1 -; GFX1164GISEL-NEXT: s_load_b32 s2, s[4:5], 0x2c -; GFX1164GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 -; GFX1164GISEL-NEXT: v_mov_b32_e32 v1, 0 -; GFX1164GISEL-NEXT: s_waitcnt lgkmcnt(0) -; GFX1164GISEL-NEXT: s_sext_i32_i16 s2, s2 -; GFX1164GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX1164GISEL-NEXT: v_mov_b32_e32 v0, s2 -; GFX1164GISEL-NEXT: global_store_b16 v1, v0, s[0:1] -; GFX1164GISEL-NEXT: s_endpgm +; GFX1164GISEL-FAKE16-LABEL: uniform_value_i16: +; GFX1164GISEL-FAKE16: ; %bb.0: ; %entry +; GFX1164GISEL-FAKE16-NEXT: s_clause 0x1 +; GFX1164GISEL-FAKE16-NEXT: s_load_b32 s2, s[4:5], 0x2c +; GFX1164GISEL-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 +; GFX1164GISEL-FAKE16-NEXT: v_mov_b32_e32 v1, 0 +; GFX1164GISEL-FAKE16-NEXT: s_waitcnt lgkmcnt(0) +; GFX1164GISEL-FAKE16-NEXT: s_sext_i32_i16 s2, s2 +; GFX1164GISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX1164GISEL-FAKE16-NEXT: v_mov_b32_e32 v0, s2 +; GFX1164GISEL-FAKE16-NEXT: global_store_b16 v1, v0, s[0:1] +; GFX1164GISEL-FAKE16-NEXT: s_endpgm ; ; GFX1132DAGISEL-LABEL: uniform_value_i16: ; GFX1132DAGISEL: ; %bb.0: ; %entry @@ -121,18 +124,44 @@ define amdgpu_kernel void @uniform_value_i16(ptr addrspace(1) %out, i16 %in) { ; GFX1132DAGISEL-NEXT: global_store_b16 v0, v1, s[0:1] ; GFX1132DAGISEL-NEXT: s_endpgm ; -; GFX1132GISEL-LABEL: uniform_value_i16: -; GFX1132GISEL: ; %bb.0: ; %entry -; GFX1132GISEL-NEXT: s_clause 0x1 -; GFX1132GISEL-NEXT: s_load_b32 s2, s[4:5], 0x2c -; GFX1132GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 -; GFX1132GISEL-NEXT: v_mov_b32_e32 v1, 0 -; GFX1132GISEL-NEXT: s_waitcnt lgkmcnt(0) -; GFX1132GISEL-NEXT: s_sext_i32_i16 s2, s2 -; GFX1132GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX1132GISEL-NEXT: v_mov_b32_e32 v0, s2 -; GFX1132GISEL-NEXT: global_store_b16 v1, v0, s[0:1] -; GFX1132GISEL-NEXT: s_endpgm +; GFX1132GISEL-FAKE16-LABEL: uniform_value_i16: +; GFX1132GISEL-FAKE16: ; %bb.0: ; %entry +; GFX1132GISEL-FAKE16-NEXT: s_clause 0x1 +; GFX1132GISEL-FAKE16-NEXT: s_load_b32 s2, s[4:5], 0x2c +; GFX1132GISEL-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 +; GFX1132GISEL-FAKE16-NEXT: v_mov_b32_e32 v1, 0 +; GFX1132GISEL-FAKE16-NEXT: s_waitcnt lgkmcnt(0) +; GFX1132GISEL-FAKE16-NEXT: s_sext_i32_i16 s2, s2 +; GFX1132GISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX1132GISEL-FAKE16-NEXT: v_mov_b32_e32 v0, s2 +; GFX1132GISEL-FAKE16-NEXT: global_store_b16 v1, v0, s[0:1] +; GFX1132GISEL-FAKE16-NEXT: s_endpgm +; +; GFX1164GISEL-TRUE16-LABEL: uniform_value_i16: +; GFX1164GISEL-TRUE16: ; %bb.0: ; %entry +; GFX1164GISEL-TRUE16-NEXT: s_clause 0x1 +; GFX1164GISEL-TRUE16-NEXT: s_load_b32 s2, s[4:5], 0x2c +; GFX1164GISEL-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 +; GFX1164GISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 0 +; GFX1164GISEL-TRUE16-NEXT: s_waitcnt lgkmcnt(0) +; GFX1164GISEL-TRUE16-NEXT: s_sext_i32_i16 s2, s2 +; GFX1164GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX1164GISEL-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2 +; GFX1164GISEL-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1] +; GFX1164GISEL-TRUE16-NEXT: s_endpgm +; +; GFX1132GISEL-TRUE16-LABEL: uniform_value_i16: +; GFX1132GISEL-TRUE16: ; %bb.0: ; %entry +; GFX1132GISEL-TRUE16-NEXT: s_clause 0x1 +; GFX1132GISEL-TRUE16-NEXT: s_load_b32 s2, s[4:5], 0x2c +; GFX1132GISEL-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 +; GFX1132GISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 0 +; GFX1132GISEL-TRUE16-NEXT: s_waitcnt lgkmcnt(0) +; GFX1132GISEL-TRUE16-NEXT: s_sext_i32_i16 s2, s2 +; GFX1132GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX1132GISEL-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2 +; GFX1132GISEL-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1] +; GFX1132GISEL-TRUE16-NEXT: s_endpgm entry: %result = call i16 @llvm.amdgcn.wave.reduce.min.i16(i16 %in, i32 1) store i16 %result, ptr addrspace(1) %out @@ -3691,3 +3720,8 @@ endif: store i64 %combine, ptr addrspace(1) %out ret void } +;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: +; GFX1132DAGISEL-FAKE16: {{.*}} +; GFX1132DAGISEL-TRUE16: {{.*}} +; GFX1164DAGISEL-FAKE16: {{.*}} +; GFX1164DAGISEL-TRUE16: {{.*}} diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umax.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umax.ll index baea90b5092bb..81a9ac7f7e92c 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umax.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umax.ll @@ -7,10 +7,14 @@ ; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX10GISEL,GFX1064GISEL %s ; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=0 < %s | FileCheck -check-prefixes=GFX10DAGISEL,GFX1032DAGISEL %s ; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX10GISEL,GFX1032GISEL %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -global-isel=0 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX11DAGISEL,GFX1164DAGISEL %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX11GISEL,GFX1164GISEL %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -global-isel=0 < %s | FileCheck -check-prefixes=GFX11DAGISEL,GFX1132DAGISEL %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX11GISEL,GFX1132GISEL %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -global-isel=0 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1164DAGISEL,GFX1164DAGISEL-FAKE16 %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1164GISEL,GFX1164GISEL-FAKE16 %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -global-isel=0 < %s | FileCheck -check-prefixes=GFX1132DAGISEL,GFX1132DAGISEL-FAKE16 %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX1132GISEL,GFX1132GISEL-FAKE16 %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -global-isel=0 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1164DAGISEL,GFX1164DAGISEL-TRUE16 %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1164GISEL,GFX1164GISEL-TRUE16 %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -global-isel=0 < %s | FileCheck -check-prefixes=GFX1132DAGISEL,GFX1132DAGISEL-TRUE16 %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX1132GISEL,GFX1132GISEL-TRUE16 %s define amdgpu_kernel void @uniform_value_i16(ptr addrspace(1) %out, i16 %in) { ; GFX8DAGISEL-LABEL: uniform_value_i16: @@ -96,18 +100,18 @@ define amdgpu_kernel void @uniform_value_i16(ptr addrspace(1) %out, i16 %in) { ; GFX1164DAGISEL-NEXT: global_store_b16 v0, v1, s[0:1] ; GFX1164DAGISEL-NEXT: s_endpgm ; -; GFX11GISEL-LABEL: uniform_value_i16: -; GFX11GISEL: ; %bb.0: ; %entry -; GFX11GISEL-NEXT: s_clause 0x1 -; GFX11GISEL-NEXT: s_load_b32 s2, s[4:5], 0x2c -; GFX11GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 -; GFX11GISEL-NEXT: v_mov_b32_e32 v1, 0 -; GFX11GISEL-NEXT: s_waitcnt lgkmcnt(0) -; GFX11GISEL-NEXT: s_and_b32 s2, s2, 0xffff -; GFX11GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX11GISEL-NEXT: v_mov_b32_e32 v0, s2 -; GFX11GISEL-NEXT: global_store_b16 v1, v0, s[0:1] -; GFX11GISEL-NEXT: s_endpgm +; GFX1164GISEL-FAKE16-LABEL: uniform_value_i16: +; GFX1164GISEL-FAKE16: ; %bb.0: ; %entry +; GFX1164GISEL-FAKE16-NEXT: s_clause 0x1 +; GFX1164GISEL-FAKE16-NEXT: s_load_b32 s2, s[4:5], 0x2c +; GFX1164GISEL-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 +; GFX1164GISEL-FAKE16-NEXT: v_mov_b32_e32 v1, 0 +; GFX1164GISEL-FAKE16-NEXT: s_waitcnt lgkmcnt(0) +; GFX1164GISEL-FAKE16-NEXT: s_and_b32 s2, s2, 0xffff +; GFX1164GISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX1164GISEL-FAKE16-NEXT: v_mov_b32_e32 v0, s2 +; GFX1164GISEL-FAKE16-NEXT: global_store_b16 v1, v0, s[0:1] +; GFX1164GISEL-FAKE16-NEXT: s_endpgm ; ; GFX1132DAGISEL-LABEL: uniform_value_i16: ; GFX1132DAGISEL: ; %bb.0: ; %entry @@ -120,6 +124,57 @@ define amdgpu_kernel void @uniform_value_i16(ptr addrspace(1) %out, i16 %in) { ; GFX1132DAGISEL-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2 ; GFX1132DAGISEL-NEXT: global_store_b16 v0, v1, s[0:1] ; GFX1132DAGISEL-NEXT: s_endpgm +; +; GFX1132GISEL-FAKE16-LABEL: uniform_value_i16: +; GFX1132GISEL-FAKE16: ; %bb.0: ; %entry +; GFX1132GISEL-FAKE16-NEXT: s_clause 0x1 +; GFX1132GISEL-FAKE16-NEXT: s_load_b32 s2, s[4:5], 0x2c +; GFX1132GISEL-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 +; GFX1132GISEL-FAKE16-NEXT: v_mov_b32_e32 v1, 0 +; GFX1132GISEL-FAKE16-NEXT: s_waitcnt lgkmcnt(0) +; GFX1132GISEL-FAKE16-NEXT: s_and_b32 s2, s2, 0xffff +; GFX1132GISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX1132GISEL-FAKE16-NEXT: v_mov_b32_e32 v0, s2 +; GFX1132GISEL-FAKE16-NEXT: global_store_b16 v1, v0, s[0:1] +; GFX1132GISEL-FAKE16-NEXT: s_endpgm +; +; GFX1164GISEL-TRUE16-LABEL: uniform_value_i16: +; GFX1164GISEL-TRUE16: ; %bb.0: ; %entry +; GFX1164GISEL-TRUE16-NEXT: s_clause 0x1 +; GFX1164GISEL-TRUE16-NEXT: s_load_b32 s2, s[4:5], 0x2c +; GFX1164GISEL-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 +; GFX1164GISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 0 +; GFX1164GISEL-TRUE16-NEXT: s_waitcnt lgkmcnt(0) +; GFX1164GISEL-TRUE16-NEXT: s_and_b32 s2, s2, 0xffff +; GFX1164GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX1164GISEL-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2 +; GFX1164GISEL-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1] +; GFX1164GISEL-TRUE16-NEXT: s_endpgm +; +; GFX1132GISEL-TRUE16-LABEL: uniform_value_i16: +; GFX1132GISEL-TRUE16: ; %bb.0: ; %entry +; GFX1132GISEL-TRUE16-NEXT: s_clause 0x1 +; GFX1132GISEL-TRUE16-NEXT: s_load_b32 s2, s[4:5], 0x2c +; GFX1132GISEL-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 +; GFX1132GISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 0 +; GFX1132GISEL-TRUE16-NEXT: s_waitcnt lgkmcnt(0) +; GFX1132GISEL-TRUE16-NEXT: s_and_b32 s2, s2, 0xffff +; GFX1132GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX1132GISEL-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2 +; GFX1132GISEL-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1] +; GFX1132GISEL-TRUE16-NEXT: s_endpgm +; GFX11GISEL-LABEL: uniform_value_i16: +; GFX11GISEL: ; %bb.0: ; %entry +; GFX11GISEL-NEXT: s_clause 0x1 +; GFX11GISEL-NEXT: s_load_b32 s2, s[4:5], 0x2c +; GFX11GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 +; GFX11GISEL-NEXT: v_mov_b32_e32 v1, 0 +; GFX11GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX11GISEL-NEXT: s_and_b32 s2, s2, 0xffff +; GFX11GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11GISEL-NEXT: v_mov_b32_e32 v0, s2 +; GFX11GISEL-NEXT: global_store_b16 v1, v0, s[0:1] +; GFX11GISEL-NEXT: s_endpgm entry: %result = call i16 @llvm.amdgcn.wave.reduce.umax.i16(i16 %in, i32 1) store i16 %result, ptr addrspace(1) %out @@ -275,24 +330,24 @@ define void @divergent_value_i16(ptr addrspace(1) %out, i16 %in) { ; GFX1032GISEL-NEXT: global_store_short v[0:1], v2, off ; GFX1032GISEL-NEXT: s_setpc_b64 s[30:31] ; -; GFX1164DAGISEL-LABEL: divergent_value_i16: -; GFX1164DAGISEL: ; %bb.0: ; %entry -; GFX1164DAGISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1164DAGISEL-NEXT: v_and_b32_e32 v2, 0xffff, v2 -; GFX1164DAGISEL-NEXT: s_mov_b64 s[0:1], exec -; GFX1164DAGISEL-NEXT: s_mov_b32 s2, 0 -; GFX1164DAGISEL-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1 -; GFX1164DAGISEL-NEXT: s_ctz_i32_b64 s3, s[0:1] -; GFX1164DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) -; GFX1164DAGISEL-NEXT: v_readlane_b32 s4, v2, s3 -; GFX1164DAGISEL-NEXT: s_bitset0_b64 s[0:1], s3 -; GFX1164DAGISEL-NEXT: s_max_u32 s2, s2, s4 -; GFX1164DAGISEL-NEXT: s_cmp_lg_u64 s[0:1], 0 -; GFX1164DAGISEL-NEXT: s_cbranch_scc1 .LBB1_1 -; GFX1164DAGISEL-NEXT: ; %bb.2: -; GFX1164DAGISEL-NEXT: v_mov_b32_e32 v2, s2 -; GFX1164DAGISEL-NEXT: global_store_b16 v[0:1], v2, off -; GFX1164DAGISEL-NEXT: s_setpc_b64 s[30:31] +; GFX1164DAGISEL-FAKE16-LABEL: divergent_value_i16: +; GFX1164DAGISEL-FAKE16: ; %bb.0: ; %entry +; GFX1164DAGISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1164DAGISEL-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2 +; GFX1164DAGISEL-FAKE16-NEXT: s_mov_b64 s[0:1], exec +; GFX1164DAGISEL-FAKE16-NEXT: s_mov_b32 s2, 0 +; GFX1164DAGISEL-FAKE16-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1 +; GFX1164DAGISEL-FAKE16-NEXT: s_ctz_i32_b64 s3, s[0:1] +; GFX1164DAGISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) +; GFX1164DAGISEL-FAKE16-NEXT: v_readlane_b32 s4, v2, s3 +; GFX1164DAGISEL-FAKE16-NEXT: s_bitset0_b64 s[0:1], s3 +; GFX1164DAGISEL-FAKE16-NEXT: s_max_u32 s2, s2, s4 +; GFX1164DAGISEL-FAKE16-NEXT: s_cmp_lg_u64 s[0:1], 0 +; GFX1164DAGISEL-FAKE16-NEXT: s_cbranch_scc1 .LBB1_1 +; GFX1164DAGISEL-FAKE16-NEXT: ; %bb.2: +; GFX1164DAGISEL-FAKE16-NEXT: v_mov_b32_e32 v2, s2 +; GFX1164DAGISEL-FAKE16-NEXT: global_store_b16 v[0:1], v2, off +; GFX1164DAGISEL-FAKE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX1164GISEL-LABEL: divergent_value_i16: ; GFX1164GISEL: ; %bb.0: ; %entry @@ -313,24 +368,24 @@ define void @divergent_value_i16(ptr addrspace(1) %out, i16 %in) { ; GFX1164GISEL-NEXT: global_store_b16 v[0:1], v2, off ; GFX1164GISEL-NEXT: s_setpc_b64 s[30:31] ; -; GFX1132DAGISEL-LABEL: divergent_value_i16: -; GFX1132DAGISEL: ; %bb.0: ; %entry -; GFX1132DAGISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1132DAGISEL-NEXT: v_and_b32_e32 v2, 0xffff, v2 -; GFX1132DAGISEL-NEXT: s_mov_b32 s1, exec_lo -; GFX1132DAGISEL-NEXT: s_mov_b32 s0, 0 -; GFX1132DAGISEL-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1 -; GFX1132DAGISEL-NEXT: s_ctz_i32_b32 s2, s1 -; GFX1132DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) -; GFX1132DAGISEL-NEXT: v_readlane_b32 s3, v2, s2 -; GFX1132DAGISEL-NEXT: s_bitset0_b32 s1, s2 -; GFX1132DAGISEL-NEXT: s_max_u32 s0, s0, s3 -; GFX1132DAGISEL-NEXT: s_cmp_lg_u32 s1, 0 -; GFX1132DAGISEL-NEXT: s_cbranch_scc1 .LBB1_1 -; GFX1132DAGISEL-NEXT: ; %bb.2: -; GFX1132DAGISEL-NEXT: v_mov_b32_e32 v2, s0 -; GFX1132DAGISEL-NEXT: global_store_b16 v[0:1], v2, off -; GFX1132DAGISEL-NEXT: s_setpc_b64 s[30:31] +; GFX1132DAGISEL-FAKE16-LABEL: divergent_value_i16: +; GFX1132DAGISEL-FAKE16: ; %bb.0: ; %entry +; GFX1132DAGISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1132DAGISEL-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2 +; GFX1132DAGISEL-FAKE16-NEXT: s_mov_b32 s1, exec_lo +; GFX1132DAGISEL-FAKE16-NEXT: s_mov_b32 s0, 0 +; GFX1132DAGISEL-FAKE16-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1 +; GFX1132DAGISEL-FAKE16-NEXT: s_ctz_i32_b32 s2, s1 +; GFX1132DAGISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) +; GFX1132DAGISEL-FAKE16-NEXT: v_readlane_b32 s3, v2, s2 +; GFX1132DAGISEL-FAKE16-NEXT: s_bitset0_b32 s1, s2 +; GFX1132DAGISEL-FAKE16-NEXT: s_max_u32 s0, s0, s3 +; GFX1132DAGISEL-FAKE16-NEXT: s_cmp_lg_u32 s1, 0 +; GFX1132DAGISEL-FAKE16-NEXT: s_cbranch_scc1 .LBB1_1 +; GFX1132DAGISEL-FAKE16-NEXT: ; %bb.2: +; GFX1132DAGISEL-FAKE16-NEXT: v_mov_b32_e32 v2, s0 +; GFX1132DAGISEL-FAKE16-NEXT: global_store_b16 v[0:1], v2, off +; GFX1132DAGISEL-FAKE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX1132GISEL-LABEL: divergent_value_i16: ; GFX1132GISEL: ; %bb.0: ; %entry @@ -350,6 +405,46 @@ define void @divergent_value_i16(ptr addrspace(1) %out, i16 %in) { ; GFX1132GISEL-NEXT: v_mov_b32_e32 v2, s0 ; GFX1132GISEL-NEXT: global_store_b16 v[0:1], v2, off ; GFX1132GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX1164DAGISEL-TRUE16-LABEL: divergent_value_i16: +; GFX1164DAGISEL-TRUE16: ; %bb.0: ; %entry +; GFX1164DAGISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1164DAGISEL-TRUE16-NEXT: v_mov_b16_e32 v3.h, 0 +; GFX1164DAGISEL-TRUE16-NEXT: v_mov_b16_e32 v3.l, v2.l +; GFX1164DAGISEL-TRUE16-NEXT: s_mov_b64 s[0:1], exec +; GFX1164DAGISEL-TRUE16-NEXT: s_mov_b32 s2, 0 +; GFX1164DAGISEL-TRUE16-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1 +; GFX1164DAGISEL-TRUE16-NEXT: s_ctz_i32_b64 s3, s[0:1] +; GFX1164DAGISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) +; GFX1164DAGISEL-TRUE16-NEXT: v_readlane_b32 s4, v3, s3 +; GFX1164DAGISEL-TRUE16-NEXT: s_bitset0_b64 s[0:1], s3 +; GFX1164DAGISEL-TRUE16-NEXT: s_max_u32 s2, s2, s4 +; GFX1164DAGISEL-TRUE16-NEXT: s_cmp_lg_u64 s[0:1], 0 +; GFX1164DAGISEL-TRUE16-NEXT: s_cbranch_scc1 .LBB1_1 +; GFX1164DAGISEL-TRUE16-NEXT: ; %bb.2: +; GFX1164DAGISEL-TRUE16-NEXT: v_mov_b32_e32 v2, s2 +; GFX1164DAGISEL-TRUE16-NEXT: global_store_b16 v[0:1], v2, off +; GFX1164DAGISEL-TRUE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX1132DAGISEL-TRUE16-LABEL: divergent_value_i16: +; GFX1132DAGISEL-TRUE16: ; %bb.0: ; %entry +; GFX1132DAGISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1132DAGISEL-TRUE16-NEXT: v_mov_b16_e32 v3.h, 0 +; GFX1132DAGISEL-TRUE16-NEXT: v_mov_b16_e32 v3.l, v2.l +; GFX1132DAGISEL-TRUE16-NEXT: s_mov_b32 s1, exec_lo +; GFX1132DAGISEL-TRUE16-NEXT: s_mov_b32 s0, 0 +; GFX1132DAGISEL-TRUE16-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1 +; GFX1132DAGISEL-TRUE16-NEXT: s_ctz_i32_b32 s2, s1 +; GFX1132DAGISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) +; GFX1132DAGISEL-TRUE16-NEXT: v_readlane_b32 s3, v3, s2 +; GFX1132DAGISEL-TRUE16-NEXT: s_bitset0_b32 s1, s2 +; GFX1132DAGISEL-TRUE16-NEXT: s_max_u32 s0, s0, s3 +; GFX1132DAGISEL-TRUE16-NEXT: s_cmp_lg_u32 s1, 0 +; GFX1132DAGISEL-TRUE16-NEXT: s_cbranch_scc1 .LBB1_1 +; GFX1132DAGISEL-TRUE16-NEXT: ; %bb.2: +; GFX1132DAGISEL-TRUE16-NEXT: v_mov_b32_e32 v2, s0 +; GFX1132DAGISEL-TRUE16-NEXT: global_store_b16 v[0:1], v2, off +; GFX1132DAGISEL-TRUE16-NEXT: s_setpc_b64 s[30:31] entry: %result = call i16 @llvm.amdgcn.wave.reduce.umax.i16(i16 %in, i32 1) store i16 %result, ptr addrspace(1) %out @@ -3123,10 +3218,24 @@ define amdgpu_kernel void @poison_value_i64(ptr addrspace(1) %out, i64 %in) { ; GFX10GISEL: ; %bb.0: ; %entry ; GFX10GISEL-NEXT: s_endpgm ; +; GFX1164DAGISEL-LABEL: poison_value_i64: +; GFX1164DAGISEL: ; %bb.0: ; %entry +; GFX1164DAGISEL-NEXT: s_endpgm +; +; GFX1164GISEL-LABEL: poison_value_i64: +; GFX1164GISEL: ; %bb.0: ; %entry +; GFX1164GISEL-NEXT: s_endpgm +; +; GFX1132DAGISEL-LABEL: poison_value_i64: +; GFX1132DAGISEL: ; %bb.0: ; %entry +; GFX1132DAGISEL-NEXT: s_endpgm +; +; GFX1132GISEL-LABEL: poison_value_i64: +; GFX1132GISEL: ; %bb.0: ; %entry +; GFX1132GISEL-NEXT: s_endpgm ; GFX11DAGISEL-LABEL: poison_value_i64: ; GFX11DAGISEL: ; %bb.0: ; %entry ; GFX11DAGISEL-NEXT: s_endpgm -; ; GFX11GISEL-LABEL: poison_value_i64: ; GFX11GISEL: ; %bb.0: ; %entry ; GFX11GISEL-NEXT: s_endpgm diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umin.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umin.ll index 78952663672b2..d0dc6da5f89e8 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umin.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umin.ll @@ -7,10 +7,14 @@ ; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX10GISEL,GFX1064GISEL %s ; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=0 < %s | FileCheck -check-prefixes=GFX10DAGISEL,GFX1032DAGISEL %s ; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX10GISEL,GFX1032GISEL %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -global-isel=0 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1164DAGISEL %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1164GISEL %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -global-isel=0 < %s | FileCheck -check-prefixes=GFX1132DAGISEL %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX1132GISEL %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -global-isel=0 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1164DAGISEL,GFX1164DAGISEL-FAKE16 %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1164GISEL,GFX1164GISEL-FAKE16 %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -global-isel=0 < %s | FileCheck -check-prefixes=GFX1132DAGISEL,GFX1132DAGISEL-FAKE16 %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX1132GISEL,GFX1132GISEL-FAKE16 %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -global-isel=0 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1164DAGISEL,GFX1164DAGISEL-TRUE16 %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1164GISEL,GFX1164GISEL-TRUE16 %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -global-isel=0 < %s | FileCheck -check-prefixes=GFX1132DAGISEL,GFX1132DAGISEL-TRUE16 %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX1132GISEL,GFX1132GISEL-TRUE16 %s define amdgpu_kernel void @uniform_value_i16(ptr addrspace(1) %out, i16 %in) { ; GFX8DAGISEL-LABEL: uniform_value_i16: @@ -96,18 +100,18 @@ define amdgpu_kernel void @uniform_value_i16(ptr addrspace(1) %out, i16 %in) { ; GFX1164DAGISEL-NEXT: global_store_b16 v0, v1, s[0:1] ; GFX1164DAGISEL-NEXT: s_endpgm ; -; GFX1164GISEL-LABEL: uniform_value_i16: -; GFX1164GISEL: ; %bb.0: ; %entry -; GFX1164GISEL-NEXT: s_clause 0x1 -; GFX1164GISEL-NEXT: s_load_b32 s2, s[4:5], 0x2c -; GFX1164GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 -; GFX1164GISEL-NEXT: v_mov_b32_e32 v1, 0 -; GFX1164GISEL-NEXT: s_waitcnt lgkmcnt(0) -; GFX1164GISEL-NEXT: s_and_b32 s2, s2, 0xffff -; GFX1164GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX1164GISEL-NEXT: v_mov_b32_e32 v0, s2 -; GFX1164GISEL-NEXT: global_store_b16 v1, v0, s[0:1] -; GFX1164GISEL-NEXT: s_endpgm +; GFX1164GISEL-FAKE16-LABEL: uniform_value_i16: +; GFX1164GISEL-FAKE16: ; %bb.0: ; %entry +; GFX1164GISEL-FAKE16-NEXT: s_clause 0x1 +; GFX1164GISEL-FAKE16-NEXT: s_load_b32 s2, s[4:5], 0x2c +; GFX1164GISEL-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 +; GFX1164GISEL-FAKE16-NEXT: v_mov_b32_e32 v1, 0 +; GFX1164GISEL-FAKE16-NEXT: s_waitcnt lgkmcnt(0) +; GFX1164GISEL-FAKE16-NEXT: s_and_b32 s2, s2, 0xffff +; GFX1164GISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX1164GISEL-FAKE16-NEXT: v_mov_b32_e32 v0, s2 +; GFX1164GISEL-FAKE16-NEXT: global_store_b16 v1, v0, s[0:1] +; GFX1164GISEL-FAKE16-NEXT: s_endpgm ; ; GFX1132DAGISEL-LABEL: uniform_value_i16: ; GFX1132DAGISEL: ; %bb.0: ; %entry @@ -121,18 +125,44 @@ define amdgpu_kernel void @uniform_value_i16(ptr addrspace(1) %out, i16 %in) { ; GFX1132DAGISEL-NEXT: global_store_b16 v0, v1, s[0:1] ; GFX1132DAGISEL-NEXT: s_endpgm ; -; GFX1132GISEL-LABEL: uniform_value_i16: -; GFX1132GISEL: ; %bb.0: ; %entry -; GFX1132GISEL-NEXT: s_clause 0x1 -; GFX1132GISEL-NEXT: s_load_b32 s2, s[4:5], 0x2c -; GFX1132GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 -; GFX1132GISEL-NEXT: v_mov_b32_e32 v1, 0 -; GFX1132GISEL-NEXT: s_waitcnt lgkmcnt(0) -; GFX1132GISEL-NEXT: s_and_b32 s2, s2, 0xffff -; GFX1132GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX1132GISEL-NEXT: v_mov_b32_e32 v0, s2 -; GFX1132GISEL-NEXT: global_store_b16 v1, v0, s[0:1] -; GFX1132GISEL-NEXT: s_endpgm +; GFX1132GISEL-FAKE16-LABEL: uniform_value_i16: +; GFX1132GISEL-FAKE16: ; %bb.0: ; %entry +; GFX1132GISEL-FAKE16-NEXT: s_clause 0x1 +; GFX1132GISEL-FAKE16-NEXT: s_load_b32 s2, s[4:5], 0x2c +; GFX1132GISEL-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 +; GFX1132GISEL-FAKE16-NEXT: v_mov_b32_e32 v1, 0 +; GFX1132GISEL-FAKE16-NEXT: s_waitcnt lgkmcnt(0) +; GFX1132GISEL-FAKE16-NEXT: s_and_b32 s2, s2, 0xffff +; GFX1132GISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX1132GISEL-FAKE16-NEXT: v_mov_b32_e32 v0, s2 +; GFX1132GISEL-FAKE16-NEXT: global_store_b16 v1, v0, s[0:1] +; GFX1132GISEL-FAKE16-NEXT: s_endpgm +; +; GFX1164GISEL-TRUE16-LABEL: uniform_value_i16: +; GFX1164GISEL-TRUE16: ; %bb.0: ; %entry +; GFX1164GISEL-TRUE16-NEXT: s_clause 0x1 +; GFX1164GISEL-TRUE16-NEXT: s_load_b32 s2, s[4:5], 0x2c +; GFX1164GISEL-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 +; GFX1164GISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 0 +; GFX1164GISEL-TRUE16-NEXT: s_waitcnt lgkmcnt(0) +; GFX1164GISEL-TRUE16-NEXT: s_and_b32 s2, s2, 0xffff +; GFX1164GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX1164GISEL-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2 +; GFX1164GISEL-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1] +; GFX1164GISEL-TRUE16-NEXT: s_endpgm +; +; GFX1132GISEL-TRUE16-LABEL: uniform_value_i16: +; GFX1132GISEL-TRUE16: ; %bb.0: ; %entry +; GFX1132GISEL-TRUE16-NEXT: s_clause 0x1 +; GFX1132GISEL-TRUE16-NEXT: s_load_b32 s2, s[4:5], 0x2c +; GFX1132GISEL-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 +; GFX1132GISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 0 +; GFX1132GISEL-TRUE16-NEXT: s_waitcnt lgkmcnt(0) +; GFX1132GISEL-TRUE16-NEXT: s_and_b32 s2, s2, 0xffff +; GFX1132GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX1132GISEL-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2 +; GFX1132GISEL-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1] +; GFX1132GISEL-TRUE16-NEXT: s_endpgm entry: %result = call i16 @llvm.amdgcn.wave.reduce.umin.i16(i16 %in, i32 1) store i16 %result, ptr addrspace(1) %out @@ -288,24 +318,24 @@ define void @divergent_value_i16(ptr addrspace(1) %out, i16 %in) { ; GFX1032GISEL-NEXT: global_store_short v[0:1], v2, off ; GFX1032GISEL-NEXT: s_setpc_b64 s[30:31] ; -; GFX1164DAGISEL-LABEL: divergent_value_i16: -; GFX1164DAGISEL: ; %bb.0: ; %entry -; GFX1164DAGISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1164DAGISEL-NEXT: v_and_b32_e32 v2, 0xffff, v2 -; GFX1164DAGISEL-NEXT: s_mov_b64 s[0:1], exec -; GFX1164DAGISEL-NEXT: s_mov_b32 s2, -1 -; GFX1164DAGISEL-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1 -; GFX1164DAGISEL-NEXT: s_ctz_i32_b64 s3, s[0:1] -; GFX1164DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) -; GFX1164DAGISEL-NEXT: v_readlane_b32 s4, v2, s3 -; GFX1164DAGISEL-NEXT: s_bitset0_b64 s[0:1], s3 -; GFX1164DAGISEL-NEXT: s_min_u32 s2, s2, s4 -; GFX1164DAGISEL-NEXT: s_cmp_lg_u64 s[0:1], 0 -; GFX1164DAGISEL-NEXT: s_cbranch_scc1 .LBB1_1 -; GFX1164DAGISEL-NEXT: ; %bb.2: -; GFX1164DAGISEL-NEXT: v_mov_b32_e32 v2, s2 -; GFX1164DAGISEL-NEXT: global_store_b16 v[0:1], v2, off -; GFX1164DAGISEL-NEXT: s_setpc_b64 s[30:31] +; GFX1164DAGISEL-FAKE16-LABEL: divergent_value_i16: +; GFX1164DAGISEL-FAKE16: ; %bb.0: ; %entry +; GFX1164DAGISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1164DAGISEL-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2 +; GFX1164DAGISEL-FAKE16-NEXT: s_mov_b64 s[0:1], exec +; GFX1164DAGISEL-FAKE16-NEXT: s_mov_b32 s2, -1 +; GFX1164DAGISEL-FAKE16-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1 +; GFX1164DAGISEL-FAKE16-NEXT: s_ctz_i32_b64 s3, s[0:1] +; GFX1164DAGISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) +; GFX1164DAGISEL-FAKE16-NEXT: v_readlane_b32 s4, v2, s3 +; GFX1164DAGISEL-FAKE16-NEXT: s_bitset0_b64 s[0:1], s3 +; GFX1164DAGISEL-FAKE16-NEXT: s_min_u32 s2, s2, s4 +; GFX1164DAGISEL-FAKE16-NEXT: s_cmp_lg_u64 s[0:1], 0 +; GFX1164DAGISEL-FAKE16-NEXT: s_cbranch_scc1 .LBB1_1 +; GFX1164DAGISEL-FAKE16-NEXT: ; %bb.2: +; GFX1164DAGISEL-FAKE16-NEXT: v_mov_b32_e32 v2, s2 +; GFX1164DAGISEL-FAKE16-NEXT: global_store_b16 v[0:1], v2, off +; GFX1164DAGISEL-FAKE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX1164GISEL-LABEL: divergent_value_i16: ; GFX1164GISEL: ; %bb.0: ; %entry @@ -326,24 +356,24 @@ define void @divergent_value_i16(ptr addrspace(1) %out, i16 %in) { ; GFX1164GISEL-NEXT: global_store_b16 v[0:1], v2, off ; GFX1164GISEL-NEXT: s_setpc_b64 s[30:31] ; -; GFX1132DAGISEL-LABEL: divergent_value_i16: -; GFX1132DAGISEL: ; %bb.0: ; %entry -; GFX1132DAGISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1132DAGISEL-NEXT: v_and_b32_e32 v2, 0xffff, v2 -; GFX1132DAGISEL-NEXT: s_mov_b32 s1, exec_lo -; GFX1132DAGISEL-NEXT: s_mov_b32 s0, -1 -; GFX1132DAGISEL-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1 -; GFX1132DAGISEL-NEXT: s_ctz_i32_b32 s2, s1 -; GFX1132DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) -; GFX1132DAGISEL-NEXT: v_readlane_b32 s3, v2, s2 -; GFX1132DAGISEL-NEXT: s_bitset0_b32 s1, s2 -; GFX1132DAGISEL-NEXT: s_min_u32 s0, s0, s3 -; GFX1132DAGISEL-NEXT: s_cmp_lg_u32 s1, 0 -; GFX1132DAGISEL-NEXT: s_cbranch_scc1 .LBB1_1 -; GFX1132DAGISEL-NEXT: ; %bb.2: -; GFX1132DAGISEL-NEXT: v_mov_b32_e32 v2, s0 -; GFX1132DAGISEL-NEXT: global_store_b16 v[0:1], v2, off -; GFX1132DAGISEL-NEXT: s_setpc_b64 s[30:31] +; GFX1132DAGISEL-FAKE16-LABEL: divergent_value_i16: +; GFX1132DAGISEL-FAKE16: ; %bb.0: ; %entry +; GFX1132DAGISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1132DAGISEL-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2 +; GFX1132DAGISEL-FAKE16-NEXT: s_mov_b32 s1, exec_lo +; GFX1132DAGISEL-FAKE16-NEXT: s_mov_b32 s0, -1 +; GFX1132DAGISEL-FAKE16-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1 +; GFX1132DAGISEL-FAKE16-NEXT: s_ctz_i32_b32 s2, s1 +; GFX1132DAGISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) +; GFX1132DAGISEL-FAKE16-NEXT: v_readlane_b32 s3, v2, s2 +; GFX1132DAGISEL-FAKE16-NEXT: s_bitset0_b32 s1, s2 +; GFX1132DAGISEL-FAKE16-NEXT: s_min_u32 s0, s0, s3 +; GFX1132DAGISEL-FAKE16-NEXT: s_cmp_lg_u32 s1, 0 +; GFX1132DAGISEL-FAKE16-NEXT: s_cbranch_scc1 .LBB1_1 +; GFX1132DAGISEL-FAKE16-NEXT: ; %bb.2: +; GFX1132DAGISEL-FAKE16-NEXT: v_mov_b32_e32 v2, s0 +; GFX1132DAGISEL-FAKE16-NEXT: global_store_b16 v[0:1], v2, off +; GFX1132DAGISEL-FAKE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX1132GISEL-LABEL: divergent_value_i16: ; GFX1132GISEL: ; %bb.0: ; %entry @@ -363,6 +393,46 @@ define void @divergent_value_i16(ptr addrspace(1) %out, i16 %in) { ; GFX1132GISEL-NEXT: v_mov_b32_e32 v2, s0 ; GFX1132GISEL-NEXT: global_store_b16 v[0:1], v2, off ; GFX1132GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX1164DAGISEL-TRUE16-LABEL: divergent_value_i16: +; GFX1164DAGISEL-TRUE16: ; %bb.0: ; %entry +; GFX1164DAGISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1164DAGISEL-TRUE16-NEXT: v_mov_b16_e32 v3.h, 0 +; GFX1164DAGISEL-TRUE16-NEXT: v_mov_b16_e32 v3.l, v2.l +; GFX1164DAGISEL-TRUE16-NEXT: s_mov_b64 s[0:1], exec +; GFX1164DAGISEL-TRUE16-NEXT: s_mov_b32 s2, -1 +; GFX1164DAGISEL-TRUE16-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1 +; GFX1164DAGISEL-TRUE16-NEXT: s_ctz_i32_b64 s3, s[0:1] +; GFX1164DAGISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) +; GFX1164DAGISEL-TRUE16-NEXT: v_readlane_b32 s4, v3, s3 +; GFX1164DAGISEL-TRUE16-NEXT: s_bitset0_b64 s[0:1], s3 +; GFX1164DAGISEL-TRUE16-NEXT: s_min_u32 s2, s2, s4 +; GFX1164DAGISEL-TRUE16-NEXT: s_cmp_lg_u64 s[0:1], 0 +; GFX1164DAGISEL-TRUE16-NEXT: s_cbranch_scc1 .LBB1_1 +; GFX1164DAGISEL-TRUE16-NEXT: ; %bb.2: +; GFX1164DAGISEL-TRUE16-NEXT: v_mov_b32_e32 v2, s2 +; GFX1164DAGISEL-TRUE16-NEXT: global_store_b16 v[0:1], v2, off +; GFX1164DAGISEL-TRUE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX1132DAGISEL-TRUE16-LABEL: divergent_value_i16: +; GFX1132DAGISEL-TRUE16: ; %bb.0: ; %entry +; GFX1132DAGISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1132DAGISEL-TRUE16-NEXT: v_mov_b16_e32 v3.h, 0 +; GFX1132DAGISEL-TRUE16-NEXT: v_mov_b16_e32 v3.l, v2.l +; GFX1132DAGISEL-TRUE16-NEXT: s_mov_b32 s1, exec_lo +; GFX1132DAGISEL-TRUE16-NEXT: s_mov_b32 s0, -1 +; GFX1132DAGISEL-TRUE16-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1 +; GFX1132DAGISEL-TRUE16-NEXT: s_ctz_i32_b32 s2, s1 +; GFX1132DAGISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) +; GFX1132DAGISEL-TRUE16-NEXT: v_readlane_b32 s3, v3, s2 +; GFX1132DAGISEL-TRUE16-NEXT: s_bitset0_b32 s1, s2 +; GFX1132DAGISEL-TRUE16-NEXT: s_min_u32 s0, s0, s3 +; GFX1132DAGISEL-TRUE16-NEXT: s_cmp_lg_u32 s1, 0 +; GFX1132DAGISEL-TRUE16-NEXT: s_cbranch_scc1 .LBB1_1 +; GFX1132DAGISEL-TRUE16-NEXT: ; %bb.2: +; GFX1132DAGISEL-TRUE16-NEXT: v_mov_b32_e32 v2, s0 +; GFX1132DAGISEL-TRUE16-NEXT: global_store_b16 v[0:1], v2, off +; GFX1132DAGISEL-TRUE16-NEXT: s_setpc_b64 s[30:31] entry: %result = call i16 @llvm.amdgcn.wave.reduce.umin.i16(i16 %in, i32 1) store i16 %result, ptr addrspace(1) %out >From 591e6bfbee7aba8ccc2cba89fe1f3170fe43fa7a Mon Sep 17 00:00:00 2001 From: Aaditya <[email protected]> Date: Mon, 4 May 2026 14:07:53 +0530 Subject: [PATCH 2/2] Use `REG_SEQUENCE` instead of `COPY` Use SALU opcodes for all reductions --- llvm/lib/Target/AMDGPU/SIInstructions.td | 3 +-- llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.min.ll | 1 + 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td index 7c5fbe488916d..3f89ebc55fc83 100644 --- a/llvm/lib/Target/AMDGPU/SIInstructions.td +++ b/llvm/lib/Target/AMDGPU/SIInstructions.td @@ -351,8 +351,7 @@ def : GCNPat<(i32 (int_amdgcn_set_inactive_chain_arg i32:$src, i32:$inactive)), multiclass AMDGPUWaveReducePseudoGenerator<string Op, string DataType, ValueType ty, RegisterClass RetReg, SrcRegOrImm9 Reg> { - let usesCustomInserter = 1, hasSideEffects = 0, mayLoad = 0, mayStore = 0, - UseNamedOperandTable = 1, Uses = [EXEC] in { + let usesCustomInserter = 1, hasSideEffects = 0, mayLoad = 0, mayStore = 0, UseNamedOperandTable = 1, Uses = [EXEC] in { def !toupper(Op) #"_PSEUDO_" #DataType : VPseudoInstSI<(outs RetReg : $sdst), (ins Reg : $src, i32imm : $strategy), diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.min.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.min.ll index d0f49a0e0b28c..91f6c5bf58449 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.min.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.min.ll @@ -15,6 +15,7 @@ ; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1164GISEL,GFX1164GISEL-TRUE16 %s ; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -global-isel=0 < %s | FileCheck -check-prefixes=GFX1132DAGISEL,GFX1132DAGISEL-TRUE16 %s ; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX1132GISEL,GFX1132GISEL-TRUE16 %s + define amdgpu_kernel void @uniform_value_i16(ptr addrspace(1) %out, i16 %in) { ; GFX8DAGISEL-LABEL: uniform_value_i16: ; GFX8DAGISEL: ; %bb.0: ; %entry _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
