https://github.com/heiher created https://github.com/llvm/llvm-project/pull/202601
None >From 7768102a79beb6566fcc23a7ea0be844fe5183c9 Mon Sep 17 00:00:00 2001 From: WANG Rui <[email protected]> Date: Fri, 5 Jun 2026 15:23:41 +0800 Subject: [PATCH] [LoongArch][NFC] Add widening shift-left tests --- llvm/test/CodeGen/LoongArch/lasx/vsllwil.ll | 205 ++++++++++++++++++++ llvm/test/CodeGen/LoongArch/lsx/vsllwil.ll | 89 +++++++++ 2 files changed, 294 insertions(+) create mode 100644 llvm/test/CodeGen/LoongArch/lasx/vsllwil.ll create mode 100644 llvm/test/CodeGen/LoongArch/lsx/vsllwil.ll diff --git a/llvm/test/CodeGen/LoongArch/lasx/vsllwil.ll b/llvm/test/CodeGen/LoongArch/lasx/vsllwil.ll new file mode 100644 index 0000000000000..b85c3310d9525 --- /dev/null +++ b/llvm/test/CodeGen/LoongArch/lasx/vsllwil.ll @@ -0,0 +1,205 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s +; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s + +define <16 x i16> @vsllwil_h_b(<32 x i8> %a) nounwind { +; CHECK-LABEL: vsllwil_h_b: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 0 +; CHECK-NEXT: vinsgr2vr.b $vr1, $a0, 0 +; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 1 +; CHECK-NEXT: vinsgr2vr.b $vr1, $a0, 1 +; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 2 +; CHECK-NEXT: vinsgr2vr.b $vr1, $a0, 2 +; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 3 +; CHECK-NEXT: vinsgr2vr.b $vr1, $a0, 3 +; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 4 +; CHECK-NEXT: vinsgr2vr.b $vr1, $a0, 4 +; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 5 +; CHECK-NEXT: vinsgr2vr.b $vr1, $a0, 5 +; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 6 +; CHECK-NEXT: vinsgr2vr.b $vr1, $a0, 6 +; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 7 +; CHECK-NEXT: vinsgr2vr.b $vr1, $a0, 7 +; CHECK-NEXT: xvpermi.d $xr0, $xr0, 14 +; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 0 +; CHECK-NEXT: vinsgr2vr.b $vr1, $a0, 8 +; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 1 +; CHECK-NEXT: vinsgr2vr.b $vr1, $a0, 9 +; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 2 +; CHECK-NEXT: vinsgr2vr.b $vr1, $a0, 10 +; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 3 +; CHECK-NEXT: vinsgr2vr.b $vr1, $a0, 11 +; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 4 +; CHECK-NEXT: vinsgr2vr.b $vr1, $a0, 12 +; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 5 +; CHECK-NEXT: vinsgr2vr.b $vr1, $a0, 13 +; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 6 +; CHECK-NEXT: vinsgr2vr.b $vr1, $a0, 14 +; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 7 +; CHECK-NEXT: vinsgr2vr.b $vr1, $a0, 15 +; CHECK-NEXT: vext2xv.h.b $xr0, $xr1 +; CHECK-NEXT: xvslli.h $xr0, $xr0, 1 +; CHECK-NEXT: ret +entry: + %0 = shufflevector <32 x i8> %a, <32 x i8> poison, + <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, + i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23> + %1 = sext <16 x i8> %0 to <16 x i16> + %2 = shl nsw <16 x i16> %1, splat (i16 1) + ret <16 x i16> %2 +} + +define <8 x i32> @vsllwil_w_h(<16 x i16> %a) nounwind { +; CHECK-LABEL: vsllwil_w_h: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 0 +; CHECK-NEXT: vinsgr2vr.h $vr1, $a0, 0 +; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 1 +; CHECK-NEXT: vinsgr2vr.h $vr1, $a0, 1 +; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 2 +; CHECK-NEXT: vinsgr2vr.h $vr1, $a0, 2 +; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 3 +; CHECK-NEXT: vinsgr2vr.h $vr1, $a0, 3 +; CHECK-NEXT: xvpermi.d $xr0, $xr0, 14 +; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 0 +; CHECK-NEXT: vinsgr2vr.h $vr1, $a0, 4 +; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 1 +; CHECK-NEXT: vinsgr2vr.h $vr1, $a0, 5 +; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 2 +; CHECK-NEXT: vinsgr2vr.h $vr1, $a0, 6 +; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 3 +; CHECK-NEXT: vinsgr2vr.h $vr1, $a0, 7 +; CHECK-NEXT: vext2xv.w.h $xr0, $xr1 +; CHECK-NEXT: xvslli.w $xr0, $xr0, 15 +; CHECK-NEXT: ret +entry: + %0 = shufflevector <16 x i16> %a, <16 x i16> poison, + <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11> + %1 = sext <8 x i16> %0 to <8 x i32> + %2 = shl nsw <8 x i32> %1, splat (i32 15) + ret <8 x i32> %2 +} + +define <4 x i64> @vsllwil_d_w(<8 x i32> %a) nounwind { +; CHECK-LABEL: vsllwil_d_w: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvpickve2gr.w $a0, $xr0, 0 +; CHECK-NEXT: vinsgr2vr.w $vr1, $a0, 0 +; CHECK-NEXT: xvpickve2gr.w $a0, $xr0, 1 +; CHECK-NEXT: vinsgr2vr.w $vr1, $a0, 1 +; CHECK-NEXT: xvpickve2gr.w $a0, $xr0, 4 +; CHECK-NEXT: vinsgr2vr.w $vr1, $a0, 2 +; CHECK-NEXT: xvpickve2gr.w $a0, $xr0, 5 +; CHECK-NEXT: vinsgr2vr.w $vr1, $a0, 3 +; CHECK-NEXT: vext2xv.d.w $xr0, $xr1 +; CHECK-NEXT: xvslli.d $xr0, $xr0, 31 +; CHECK-NEXT: ret +entry: + %0 = shufflevector <8 x i32> %a, <8 x i32> poison, + <4 x i32> <i32 0, i32 1, i32 4, i32 5> + %1 = sext <4 x i32> %0 to <4 x i64> + %2 = shl nsw <4 x i64> %1, splat (i64 31) + ret <4 x i64> %2 +} + +define <16 x i16> @vsllwil_hu_bu(<32 x i8> %a) nounwind { +; CHECK-LABEL: vsllwil_hu_bu: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 0 +; CHECK-NEXT: vinsgr2vr.b $vr1, $a0, 0 +; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 1 +; CHECK-NEXT: vinsgr2vr.b $vr1, $a0, 1 +; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 2 +; CHECK-NEXT: vinsgr2vr.b $vr1, $a0, 2 +; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 3 +; CHECK-NEXT: vinsgr2vr.b $vr1, $a0, 3 +; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 4 +; CHECK-NEXT: vinsgr2vr.b $vr1, $a0, 4 +; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 5 +; CHECK-NEXT: vinsgr2vr.b $vr1, $a0, 5 +; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 6 +; CHECK-NEXT: vinsgr2vr.b $vr1, $a0, 6 +; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 7 +; CHECK-NEXT: vinsgr2vr.b $vr1, $a0, 7 +; CHECK-NEXT: xvpermi.d $xr0, $xr0, 14 +; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 0 +; CHECK-NEXT: vinsgr2vr.b $vr1, $a0, 8 +; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 1 +; CHECK-NEXT: vinsgr2vr.b $vr1, $a0, 9 +; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 2 +; CHECK-NEXT: vinsgr2vr.b $vr1, $a0, 10 +; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 3 +; CHECK-NEXT: vinsgr2vr.b $vr1, $a0, 11 +; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 4 +; CHECK-NEXT: vinsgr2vr.b $vr1, $a0, 12 +; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 5 +; CHECK-NEXT: vinsgr2vr.b $vr1, $a0, 13 +; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 6 +; CHECK-NEXT: vinsgr2vr.b $vr1, $a0, 14 +; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 7 +; CHECK-NEXT: vinsgr2vr.b $vr1, $a0, 15 +; CHECK-NEXT: vext2xv.hu.bu $xr0, $xr1 +; CHECK-NEXT: xvslli.h $xr0, $xr0, 1 +; CHECK-NEXT: ret +entry: + %0 = shufflevector <32 x i8> %a, <32 x i8> poison, + <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, + i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23> + %1 = zext <16 x i8> %0 to <16 x i16> + %2 = shl nsw <16 x i16> %1, splat (i16 1) + ret <16 x i16> %2 +} + +define <8 x i32> @vsllwil_wu_hu(<16 x i16> %a) nounwind { +; CHECK-LABEL: vsllwil_wu_hu: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 0 +; CHECK-NEXT: vinsgr2vr.h $vr1, $a0, 0 +; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 1 +; CHECK-NEXT: vinsgr2vr.h $vr1, $a0, 1 +; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 2 +; CHECK-NEXT: vinsgr2vr.h $vr1, $a0, 2 +; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 3 +; CHECK-NEXT: vinsgr2vr.h $vr1, $a0, 3 +; CHECK-NEXT: xvpermi.d $xr0, $xr0, 14 +; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 0 +; CHECK-NEXT: vinsgr2vr.h $vr1, $a0, 4 +; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 1 +; CHECK-NEXT: vinsgr2vr.h $vr1, $a0, 5 +; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 2 +; CHECK-NEXT: vinsgr2vr.h $vr1, $a0, 6 +; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 3 +; CHECK-NEXT: vinsgr2vr.h $vr1, $a0, 7 +; CHECK-NEXT: vext2xv.wu.hu $xr0, $xr1 +; CHECK-NEXT: xvslli.w $xr0, $xr0, 15 +; CHECK-NEXT: ret +entry: + %0 = shufflevector <16 x i16> %a, <16 x i16> poison, + <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11> + %1 = zext <8 x i16> %0 to <8 x i32> + %2 = shl nsw <8 x i32> %1, splat (i32 15) + ret <8 x i32> %2 +} + +define <4 x i64> @vsllwil_du_wu(<8 x i32> %a) nounwind { +; CHECK-LABEL: vsllwil_du_wu: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvpickve2gr.w $a0, $xr0, 0 +; CHECK-NEXT: vinsgr2vr.w $vr1, $a0, 0 +; CHECK-NEXT: xvpickve2gr.w $a0, $xr0, 1 +; CHECK-NEXT: vinsgr2vr.w $vr1, $a0, 1 +; CHECK-NEXT: xvpickve2gr.w $a0, $xr0, 4 +; CHECK-NEXT: vinsgr2vr.w $vr1, $a0, 2 +; CHECK-NEXT: xvpickve2gr.w $a0, $xr0, 5 +; CHECK-NEXT: vinsgr2vr.w $vr1, $a0, 3 +; CHECK-NEXT: vext2xv.du.wu $xr0, $xr1 +; CHECK-NEXT: xvslli.d $xr0, $xr0, 31 +; CHECK-NEXT: ret +entry: + %0 = shufflevector <8 x i32> %a, <8 x i32> poison, + <4 x i32> <i32 0, i32 1, i32 4, i32 5> + %1 = zext <4 x i32> %0 to <4 x i64> + %2 = shl nsw <4 x i64> %1, splat (i64 31) + ret <4 x i64> %2 +} diff --git a/llvm/test/CodeGen/LoongArch/lsx/vsllwil.ll b/llvm/test/CodeGen/LoongArch/lsx/vsllwil.ll new file mode 100644 index 0000000000000..597c5cecb844a --- /dev/null +++ b/llvm/test/CodeGen/LoongArch/lsx/vsllwil.ll @@ -0,0 +1,89 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s +; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s + +define <8 x i16> @vsllwil_h_b(<16 x i8> %a) nounwind { +; CHECK-LABEL: vsllwil_h_b: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vslti.b $vr1, $vr0, 0 +; CHECK-NEXT: vilvl.b $vr0, $vr1, $vr0 +; CHECK-NEXT: vslli.h $vr0, $vr0, 1 +; CHECK-NEXT: ret +entry: + %0 = shufflevector <16 x i8> %a, <16 x i8> poison, + <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> + %1 = sext <8 x i8> %0 to <8 x i16> + %2 = shl nsw <8 x i16> %1, splat (i16 1) + ret <8 x i16> %2 +} + +define <4 x i32> @vsllwil_w_h(<8 x i16> %a) nounwind { +; CHECK-LABEL: vsllwil_w_h: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vslti.h $vr1, $vr0, 0 +; CHECK-NEXT: vilvl.h $vr0, $vr1, $vr0 +; CHECK-NEXT: vslli.w $vr0, $vr0, 15 +; CHECK-NEXT: ret +entry: + %0 = shufflevector <8 x i16> %a, <8 x i16> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3> + %1 = sext <4 x i16> %0 to <4 x i32> + %2 = shl nsw <4 x i32> %1, splat (i32 15) + ret <4 x i32> %2 +} + +define <2 x i64> @vsllwil_d_w(<4 x i32> %a) nounwind { +; CHECK-LABEL: vsllwil_d_w: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vslti.w $vr1, $vr0, 0 +; CHECK-NEXT: vilvl.w $vr0, $vr1, $vr0 +; CHECK-NEXT: vslli.d $vr0, $vr0, 31 +; CHECK-NEXT: ret +entry: + %0 = shufflevector <4 x i32> %a, <4 x i32> poison, <2 x i32> <i32 0, i32 1> + %1 = sext <2 x i32> %0 to <2 x i64> + %2 = shl nsw <2 x i64> %1, splat (i64 31) + ret <2 x i64> %2 +} + +define <8 x i16> @vsllwil_hu_bu(<16 x i8> %a) nounwind { +; CHECK-LABEL: vsllwil_hu_bu: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vrepli.b $vr1, 0 +; CHECK-NEXT: vilvl.b $vr0, $vr1, $vr0 +; CHECK-NEXT: vslli.h $vr0, $vr0, 1 +; CHECK-NEXT: ret +entry: + %0 = shufflevector <16 x i8> %a, <16 x i8> poison, + <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> + %1 = zext <8 x i8> %0 to <8 x i16> + %2 = shl nsw <8 x i16> %1, splat (i16 1) + ret <8 x i16> %2 +} + +define <4 x i32> @vsllwil_wu_hu(<8 x i16> %a) nounwind { +; CHECK-LABEL: vsllwil_wu_hu: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vrepli.b $vr1, 0 +; CHECK-NEXT: vilvl.h $vr0, $vr1, $vr0 +; CHECK-NEXT: vslli.w $vr0, $vr0, 15 +; CHECK-NEXT: ret +entry: + %0 = shufflevector <8 x i16> %a, <8 x i16> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3> + %1 = zext <4 x i16> %0 to <4 x i32> + %2 = shl nsw <4 x i32> %1, splat (i32 15) + ret <4 x i32> %2 +} + +define <2 x i64> @vsllwil_du_wu(<4 x i32> %a) nounwind { +; CHECK-LABEL: vsllwil_du_wu: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vrepli.b $vr1, 0 +; CHECK-NEXT: vilvl.w $vr0, $vr1, $vr0 +; CHECK-NEXT: vslli.d $vr0, $vr0, 31 +; CHECK-NEXT: ret +entry: + %0 = shufflevector <4 x i32> %a, <4 x i32> poison, <2 x i32> <i32 0, i32 1> + %1 = zext <2 x i32> %0 to <2 x i64> + %2 = shl nsw <2 x i64> %1, splat (i64 31) + ret <2 x i64> %2 +} _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
