https://github.com/easyonaadit updated https://github.com/llvm/llvm-project/pull/194813
>From 60b6529ca535dfe8ffc8ba689354454473ecc216 Mon Sep 17 00:00:00 2001 From: Aaditya <[email protected]> Date: Fri, 29 May 2026 14:34:40 +0530 Subject: [PATCH] Modify test run lines --- .../CodeGen/AMDGPU/llvm.amdgcn.reduce.and.ll | 198 ++++++++++----- .../CodeGen/AMDGPU/llvm.amdgcn.reduce.or.ll | 198 ++++++++++----- .../CodeGen/AMDGPU/llvm.amdgcn.reduce.xor.ll | 228 ++++++++++++------ 3 files changed, 422 insertions(+), 202 deletions(-) diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.and.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.and.ll index 6814b4858c874..317b00d7d5e3d 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.and.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.and.ll @@ -7,10 +7,14 @@ ; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX10GISEL,GFX1064GISEL %s ; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=0 < %s | FileCheck -check-prefixes=GFX10DAGISEL,GFX1032DAGISEL %s ; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX10GISEL,GFX1032GISEL %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -global-isel=0 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1164DAGISEL %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1164GISEL %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -global-isel=0 < %s | FileCheck -check-prefixes=GFX1132DAGISEL %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX1132GISEL %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -global-isel=0 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1164DAGISEL,GFX1164DAGISEL-FAKE16 %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1164GISEL,GFX1164GISEL-FAKE16 %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -global-isel=0 < %s | FileCheck -check-prefixes=GFX1132DAGISEL,GFX1132DAGISEL-FAKE16 %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX1132GISEL,GFX1132GISEL-FAKE16 %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -global-isel=0 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1164DAGISEL,GFX1164DAGISEL-TRUE16 %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1164GISEL,GFX1164GISEL-TRUE16 %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -global-isel=0 < %s | FileCheck -check-prefixes=GFX1132DAGISEL,GFX1132DAGISEL-TRUE16 %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX1132GISEL,GFX1132GISEL-TRUE16 %s define amdgpu_kernel void @uniform_value_i16(ptr addrspace(1) %out, i16 %in) { ; GFX8DAGISEL-LABEL: uniform_value_i16: @@ -96,18 +100,18 @@ define amdgpu_kernel void @uniform_value_i16(ptr addrspace(1) %out, i16 %in) { ; GFX1164DAGISEL-NEXT: global_store_b16 v0, v1, s[0:1] ; GFX1164DAGISEL-NEXT: s_endpgm ; -; GFX1164GISEL-LABEL: uniform_value_i16: -; GFX1164GISEL: ; %bb.0: ; %entry -; GFX1164GISEL-NEXT: s_clause 0x1 -; GFX1164GISEL-NEXT: s_load_b32 s2, s[4:5], 0x2c -; GFX1164GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 -; GFX1164GISEL-NEXT: v_mov_b32_e32 v1, 0 -; GFX1164GISEL-NEXT: s_waitcnt lgkmcnt(0) -; GFX1164GISEL-NEXT: s_and_b32 s2, s2, 0xffff -; GFX1164GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX1164GISEL-NEXT: v_mov_b32_e32 v0, s2 -; GFX1164GISEL-NEXT: global_store_b16 v1, v0, s[0:1] -; GFX1164GISEL-NEXT: s_endpgm +; GFX1164GISEL-FAKE16-LABEL: uniform_value_i16: +; GFX1164GISEL-FAKE16: ; %bb.0: ; %entry +; GFX1164GISEL-FAKE16-NEXT: s_clause 0x1 +; GFX1164GISEL-FAKE16-NEXT: s_load_b32 s2, s[4:5], 0x2c +; GFX1164GISEL-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 +; GFX1164GISEL-FAKE16-NEXT: v_mov_b32_e32 v1, 0 +; GFX1164GISEL-FAKE16-NEXT: s_waitcnt lgkmcnt(0) +; GFX1164GISEL-FAKE16-NEXT: s_and_b32 s2, s2, 0xffff +; GFX1164GISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX1164GISEL-FAKE16-NEXT: v_mov_b32_e32 v0, s2 +; GFX1164GISEL-FAKE16-NEXT: global_store_b16 v1, v0, s[0:1] +; GFX1164GISEL-FAKE16-NEXT: s_endpgm ; ; GFX1132DAGISEL-LABEL: uniform_value_i16: ; GFX1132DAGISEL: ; %bb.0: ; %entry @@ -121,18 +125,44 @@ define amdgpu_kernel void @uniform_value_i16(ptr addrspace(1) %out, i16 %in) { ; GFX1132DAGISEL-NEXT: global_store_b16 v0, v1, s[0:1] ; GFX1132DAGISEL-NEXT: s_endpgm ; -; GFX1132GISEL-LABEL: uniform_value_i16: -; GFX1132GISEL: ; %bb.0: ; %entry -; GFX1132GISEL-NEXT: s_clause 0x1 -; GFX1132GISEL-NEXT: s_load_b32 s2, s[4:5], 0x2c -; GFX1132GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 -; GFX1132GISEL-NEXT: v_mov_b32_e32 v1, 0 -; GFX1132GISEL-NEXT: s_waitcnt lgkmcnt(0) -; GFX1132GISEL-NEXT: s_and_b32 s2, s2, 0xffff -; GFX1132GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX1132GISEL-NEXT: v_mov_b32_e32 v0, s2 -; GFX1132GISEL-NEXT: global_store_b16 v1, v0, s[0:1] -; GFX1132GISEL-NEXT: s_endpgm +; GFX1132GISEL-FAKE16-LABEL: uniform_value_i16: +; GFX1132GISEL-FAKE16: ; %bb.0: ; %entry +; GFX1132GISEL-FAKE16-NEXT: s_clause 0x1 +; GFX1132GISEL-FAKE16-NEXT: s_load_b32 s2, s[4:5], 0x2c +; GFX1132GISEL-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 +; GFX1132GISEL-FAKE16-NEXT: v_mov_b32_e32 v1, 0 +; GFX1132GISEL-FAKE16-NEXT: s_waitcnt lgkmcnt(0) +; GFX1132GISEL-FAKE16-NEXT: s_and_b32 s2, s2, 0xffff +; GFX1132GISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX1132GISEL-FAKE16-NEXT: v_mov_b32_e32 v0, s2 +; GFX1132GISEL-FAKE16-NEXT: global_store_b16 v1, v0, s[0:1] +; GFX1132GISEL-FAKE16-NEXT: s_endpgm +; +; GFX1164GISEL-TRUE16-LABEL: uniform_value_i16: +; GFX1164GISEL-TRUE16: ; %bb.0: ; %entry +; GFX1164GISEL-TRUE16-NEXT: s_clause 0x1 +; GFX1164GISEL-TRUE16-NEXT: s_load_b32 s2, s[4:5], 0x2c +; GFX1164GISEL-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 +; GFX1164GISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 0 +; GFX1164GISEL-TRUE16-NEXT: s_waitcnt lgkmcnt(0) +; GFX1164GISEL-TRUE16-NEXT: s_and_b32 s2, s2, 0xffff +; GFX1164GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX1164GISEL-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2 +; GFX1164GISEL-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1] +; GFX1164GISEL-TRUE16-NEXT: s_endpgm +; +; GFX1132GISEL-TRUE16-LABEL: uniform_value_i16: +; GFX1132GISEL-TRUE16: ; %bb.0: ; %entry +; GFX1132GISEL-TRUE16-NEXT: s_clause 0x1 +; GFX1132GISEL-TRUE16-NEXT: s_load_b32 s2, s[4:5], 0x2c +; GFX1132GISEL-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 +; GFX1132GISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 0 +; GFX1132GISEL-TRUE16-NEXT: s_waitcnt lgkmcnt(0) +; GFX1132GISEL-TRUE16-NEXT: s_and_b32 s2, s2, 0xffff +; GFX1132GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX1132GISEL-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2 +; GFX1132GISEL-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1] +; GFX1132GISEL-TRUE16-NEXT: s_endpgm entry: %result = call i16 @llvm.amdgcn.wave.reduce.and.i16(i16 %in, i32 1) store i16 %result, ptr addrspace(1) %out @@ -288,24 +318,24 @@ define void @divergent_value_i16(ptr addrspace(1) %out, i16 %in) { ; GFX1032GISEL-NEXT: global_store_short v[0:1], v2, off ; GFX1032GISEL-NEXT: s_setpc_b64 s[30:31] ; -; GFX1164DAGISEL-LABEL: divergent_value_i16: -; GFX1164DAGISEL: ; %bb.0: ; %entry -; GFX1164DAGISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1164DAGISEL-NEXT: v_and_b32_e32 v2, 0xffff, v2 -; GFX1164DAGISEL-NEXT: s_mov_b64 s[0:1], exec -; GFX1164DAGISEL-NEXT: s_mov_b32 s2, -1 -; GFX1164DAGISEL-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1 -; GFX1164DAGISEL-NEXT: s_ctz_i32_b64 s3, s[0:1] -; GFX1164DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) -; GFX1164DAGISEL-NEXT: v_readlane_b32 s4, v2, s3 -; GFX1164DAGISEL-NEXT: s_bitset0_b64 s[0:1], s3 -; GFX1164DAGISEL-NEXT: s_and_b32 s2, s2, s4 -; GFX1164DAGISEL-NEXT: s_cmp_lg_u64 s[0:1], 0 -; GFX1164DAGISEL-NEXT: s_cbranch_scc1 .LBB1_1 -; GFX1164DAGISEL-NEXT: ; %bb.2: -; GFX1164DAGISEL-NEXT: v_mov_b32_e32 v2, s2 -; GFX1164DAGISEL-NEXT: global_store_b16 v[0:1], v2, off -; GFX1164DAGISEL-NEXT: s_setpc_b64 s[30:31] +; GFX1164DAGISEL-FAKE16-LABEL: divergent_value_i16: +; GFX1164DAGISEL-FAKE16: ; %bb.0: ; %entry +; GFX1164DAGISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1164DAGISEL-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2 +; GFX1164DAGISEL-FAKE16-NEXT: s_mov_b64 s[0:1], exec +; GFX1164DAGISEL-FAKE16-NEXT: s_mov_b32 s2, -1 +; GFX1164DAGISEL-FAKE16-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1 +; GFX1164DAGISEL-FAKE16-NEXT: s_ctz_i32_b64 s3, s[0:1] +; GFX1164DAGISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) +; GFX1164DAGISEL-FAKE16-NEXT: v_readlane_b32 s4, v2, s3 +; GFX1164DAGISEL-FAKE16-NEXT: s_bitset0_b64 s[0:1], s3 +; GFX1164DAGISEL-FAKE16-NEXT: s_and_b32 s2, s2, s4 +; GFX1164DAGISEL-FAKE16-NEXT: s_cmp_lg_u64 s[0:1], 0 +; GFX1164DAGISEL-FAKE16-NEXT: s_cbranch_scc1 .LBB1_1 +; GFX1164DAGISEL-FAKE16-NEXT: ; %bb.2: +; GFX1164DAGISEL-FAKE16-NEXT: v_mov_b32_e32 v2, s2 +; GFX1164DAGISEL-FAKE16-NEXT: global_store_b16 v[0:1], v2, off +; GFX1164DAGISEL-FAKE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX1164GISEL-LABEL: divergent_value_i16: ; GFX1164GISEL: ; %bb.0: ; %entry @@ -326,24 +356,24 @@ define void @divergent_value_i16(ptr addrspace(1) %out, i16 %in) { ; GFX1164GISEL-NEXT: global_store_b16 v[0:1], v2, off ; GFX1164GISEL-NEXT: s_setpc_b64 s[30:31] ; -; GFX1132DAGISEL-LABEL: divergent_value_i16: -; GFX1132DAGISEL: ; %bb.0: ; %entry -; GFX1132DAGISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1132DAGISEL-NEXT: v_and_b32_e32 v2, 0xffff, v2 -; GFX1132DAGISEL-NEXT: s_mov_b32 s1, exec_lo -; GFX1132DAGISEL-NEXT: s_mov_b32 s0, -1 -; GFX1132DAGISEL-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1 -; GFX1132DAGISEL-NEXT: s_ctz_i32_b32 s2, s1 -; GFX1132DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) -; GFX1132DAGISEL-NEXT: v_readlane_b32 s3, v2, s2 -; GFX1132DAGISEL-NEXT: s_bitset0_b32 s1, s2 -; GFX1132DAGISEL-NEXT: s_and_b32 s0, s0, s3 -; GFX1132DAGISEL-NEXT: s_cmp_lg_u32 s1, 0 -; GFX1132DAGISEL-NEXT: s_cbranch_scc1 .LBB1_1 -; GFX1132DAGISEL-NEXT: ; %bb.2: -; GFX1132DAGISEL-NEXT: v_mov_b32_e32 v2, s0 -; GFX1132DAGISEL-NEXT: global_store_b16 v[0:1], v2, off -; GFX1132DAGISEL-NEXT: s_setpc_b64 s[30:31] +; GFX1132DAGISEL-FAKE16-LABEL: divergent_value_i16: +; GFX1132DAGISEL-FAKE16: ; %bb.0: ; %entry +; GFX1132DAGISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1132DAGISEL-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2 +; GFX1132DAGISEL-FAKE16-NEXT: s_mov_b32 s1, exec_lo +; GFX1132DAGISEL-FAKE16-NEXT: s_mov_b32 s0, -1 +; GFX1132DAGISEL-FAKE16-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1 +; GFX1132DAGISEL-FAKE16-NEXT: s_ctz_i32_b32 s2, s1 +; GFX1132DAGISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) +; GFX1132DAGISEL-FAKE16-NEXT: v_readlane_b32 s3, v2, s2 +; GFX1132DAGISEL-FAKE16-NEXT: s_bitset0_b32 s1, s2 +; GFX1132DAGISEL-FAKE16-NEXT: s_and_b32 s0, s0, s3 +; GFX1132DAGISEL-FAKE16-NEXT: s_cmp_lg_u32 s1, 0 +; GFX1132DAGISEL-FAKE16-NEXT: s_cbranch_scc1 .LBB1_1 +; GFX1132DAGISEL-FAKE16-NEXT: ; %bb.2: +; GFX1132DAGISEL-FAKE16-NEXT: v_mov_b32_e32 v2, s0 +; GFX1132DAGISEL-FAKE16-NEXT: global_store_b16 v[0:1], v2, off +; GFX1132DAGISEL-FAKE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX1132GISEL-LABEL: divergent_value_i16: ; GFX1132GISEL: ; %bb.0: ; %entry @@ -363,6 +393,46 @@ define void @divergent_value_i16(ptr addrspace(1) %out, i16 %in) { ; GFX1132GISEL-NEXT: v_mov_b32_e32 v2, s0 ; GFX1132GISEL-NEXT: global_store_b16 v[0:1], v2, off ; GFX1132GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX1164DAGISEL-TRUE16-LABEL: divergent_value_i16: +; GFX1164DAGISEL-TRUE16: ; %bb.0: ; %entry +; GFX1164DAGISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1164DAGISEL-TRUE16-NEXT: v_mov_b16_e32 v3.h, 0 +; GFX1164DAGISEL-TRUE16-NEXT: v_mov_b16_e32 v3.l, v2.l +; GFX1164DAGISEL-TRUE16-NEXT: s_mov_b64 s[0:1], exec +; GFX1164DAGISEL-TRUE16-NEXT: s_mov_b32 s2, -1 +; GFX1164DAGISEL-TRUE16-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1 +; GFX1164DAGISEL-TRUE16-NEXT: s_ctz_i32_b64 s3, s[0:1] +; GFX1164DAGISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) +; GFX1164DAGISEL-TRUE16-NEXT: v_readlane_b32 s4, v3, s3 +; GFX1164DAGISEL-TRUE16-NEXT: s_bitset0_b64 s[0:1], s3 +; GFX1164DAGISEL-TRUE16-NEXT: s_and_b32 s2, s2, s4 +; GFX1164DAGISEL-TRUE16-NEXT: s_cmp_lg_u64 s[0:1], 0 +; GFX1164DAGISEL-TRUE16-NEXT: s_cbranch_scc1 .LBB1_1 +; GFX1164DAGISEL-TRUE16-NEXT: ; %bb.2: +; GFX1164DAGISEL-TRUE16-NEXT: v_mov_b32_e32 v2, s2 +; GFX1164DAGISEL-TRUE16-NEXT: global_store_b16 v[0:1], v2, off +; GFX1164DAGISEL-TRUE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX1132DAGISEL-TRUE16-LABEL: divergent_value_i16: +; GFX1132DAGISEL-TRUE16: ; %bb.0: ; %entry +; GFX1132DAGISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1132DAGISEL-TRUE16-NEXT: v_mov_b16_e32 v3.h, 0 +; GFX1132DAGISEL-TRUE16-NEXT: v_mov_b16_e32 v3.l, v2.l +; GFX1132DAGISEL-TRUE16-NEXT: s_mov_b32 s1, exec_lo +; GFX1132DAGISEL-TRUE16-NEXT: s_mov_b32 s0, -1 +; GFX1132DAGISEL-TRUE16-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1 +; GFX1132DAGISEL-TRUE16-NEXT: s_ctz_i32_b32 s2, s1 +; GFX1132DAGISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) +; GFX1132DAGISEL-TRUE16-NEXT: v_readlane_b32 s3, v3, s2 +; GFX1132DAGISEL-TRUE16-NEXT: s_bitset0_b32 s1, s2 +; GFX1132DAGISEL-TRUE16-NEXT: s_and_b32 s0, s0, s3 +; GFX1132DAGISEL-TRUE16-NEXT: s_cmp_lg_u32 s1, 0 +; GFX1132DAGISEL-TRUE16-NEXT: s_cbranch_scc1 .LBB1_1 +; GFX1132DAGISEL-TRUE16-NEXT: ; %bb.2: +; GFX1132DAGISEL-TRUE16-NEXT: v_mov_b32_e32 v2, s0 +; GFX1132DAGISEL-TRUE16-NEXT: global_store_b16 v[0:1], v2, off +; GFX1132DAGISEL-TRUE16-NEXT: s_setpc_b64 s[30:31] entry: %result = call i16 @llvm.amdgcn.wave.reduce.and.i16(i16 %in, i32 1) store i16 %result, ptr addrspace(1) %out diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.or.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.or.ll index 6ea9fe2336a69..80f49fcf6c36c 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.or.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.or.ll @@ -7,10 +7,14 @@ ; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX10GISEL,GFX1064GISEL %s ; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=0 < %s | FileCheck -check-prefixes=GFX10DAGISEL,GFX1032DAGISEL %s ; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX10GISEL,GFX1032GISEL %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -global-isel=0 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1164DAGISEL %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1164GISEL %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -global-isel=0 < %s | FileCheck -check-prefixes=GFX1132DAGISEL %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX1132GISEL %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -global-isel=0 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1164DAGISEL,GFX1164DAGISEL-FAKE16 %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1164GISEL,GFX1164GISEL-FAKE16 %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -global-isel=0 < %s | FileCheck -check-prefixes=GFX1132DAGISEL,GFX1132DAGISEL-FAKE16 %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX1132GISEL,GFX1132GISEL-FAKE16 %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -global-isel=0 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1164DAGISEL,GFX1164DAGISEL-TRUE16 %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1164GISEL,GFX1164GISEL-TRUE16 %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -global-isel=0 < %s | FileCheck -check-prefixes=GFX1132DAGISEL,GFX1132DAGISEL-TRUE16 %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX1132GISEL,GFX1132GISEL-TRUE16 %s define amdgpu_kernel void @uniform_value_i16(ptr addrspace(1) %out, i16 %in) { ; GFX8DAGISEL-LABEL: uniform_value_i16: @@ -96,18 +100,18 @@ define amdgpu_kernel void @uniform_value_i16(ptr addrspace(1) %out, i16 %in) { ; GFX1164DAGISEL-NEXT: global_store_b16 v0, v1, s[0:1] ; GFX1164DAGISEL-NEXT: s_endpgm ; -; GFX1164GISEL-LABEL: uniform_value_i16: -; GFX1164GISEL: ; %bb.0: ; %entry -; GFX1164GISEL-NEXT: s_clause 0x1 -; GFX1164GISEL-NEXT: s_load_b32 s2, s[4:5], 0x2c -; GFX1164GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 -; GFX1164GISEL-NEXT: v_mov_b32_e32 v1, 0 -; GFX1164GISEL-NEXT: s_waitcnt lgkmcnt(0) -; GFX1164GISEL-NEXT: s_and_b32 s2, s2, 0xffff -; GFX1164GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX1164GISEL-NEXT: v_mov_b32_e32 v0, s2 -; GFX1164GISEL-NEXT: global_store_b16 v1, v0, s[0:1] -; GFX1164GISEL-NEXT: s_endpgm +; GFX1164GISEL-FAKE16-LABEL: uniform_value_i16: +; GFX1164GISEL-FAKE16: ; %bb.0: ; %entry +; GFX1164GISEL-FAKE16-NEXT: s_clause 0x1 +; GFX1164GISEL-FAKE16-NEXT: s_load_b32 s2, s[4:5], 0x2c +; GFX1164GISEL-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 +; GFX1164GISEL-FAKE16-NEXT: v_mov_b32_e32 v1, 0 +; GFX1164GISEL-FAKE16-NEXT: s_waitcnt lgkmcnt(0) +; GFX1164GISEL-FAKE16-NEXT: s_and_b32 s2, s2, 0xffff +; GFX1164GISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX1164GISEL-FAKE16-NEXT: v_mov_b32_e32 v0, s2 +; GFX1164GISEL-FAKE16-NEXT: global_store_b16 v1, v0, s[0:1] +; GFX1164GISEL-FAKE16-NEXT: s_endpgm ; ; GFX1132DAGISEL-LABEL: uniform_value_i16: ; GFX1132DAGISEL: ; %bb.0: ; %entry @@ -121,18 +125,44 @@ define amdgpu_kernel void @uniform_value_i16(ptr addrspace(1) %out, i16 %in) { ; GFX1132DAGISEL-NEXT: global_store_b16 v0, v1, s[0:1] ; GFX1132DAGISEL-NEXT: s_endpgm ; -; GFX1132GISEL-LABEL: uniform_value_i16: -; GFX1132GISEL: ; %bb.0: ; %entry -; GFX1132GISEL-NEXT: s_clause 0x1 -; GFX1132GISEL-NEXT: s_load_b32 s2, s[4:5], 0x2c -; GFX1132GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 -; GFX1132GISEL-NEXT: v_mov_b32_e32 v1, 0 -; GFX1132GISEL-NEXT: s_waitcnt lgkmcnt(0) -; GFX1132GISEL-NEXT: s_and_b32 s2, s2, 0xffff -; GFX1132GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX1132GISEL-NEXT: v_mov_b32_e32 v0, s2 -; GFX1132GISEL-NEXT: global_store_b16 v1, v0, s[0:1] -; GFX1132GISEL-NEXT: s_endpgm +; GFX1132GISEL-FAKE16-LABEL: uniform_value_i16: +; GFX1132GISEL-FAKE16: ; %bb.0: ; %entry +; GFX1132GISEL-FAKE16-NEXT: s_clause 0x1 +; GFX1132GISEL-FAKE16-NEXT: s_load_b32 s2, s[4:5], 0x2c +; GFX1132GISEL-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 +; GFX1132GISEL-FAKE16-NEXT: v_mov_b32_e32 v1, 0 +; GFX1132GISEL-FAKE16-NEXT: s_waitcnt lgkmcnt(0) +; GFX1132GISEL-FAKE16-NEXT: s_and_b32 s2, s2, 0xffff +; GFX1132GISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX1132GISEL-FAKE16-NEXT: v_mov_b32_e32 v0, s2 +; GFX1132GISEL-FAKE16-NEXT: global_store_b16 v1, v0, s[0:1] +; GFX1132GISEL-FAKE16-NEXT: s_endpgm +; +; GFX1164GISEL-TRUE16-LABEL: uniform_value_i16: +; GFX1164GISEL-TRUE16: ; %bb.0: ; %entry +; GFX1164GISEL-TRUE16-NEXT: s_clause 0x1 +; GFX1164GISEL-TRUE16-NEXT: s_load_b32 s2, s[4:5], 0x2c +; GFX1164GISEL-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 +; GFX1164GISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 0 +; GFX1164GISEL-TRUE16-NEXT: s_waitcnt lgkmcnt(0) +; GFX1164GISEL-TRUE16-NEXT: s_and_b32 s2, s2, 0xffff +; GFX1164GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX1164GISEL-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2 +; GFX1164GISEL-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1] +; GFX1164GISEL-TRUE16-NEXT: s_endpgm +; +; GFX1132GISEL-TRUE16-LABEL: uniform_value_i16: +; GFX1132GISEL-TRUE16: ; %bb.0: ; %entry +; GFX1132GISEL-TRUE16-NEXT: s_clause 0x1 +; GFX1132GISEL-TRUE16-NEXT: s_load_b32 s2, s[4:5], 0x2c +; GFX1132GISEL-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 +; GFX1132GISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 0 +; GFX1132GISEL-TRUE16-NEXT: s_waitcnt lgkmcnt(0) +; GFX1132GISEL-TRUE16-NEXT: s_and_b32 s2, s2, 0xffff +; GFX1132GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX1132GISEL-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2 +; GFX1132GISEL-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1] +; GFX1132GISEL-TRUE16-NEXT: s_endpgm entry: %result = call i16 @llvm.amdgcn.wave.reduce.or.i16(i16 %in, i32 1) store i16 %result, ptr addrspace(1) %out @@ -288,24 +318,24 @@ define void @divergent_value_i16(ptr addrspace(1) %out, i16 %in) { ; GFX1032GISEL-NEXT: global_store_short v[0:1], v2, off ; GFX1032GISEL-NEXT: s_setpc_b64 s[30:31] ; -; GFX1164DAGISEL-LABEL: divergent_value_i16: -; GFX1164DAGISEL: ; %bb.0: ; %entry -; GFX1164DAGISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1164DAGISEL-NEXT: v_and_b32_e32 v2, 0xffff, v2 -; GFX1164DAGISEL-NEXT: s_mov_b64 s[0:1], exec -; GFX1164DAGISEL-NEXT: s_mov_b32 s2, 0 -; GFX1164DAGISEL-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1 -; GFX1164DAGISEL-NEXT: s_ctz_i32_b64 s3, s[0:1] -; GFX1164DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) -; GFX1164DAGISEL-NEXT: v_readlane_b32 s4, v2, s3 -; GFX1164DAGISEL-NEXT: s_bitset0_b64 s[0:1], s3 -; GFX1164DAGISEL-NEXT: s_or_b32 s2, s2, s4 -; GFX1164DAGISEL-NEXT: s_cmp_lg_u64 s[0:1], 0 -; GFX1164DAGISEL-NEXT: s_cbranch_scc1 .LBB1_1 -; GFX1164DAGISEL-NEXT: ; %bb.2: -; GFX1164DAGISEL-NEXT: v_mov_b32_e32 v2, s2 -; GFX1164DAGISEL-NEXT: global_store_b16 v[0:1], v2, off -; GFX1164DAGISEL-NEXT: s_setpc_b64 s[30:31] +; GFX1164DAGISEL-FAKE16-LABEL: divergent_value_i16: +; GFX1164DAGISEL-FAKE16: ; %bb.0: ; %entry +; GFX1164DAGISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1164DAGISEL-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2 +; GFX1164DAGISEL-FAKE16-NEXT: s_mov_b64 s[0:1], exec +; GFX1164DAGISEL-FAKE16-NEXT: s_mov_b32 s2, 0 +; GFX1164DAGISEL-FAKE16-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1 +; GFX1164DAGISEL-FAKE16-NEXT: s_ctz_i32_b64 s3, s[0:1] +; GFX1164DAGISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) +; GFX1164DAGISEL-FAKE16-NEXT: v_readlane_b32 s4, v2, s3 +; GFX1164DAGISEL-FAKE16-NEXT: s_bitset0_b64 s[0:1], s3 +; GFX1164DAGISEL-FAKE16-NEXT: s_or_b32 s2, s2, s4 +; GFX1164DAGISEL-FAKE16-NEXT: s_cmp_lg_u64 s[0:1], 0 +; GFX1164DAGISEL-FAKE16-NEXT: s_cbranch_scc1 .LBB1_1 +; GFX1164DAGISEL-FAKE16-NEXT: ; %bb.2: +; GFX1164DAGISEL-FAKE16-NEXT: v_mov_b32_e32 v2, s2 +; GFX1164DAGISEL-FAKE16-NEXT: global_store_b16 v[0:1], v2, off +; GFX1164DAGISEL-FAKE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX1164GISEL-LABEL: divergent_value_i16: ; GFX1164GISEL: ; %bb.0: ; %entry @@ -326,24 +356,24 @@ define void @divergent_value_i16(ptr addrspace(1) %out, i16 %in) { ; GFX1164GISEL-NEXT: global_store_b16 v[0:1], v2, off ; GFX1164GISEL-NEXT: s_setpc_b64 s[30:31] ; -; GFX1132DAGISEL-LABEL: divergent_value_i16: -; GFX1132DAGISEL: ; %bb.0: ; %entry -; GFX1132DAGISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1132DAGISEL-NEXT: v_and_b32_e32 v2, 0xffff, v2 -; GFX1132DAGISEL-NEXT: s_mov_b32 s1, exec_lo -; GFX1132DAGISEL-NEXT: s_mov_b32 s0, 0 -; GFX1132DAGISEL-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1 -; GFX1132DAGISEL-NEXT: s_ctz_i32_b32 s2, s1 -; GFX1132DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) -; GFX1132DAGISEL-NEXT: v_readlane_b32 s3, v2, s2 -; GFX1132DAGISEL-NEXT: s_bitset0_b32 s1, s2 -; GFX1132DAGISEL-NEXT: s_or_b32 s0, s0, s3 -; GFX1132DAGISEL-NEXT: s_cmp_lg_u32 s1, 0 -; GFX1132DAGISEL-NEXT: s_cbranch_scc1 .LBB1_1 -; GFX1132DAGISEL-NEXT: ; %bb.2: -; GFX1132DAGISEL-NEXT: v_mov_b32_e32 v2, s0 -; GFX1132DAGISEL-NEXT: global_store_b16 v[0:1], v2, off -; GFX1132DAGISEL-NEXT: s_setpc_b64 s[30:31] +; GFX1132DAGISEL-FAKE16-LABEL: divergent_value_i16: +; GFX1132DAGISEL-FAKE16: ; %bb.0: ; %entry +; GFX1132DAGISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1132DAGISEL-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2 +; GFX1132DAGISEL-FAKE16-NEXT: s_mov_b32 s1, exec_lo +; GFX1132DAGISEL-FAKE16-NEXT: s_mov_b32 s0, 0 +; GFX1132DAGISEL-FAKE16-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1 +; GFX1132DAGISEL-FAKE16-NEXT: s_ctz_i32_b32 s2, s1 +; GFX1132DAGISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) +; GFX1132DAGISEL-FAKE16-NEXT: v_readlane_b32 s3, v2, s2 +; GFX1132DAGISEL-FAKE16-NEXT: s_bitset0_b32 s1, s2 +; GFX1132DAGISEL-FAKE16-NEXT: s_or_b32 s0, s0, s3 +; GFX1132DAGISEL-FAKE16-NEXT: s_cmp_lg_u32 s1, 0 +; GFX1132DAGISEL-FAKE16-NEXT: s_cbranch_scc1 .LBB1_1 +; GFX1132DAGISEL-FAKE16-NEXT: ; %bb.2: +; GFX1132DAGISEL-FAKE16-NEXT: v_mov_b32_e32 v2, s0 +; GFX1132DAGISEL-FAKE16-NEXT: global_store_b16 v[0:1], v2, off +; GFX1132DAGISEL-FAKE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX1132GISEL-LABEL: divergent_value_i16: ; GFX1132GISEL: ; %bb.0: ; %entry @@ -363,6 +393,46 @@ define void @divergent_value_i16(ptr addrspace(1) %out, i16 %in) { ; GFX1132GISEL-NEXT: v_mov_b32_e32 v2, s0 ; GFX1132GISEL-NEXT: global_store_b16 v[0:1], v2, off ; GFX1132GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX1164DAGISEL-TRUE16-LABEL: divergent_value_i16: +; GFX1164DAGISEL-TRUE16: ; %bb.0: ; %entry +; GFX1164DAGISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1164DAGISEL-TRUE16-NEXT: v_mov_b16_e32 v3.h, 0 +; GFX1164DAGISEL-TRUE16-NEXT: v_mov_b16_e32 v3.l, v2.l +; GFX1164DAGISEL-TRUE16-NEXT: s_mov_b64 s[0:1], exec +; GFX1164DAGISEL-TRUE16-NEXT: s_mov_b32 s2, 0 +; GFX1164DAGISEL-TRUE16-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1 +; GFX1164DAGISEL-TRUE16-NEXT: s_ctz_i32_b64 s3, s[0:1] +; GFX1164DAGISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) +; GFX1164DAGISEL-TRUE16-NEXT: v_readlane_b32 s4, v3, s3 +; GFX1164DAGISEL-TRUE16-NEXT: s_bitset0_b64 s[0:1], s3 +; GFX1164DAGISEL-TRUE16-NEXT: s_or_b32 s2, s2, s4 +; GFX1164DAGISEL-TRUE16-NEXT: s_cmp_lg_u64 s[0:1], 0 +; GFX1164DAGISEL-TRUE16-NEXT: s_cbranch_scc1 .LBB1_1 +; GFX1164DAGISEL-TRUE16-NEXT: ; %bb.2: +; GFX1164DAGISEL-TRUE16-NEXT: v_mov_b32_e32 v2, s2 +; GFX1164DAGISEL-TRUE16-NEXT: global_store_b16 v[0:1], v2, off +; GFX1164DAGISEL-TRUE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX1132DAGISEL-TRUE16-LABEL: divergent_value_i16: +; GFX1132DAGISEL-TRUE16: ; %bb.0: ; %entry +; GFX1132DAGISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1132DAGISEL-TRUE16-NEXT: v_mov_b16_e32 v3.h, 0 +; GFX1132DAGISEL-TRUE16-NEXT: v_mov_b16_e32 v3.l, v2.l +; GFX1132DAGISEL-TRUE16-NEXT: s_mov_b32 s1, exec_lo +; GFX1132DAGISEL-TRUE16-NEXT: s_mov_b32 s0, 0 +; GFX1132DAGISEL-TRUE16-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1 +; GFX1132DAGISEL-TRUE16-NEXT: s_ctz_i32_b32 s2, s1 +; GFX1132DAGISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) +; GFX1132DAGISEL-TRUE16-NEXT: v_readlane_b32 s3, v3, s2 +; GFX1132DAGISEL-TRUE16-NEXT: s_bitset0_b32 s1, s2 +; GFX1132DAGISEL-TRUE16-NEXT: s_or_b32 s0, s0, s3 +; GFX1132DAGISEL-TRUE16-NEXT: s_cmp_lg_u32 s1, 0 +; GFX1132DAGISEL-TRUE16-NEXT: s_cbranch_scc1 .LBB1_1 +; GFX1132DAGISEL-TRUE16-NEXT: ; %bb.2: +; GFX1132DAGISEL-TRUE16-NEXT: v_mov_b32_e32 v2, s0 +; GFX1132DAGISEL-TRUE16-NEXT: global_store_b16 v[0:1], v2, off +; GFX1132DAGISEL-TRUE16-NEXT: s_setpc_b64 s[30:31] entry: %result = call i16 @llvm.amdgcn.wave.reduce.or.i16(i16 %in, i32 1) store i16 %result, ptr addrspace(1) %out diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.xor.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.xor.ll index 4566d94bd5e3a..4481a35418c10 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.xor.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.xor.ll @@ -7,10 +7,14 @@ ; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1064GISEL %s ; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=0 < %s | FileCheck -check-prefixes=GFX1032DAGISEL %s ; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX1032GISEL %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -global-isel=0 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1164DAGISEL %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1164GISEL %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -global-isel=0 < %s | FileCheck -check-prefixes=GFX1132DAGISEL %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX1132GISEL %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -global-isel=0 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1164DAGISEL,GFX1164DAGISEL-FAKE16 %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1164GISEL,GFX1164GISEL-FAKE16 %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -global-isel=0 < %s | FileCheck -check-prefixes=GFX1132DAGISEL,GFX1132DAGISEL-FAKE16 %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX1132GISEL,GFX1132GISEL-FAKE16 %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -global-isel=0 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1164DAGISEL,GFX1164DAGISEL-TRUE16 %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1164GISEL,GFX1164GISEL-TRUE16 %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -global-isel=0 < %s | FileCheck -check-prefixes=GFX1132DAGISEL,GFX1132DAGISEL-TRUE16 %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX1132GISEL,GFX1132GISEL-TRUE16 %s define amdgpu_kernel void @uniform_value_i16(ptr addrspace(1) %out, i16 %in) { ; GFX8DAGISEL-LABEL: uniform_value_i16: @@ -157,23 +161,23 @@ define amdgpu_kernel void @uniform_value_i16(ptr addrspace(1) %out, i16 %in) { ; GFX1164DAGISEL-NEXT: global_store_b16 v0, v1, s[0:1] ; GFX1164DAGISEL-NEXT: s_endpgm ; -; GFX1164GISEL-LABEL: uniform_value_i16: -; GFX1164GISEL: ; %bb.0: ; %entry -; GFX1164GISEL-NEXT: s_clause 0x1 -; GFX1164GISEL-NEXT: s_load_b32 s6, s[4:5], 0x2c -; GFX1164GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 -; GFX1164GISEL-NEXT: s_mov_b64 s[2:3], exec -; GFX1164GISEL-NEXT: v_mov_b32_e32 v1, 0 -; GFX1164GISEL-NEXT: s_bcnt1_i32_b64 s2, s[2:3] -; GFX1164GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) -; GFX1164GISEL-NEXT: s_and_b32 s2, s2, 1 -; GFX1164GISEL-NEXT: s_waitcnt lgkmcnt(0) -; GFX1164GISEL-NEXT: s_and_b32 s3, s6, 0xffff -; GFX1164GISEL-NEXT: s_mul_i32 s2, s3, s2 -; GFX1164GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX1164GISEL-NEXT: v_mov_b32_e32 v0, s2 -; GFX1164GISEL-NEXT: global_store_b16 v1, v0, s[0:1] -; GFX1164GISEL-NEXT: s_endpgm +; GFX1164GISEL-FAKE16-LABEL: uniform_value_i16: +; GFX1164GISEL-FAKE16: ; %bb.0: ; %entry +; GFX1164GISEL-FAKE16-NEXT: s_clause 0x1 +; GFX1164GISEL-FAKE16-NEXT: s_load_b32 s6, s[4:5], 0x2c +; GFX1164GISEL-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 +; GFX1164GISEL-FAKE16-NEXT: s_mov_b64 s[2:3], exec +; GFX1164GISEL-FAKE16-NEXT: v_mov_b32_e32 v1, 0 +; GFX1164GISEL-FAKE16-NEXT: s_bcnt1_i32_b64 s2, s[2:3] +; GFX1164GISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) +; GFX1164GISEL-FAKE16-NEXT: s_and_b32 s2, s2, 1 +; GFX1164GISEL-FAKE16-NEXT: s_waitcnt lgkmcnt(0) +; GFX1164GISEL-FAKE16-NEXT: s_and_b32 s3, s6, 0xffff +; GFX1164GISEL-FAKE16-NEXT: s_mul_i32 s2, s3, s2 +; GFX1164GISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX1164GISEL-FAKE16-NEXT: v_mov_b32_e32 v0, s2 +; GFX1164GISEL-FAKE16-NEXT: global_store_b16 v1, v0, s[0:1] +; GFX1164GISEL-FAKE16-NEXT: s_endpgm ; ; GFX1132DAGISEL-LABEL: uniform_value_i16: ; GFX1132DAGISEL: ; %bb.0: ; %entry @@ -192,23 +196,59 @@ define amdgpu_kernel void @uniform_value_i16(ptr addrspace(1) %out, i16 %in) { ; GFX1132DAGISEL-NEXT: global_store_b16 v0, v1, s[0:1] ; GFX1132DAGISEL-NEXT: s_endpgm ; -; GFX1132GISEL-LABEL: uniform_value_i16: -; GFX1132GISEL: ; %bb.0: ; %entry -; GFX1132GISEL-NEXT: s_clause 0x1 -; GFX1132GISEL-NEXT: s_load_b32 s2, s[4:5], 0x2c -; GFX1132GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 -; GFX1132GISEL-NEXT: s_mov_b32 s3, exec_lo -; GFX1132GISEL-NEXT: v_mov_b32_e32 v1, 0 -; GFX1132GISEL-NEXT: s_bcnt1_i32_b32 s3, s3 -; GFX1132GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) -; GFX1132GISEL-NEXT: s_and_b32 s3, s3, 1 -; GFX1132GISEL-NEXT: s_waitcnt lgkmcnt(0) -; GFX1132GISEL-NEXT: s_and_b32 s2, s2, 0xffff -; GFX1132GISEL-NEXT: s_mul_i32 s2, s2, s3 -; GFX1132GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX1132GISEL-NEXT: v_mov_b32_e32 v0, s2 -; GFX1132GISEL-NEXT: global_store_b16 v1, v0, s[0:1] -; GFX1132GISEL-NEXT: s_endpgm +; GFX1132GISEL-FAKE16-LABEL: uniform_value_i16: +; GFX1132GISEL-FAKE16: ; %bb.0: ; %entry +; GFX1132GISEL-FAKE16-NEXT: s_clause 0x1 +; GFX1132GISEL-FAKE16-NEXT: s_load_b32 s2, s[4:5], 0x2c +; GFX1132GISEL-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 +; GFX1132GISEL-FAKE16-NEXT: s_mov_b32 s3, exec_lo +; GFX1132GISEL-FAKE16-NEXT: v_mov_b32_e32 v1, 0 +; GFX1132GISEL-FAKE16-NEXT: s_bcnt1_i32_b32 s3, s3 +; GFX1132GISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) +; GFX1132GISEL-FAKE16-NEXT: s_and_b32 s3, s3, 1 +; GFX1132GISEL-FAKE16-NEXT: s_waitcnt lgkmcnt(0) +; GFX1132GISEL-FAKE16-NEXT: s_and_b32 s2, s2, 0xffff +; GFX1132GISEL-FAKE16-NEXT: s_mul_i32 s2, s2, s3 +; GFX1132GISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX1132GISEL-FAKE16-NEXT: v_mov_b32_e32 v0, s2 +; GFX1132GISEL-FAKE16-NEXT: global_store_b16 v1, v0, s[0:1] +; GFX1132GISEL-FAKE16-NEXT: s_endpgm +; +; GFX1164GISEL-TRUE16-LABEL: uniform_value_i16: +; GFX1164GISEL-TRUE16: ; %bb.0: ; %entry +; GFX1164GISEL-TRUE16-NEXT: s_clause 0x1 +; GFX1164GISEL-TRUE16-NEXT: s_load_b32 s6, s[4:5], 0x2c +; GFX1164GISEL-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 +; GFX1164GISEL-TRUE16-NEXT: s_mov_b64 s[2:3], exec +; GFX1164GISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 0 +; GFX1164GISEL-TRUE16-NEXT: s_bcnt1_i32_b64 s2, s[2:3] +; GFX1164GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) +; GFX1164GISEL-TRUE16-NEXT: s_and_b32 s2, s2, 1 +; GFX1164GISEL-TRUE16-NEXT: s_waitcnt lgkmcnt(0) +; GFX1164GISEL-TRUE16-NEXT: s_and_b32 s3, s6, 0xffff +; GFX1164GISEL-TRUE16-NEXT: s_mul_i32 s2, s3, s2 +; GFX1164GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX1164GISEL-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2 +; GFX1164GISEL-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1] +; GFX1164GISEL-TRUE16-NEXT: s_endpgm +; +; GFX1132GISEL-TRUE16-LABEL: uniform_value_i16: +; GFX1132GISEL-TRUE16: ; %bb.0: ; %entry +; GFX1132GISEL-TRUE16-NEXT: s_clause 0x1 +; GFX1132GISEL-TRUE16-NEXT: s_load_b32 s2, s[4:5], 0x2c +; GFX1132GISEL-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 +; GFX1132GISEL-TRUE16-NEXT: s_mov_b32 s3, exec_lo +; GFX1132GISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 0 +; GFX1132GISEL-TRUE16-NEXT: s_bcnt1_i32_b32 s3, s3 +; GFX1132GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) +; GFX1132GISEL-TRUE16-NEXT: s_and_b32 s3, s3, 1 +; GFX1132GISEL-TRUE16-NEXT: s_waitcnt lgkmcnt(0) +; GFX1132GISEL-TRUE16-NEXT: s_and_b32 s2, s2, 0xffff +; GFX1132GISEL-TRUE16-NEXT: s_mul_i32 s2, s2, s3 +; GFX1132GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX1132GISEL-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2 +; GFX1132GISEL-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1] +; GFX1132GISEL-TRUE16-NEXT: s_endpgm entry: %result = call i16 @llvm.amdgcn.wave.reduce.xor.i16(i16 %in, i32 1) store i16 %result, ptr addrspace(1) %out @@ -364,24 +404,24 @@ define void @divergent_value_i16(ptr addrspace(1) %out, i16 %in) { ; GFX1032GISEL-NEXT: global_store_short v[0:1], v2, off ; GFX1032GISEL-NEXT: s_setpc_b64 s[30:31] ; -; GFX1164DAGISEL-LABEL: divergent_value_i16: -; GFX1164DAGISEL: ; %bb.0: ; %entry -; GFX1164DAGISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1164DAGISEL-NEXT: v_and_b32_e32 v2, 0xffff, v2 -; GFX1164DAGISEL-NEXT: s_mov_b64 s[0:1], exec -; GFX1164DAGISEL-NEXT: s_mov_b32 s2, 0 -; GFX1164DAGISEL-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1 -; GFX1164DAGISEL-NEXT: s_ctz_i32_b64 s3, s[0:1] -; GFX1164DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) -; GFX1164DAGISEL-NEXT: v_readlane_b32 s4, v2, s3 -; GFX1164DAGISEL-NEXT: s_bitset0_b64 s[0:1], s3 -; GFX1164DAGISEL-NEXT: s_xor_b32 s2, s2, s4 -; GFX1164DAGISEL-NEXT: s_cmp_lg_u64 s[0:1], 0 -; GFX1164DAGISEL-NEXT: s_cbranch_scc1 .LBB1_1 -; GFX1164DAGISEL-NEXT: ; %bb.2: -; GFX1164DAGISEL-NEXT: v_mov_b32_e32 v2, s2 -; GFX1164DAGISEL-NEXT: global_store_b16 v[0:1], v2, off -; GFX1164DAGISEL-NEXT: s_setpc_b64 s[30:31] +; GFX1164DAGISEL-FAKE16-LABEL: divergent_value_i16: +; GFX1164DAGISEL-FAKE16: ; %bb.0: ; %entry +; GFX1164DAGISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1164DAGISEL-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2 +; GFX1164DAGISEL-FAKE16-NEXT: s_mov_b64 s[0:1], exec +; GFX1164DAGISEL-FAKE16-NEXT: s_mov_b32 s2, 0 +; GFX1164DAGISEL-FAKE16-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1 +; GFX1164DAGISEL-FAKE16-NEXT: s_ctz_i32_b64 s3, s[0:1] +; GFX1164DAGISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) +; GFX1164DAGISEL-FAKE16-NEXT: v_readlane_b32 s4, v2, s3 +; GFX1164DAGISEL-FAKE16-NEXT: s_bitset0_b64 s[0:1], s3 +; GFX1164DAGISEL-FAKE16-NEXT: s_xor_b32 s2, s2, s4 +; GFX1164DAGISEL-FAKE16-NEXT: s_cmp_lg_u64 s[0:1], 0 +; GFX1164DAGISEL-FAKE16-NEXT: s_cbranch_scc1 .LBB1_1 +; GFX1164DAGISEL-FAKE16-NEXT: ; %bb.2: +; GFX1164DAGISEL-FAKE16-NEXT: v_mov_b32_e32 v2, s2 +; GFX1164DAGISEL-FAKE16-NEXT: global_store_b16 v[0:1], v2, off +; GFX1164DAGISEL-FAKE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX1164GISEL-LABEL: divergent_value_i16: ; GFX1164GISEL: ; %bb.0: ; %entry @@ -402,24 +442,24 @@ define void @divergent_value_i16(ptr addrspace(1) %out, i16 %in) { ; GFX1164GISEL-NEXT: global_store_b16 v[0:1], v2, off ; GFX1164GISEL-NEXT: s_setpc_b64 s[30:31] ; -; GFX1132DAGISEL-LABEL: divergent_value_i16: -; GFX1132DAGISEL: ; %bb.0: ; %entry -; GFX1132DAGISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1132DAGISEL-NEXT: v_and_b32_e32 v2, 0xffff, v2 -; GFX1132DAGISEL-NEXT: s_mov_b32 s1, exec_lo -; GFX1132DAGISEL-NEXT: s_mov_b32 s0, 0 -; GFX1132DAGISEL-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1 -; GFX1132DAGISEL-NEXT: s_ctz_i32_b32 s2, s1 -; GFX1132DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) -; GFX1132DAGISEL-NEXT: v_readlane_b32 s3, v2, s2 -; GFX1132DAGISEL-NEXT: s_bitset0_b32 s1, s2 -; GFX1132DAGISEL-NEXT: s_xor_b32 s0, s0, s3 -; GFX1132DAGISEL-NEXT: s_cmp_lg_u32 s1, 0 -; GFX1132DAGISEL-NEXT: s_cbranch_scc1 .LBB1_1 -; GFX1132DAGISEL-NEXT: ; %bb.2: -; GFX1132DAGISEL-NEXT: v_mov_b32_e32 v2, s0 -; GFX1132DAGISEL-NEXT: global_store_b16 v[0:1], v2, off -; GFX1132DAGISEL-NEXT: s_setpc_b64 s[30:31] +; GFX1132DAGISEL-FAKE16-LABEL: divergent_value_i16: +; GFX1132DAGISEL-FAKE16: ; %bb.0: ; %entry +; GFX1132DAGISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1132DAGISEL-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2 +; GFX1132DAGISEL-FAKE16-NEXT: s_mov_b32 s1, exec_lo +; GFX1132DAGISEL-FAKE16-NEXT: s_mov_b32 s0, 0 +; GFX1132DAGISEL-FAKE16-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1 +; GFX1132DAGISEL-FAKE16-NEXT: s_ctz_i32_b32 s2, s1 +; GFX1132DAGISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) +; GFX1132DAGISEL-FAKE16-NEXT: v_readlane_b32 s3, v2, s2 +; GFX1132DAGISEL-FAKE16-NEXT: s_bitset0_b32 s1, s2 +; GFX1132DAGISEL-FAKE16-NEXT: s_xor_b32 s0, s0, s3 +; GFX1132DAGISEL-FAKE16-NEXT: s_cmp_lg_u32 s1, 0 +; GFX1132DAGISEL-FAKE16-NEXT: s_cbranch_scc1 .LBB1_1 +; GFX1132DAGISEL-FAKE16-NEXT: ; %bb.2: +; GFX1132DAGISEL-FAKE16-NEXT: v_mov_b32_e32 v2, s0 +; GFX1132DAGISEL-FAKE16-NEXT: global_store_b16 v[0:1], v2, off +; GFX1132DAGISEL-FAKE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX1132GISEL-LABEL: divergent_value_i16: ; GFX1132GISEL: ; %bb.0: ; %entry @@ -439,6 +479,46 @@ define void @divergent_value_i16(ptr addrspace(1) %out, i16 %in) { ; GFX1132GISEL-NEXT: v_mov_b32_e32 v2, s0 ; GFX1132GISEL-NEXT: global_store_b16 v[0:1], v2, off ; GFX1132GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX1164DAGISEL-TRUE16-LABEL: divergent_value_i16: +; GFX1164DAGISEL-TRUE16: ; %bb.0: ; %entry +; GFX1164DAGISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1164DAGISEL-TRUE16-NEXT: v_mov_b16_e32 v3.h, 0 +; GFX1164DAGISEL-TRUE16-NEXT: v_mov_b16_e32 v3.l, v2.l +; GFX1164DAGISEL-TRUE16-NEXT: s_mov_b64 s[0:1], exec +; GFX1164DAGISEL-TRUE16-NEXT: s_mov_b32 s2, 0 +; GFX1164DAGISEL-TRUE16-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1 +; GFX1164DAGISEL-TRUE16-NEXT: s_ctz_i32_b64 s3, s[0:1] +; GFX1164DAGISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) +; GFX1164DAGISEL-TRUE16-NEXT: v_readlane_b32 s4, v3, s3 +; GFX1164DAGISEL-TRUE16-NEXT: s_bitset0_b64 s[0:1], s3 +; GFX1164DAGISEL-TRUE16-NEXT: s_xor_b32 s2, s2, s4 +; GFX1164DAGISEL-TRUE16-NEXT: s_cmp_lg_u64 s[0:1], 0 +; GFX1164DAGISEL-TRUE16-NEXT: s_cbranch_scc1 .LBB1_1 +; GFX1164DAGISEL-TRUE16-NEXT: ; %bb.2: +; GFX1164DAGISEL-TRUE16-NEXT: v_mov_b32_e32 v2, s2 +; GFX1164DAGISEL-TRUE16-NEXT: global_store_b16 v[0:1], v2, off +; GFX1164DAGISEL-TRUE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX1132DAGISEL-TRUE16-LABEL: divergent_value_i16: +; GFX1132DAGISEL-TRUE16: ; %bb.0: ; %entry +; GFX1132DAGISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1132DAGISEL-TRUE16-NEXT: v_mov_b16_e32 v3.h, 0 +; GFX1132DAGISEL-TRUE16-NEXT: v_mov_b16_e32 v3.l, v2.l +; GFX1132DAGISEL-TRUE16-NEXT: s_mov_b32 s1, exec_lo +; GFX1132DAGISEL-TRUE16-NEXT: s_mov_b32 s0, 0 +; GFX1132DAGISEL-TRUE16-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1 +; GFX1132DAGISEL-TRUE16-NEXT: s_ctz_i32_b32 s2, s1 +; GFX1132DAGISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) +; GFX1132DAGISEL-TRUE16-NEXT: v_readlane_b32 s3, v3, s2 +; GFX1132DAGISEL-TRUE16-NEXT: s_bitset0_b32 s1, s2 +; GFX1132DAGISEL-TRUE16-NEXT: s_xor_b32 s0, s0, s3 +; GFX1132DAGISEL-TRUE16-NEXT: s_cmp_lg_u32 s1, 0 +; GFX1132DAGISEL-TRUE16-NEXT: s_cbranch_scc1 .LBB1_1 +; GFX1132DAGISEL-TRUE16-NEXT: ; %bb.2: +; GFX1132DAGISEL-TRUE16-NEXT: v_mov_b32_e32 v2, s0 +; GFX1132DAGISEL-TRUE16-NEXT: global_store_b16 v[0:1], v2, off +; GFX1132DAGISEL-TRUE16-NEXT: s_setpc_b64 s[30:31] entry: %result = call i16 @llvm.amdgcn.wave.reduce.xor.i16(i16 %in, i32 1) store i16 %result, ptr addrspace(1) %out _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
