================
@@ -28,11 +29,14 @@ namespace llvm {
///
/// At the moment this supports rematerializing registers that meet all of the
/// following constraints.
-/// 1. The register is virtual and has a single defining instruction.
-/// 2. The single defining instruction is deemed rematerializable by the TII
and
-/// doesn't have any physical register use that is both non-constant and
+/// 1. The register is virtual.
+/// 2. The register is defined within a single region---potentially over
+/// multiple MIs---and isn't used by a MI that is not defining part of the
+/// register before its last defining MI.
----------------
qcolombet wrote:
What you're saying is:
This is okay:
```
v1.sub0 =
v1.sub1 = op v1.sub0
```
This is okay:
```
v1.sub0 =
v1.sub1 =
... = op v1.sub0
```
but this is not okay:
```
v1.sub0 =
... = v1.sub0
v1.sub1 = ...
```
Do I got that right?
https://github.com/llvm/llvm-project/pull/197580
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