https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/205791
Introduce the missing -mcpu argument to some tests which are not autogenerated. Co-Authored-By: Claude <[email protected]> (Claude-Opus-4.8) >From 7e2a762b5acd5984a082f573e9824b337bd98f5a Mon Sep 17 00:00:00 2001 From: Matt Arsenault <[email protected]> Date: Thu, 25 Jun 2026 11:45:02 +0200 Subject: [PATCH] AMDGPU: Avoid default subtarget in hand-written codegen tests (8/9) Introduce the missing -mcpu argument to some tests which are not autogenerated. Co-Authored-By: Claude <[email protected]> (Claude-Opus-4.8) --- llvm/test/CodeGen/AMDGPU/vop-shrink.ll | 2 +- llvm/test/CodeGen/AMDGPU/waitcnt-no-redundant.mir | 2 +- llvm/test/CodeGen/AMDGPU/waitcnt-trailing.mir | 2 +- llvm/test/CodeGen/AMDGPU/wave_dispatch_regs.ll | 4 ++-- llvm/test/CodeGen/AMDGPU/zext-i64-bit-operand.ll | 2 +- llvm/test/CodeGen/AMDGPU/zext-lid.ll | 4 ++-- 6 files changed, 8 insertions(+), 8 deletions(-) diff --git a/llvm/test/CodeGen/AMDGPU/vop-shrink.ll b/llvm/test/CodeGen/AMDGPU/vop-shrink.ll index 83c0ef70b45b8..33e382e5fb7a4 100644 --- a/llvm/test/CodeGen/AMDGPU/vop-shrink.ll +++ b/llvm/test/CodeGen/AMDGPU/vop-shrink.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; Test that we correctly commute a sub instruction diff --git a/llvm/test/CodeGen/AMDGPU/waitcnt-no-redundant.mir b/llvm/test/CodeGen/AMDGPU/waitcnt-no-redundant.mir index fbfa517007c70..e3aad7dddc1a7 100644 --- a/llvm/test/CodeGen/AMDGPU/waitcnt-no-redundant.mir +++ b/llvm/test/CodeGen/AMDGPU/waitcnt-no-redundant.mir @@ -1,4 +1,4 @@ -# RUN: llc -mtriple=amdgcn -verify-machineinstrs -run-pass si-insert-waitcnts -o - %s | FileCheck %s +# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -verify-machineinstrs -run-pass si-insert-waitcnts -o - %s | FileCheck %s # Check that the waitcnt pass does *not* insert a redundant waitcnt instr. # In this testcase, ensure that pass does not insert redundant S_WAITCNT 3952 diff --git a/llvm/test/CodeGen/AMDGPU/waitcnt-trailing.mir b/llvm/test/CodeGen/AMDGPU/waitcnt-trailing.mir index 38f40d3e18e2f..f8ecd01d0f8e3 100644 --- a/llvm/test/CodeGen/AMDGPU/waitcnt-trailing.mir +++ b/llvm/test/CodeGen/AMDGPU/waitcnt-trailing.mir @@ -1,4 +1,4 @@ -# RUN: llc -mtriple=amdgcn -verify-machineinstrs -run-pass si-insert-waitcnts -o - %s | FileCheck %s +# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -verify-machineinstrs -run-pass si-insert-waitcnts -o - %s | FileCheck %s # Check that a trivial soft waitcnt at the end of a block is deleted even if it # is followed by a meta instruction. diff --git a/llvm/test/CodeGen/AMDGPU/wave_dispatch_regs.ll b/llvm/test/CodeGen/AMDGPU/wave_dispatch_regs.ll index e2ef60bb80153..bb22cd08e062b 100644 --- a/llvm/test/CodeGen/AMDGPU/wave_dispatch_regs.ll +++ b/llvm/test/CodeGen/AMDGPU/wave_dispatch_regs.ll @@ -1,7 +1,7 @@ -; RUN: llc -global-isel=1 -mtriple=amdgcn--amdpal < %s | FileCheck -check-prefix=GCN -check-prefix=SI -enable-var-scope %s +; RUN: llc -global-isel=1 -mtriple=amdgcn--amdpal -mcpu=gfx600 < %s | FileCheck -check-prefix=GCN -check-prefix=SI -enable-var-scope %s ; RUN: llc -global-isel=1 -mtriple=amdgcn--amdpal -mcpu=tonga < %s | FileCheck -check-prefix=GCN -check-prefix=VI -enable-var-scope %s ; RUN: llc -global-isel=1 -mtriple=amdgcn--amdpal -mcpu=gfx900 < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -enable-var-scope %s -; RUN: llc -global-isel=0 -mtriple=amdgcn--amdpal < %s | FileCheck -check-prefix=GCN -check-prefix=SI -enable-var-scope %s +; RUN: llc -global-isel=0 -mtriple=amdgcn--amdpal -mcpu=gfx600 < %s | FileCheck -check-prefix=GCN -check-prefix=SI -enable-var-scope %s ; RUN: llc -global-isel=0 -mtriple=amdgcn--amdpal -mcpu=tonga < %s | FileCheck -check-prefix=GCN -check-prefix=VI -enable-var-scope %s ; RUN: llc -global-isel=0 -mtriple=amdgcn--amdpal -mcpu=gfx900 < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -enable-var-scope %s diff --git a/llvm/test/CodeGen/AMDGPU/zext-i64-bit-operand.ll b/llvm/test/CodeGen/AMDGPU/zext-i64-bit-operand.ll index 01a135e1e4cf9..ced74e56e0a33 100644 --- a/llvm/test/CodeGen/AMDGPU/zext-i64-bit-operand.ll +++ b/llvm/test/CodeGen/AMDGPU/zext-i64-bit-operand.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -check-prefix=GCN %s ; GCN-LABEL: {{^}}zext_or_operand_i64: ; GCN: buffer_load_dwordx2 v[[[LO:[0-9]+]]:[[HI:[0-9]+]]] diff --git a/llvm/test/CodeGen/AMDGPU/zext-lid.ll b/llvm/test/CodeGen/AMDGPU/zext-lid.ll index f6922d4e5ed7e..650fb0c3c117d 100644 --- a/llvm/test/CodeGen/AMDGPU/zext-lid.ll +++ b/llvm/test/CodeGen/AMDGPU/zext-lid.ll @@ -1,5 +1,5 @@ -; RUN: llc -mtriple=amdgcn < %s | FileCheck -enable-var-scope -check-prefixes=GCN,O2 %s -; RUN: llc -O0 -mtriple=amdgcn < %s | FileCheck -enable-var-scope -check-prefix=GCN %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,O2 %s +; RUN: llc -O0 -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -enable-var-scope -check-prefix=GCN %s ; GCN-LABEL: {{^}}zext_grp_size_128: ; O2-NOT: and_b32 _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
