https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/205790
Introduce an -mcpu argument to tests missing it to avoid codegening the default dummy target. These are cases that didn't require adjusting the check lines. Co-Authored-By: Claude <[email protected]> (Claude-Opus-4.8) >From 5176131c697d0db5c2264beb4ebc7e44bcc8ef20 Mon Sep 17 00:00:00 2001 From: Matt Arsenault <[email protected]> Date: Thu, 25 Jun 2026 11:44:54 +0200 Subject: [PATCH] AMDGPU: Avoid default subtarget in hand-written codegen tests (7/9) Introduce an -mcpu argument to tests missing it to avoid codegening the default dummy target. These are cases that didn't require adjusting the check lines. Co-Authored-By: Claude <[email protected]> (Claude-Opus-4.8) --- .../CodeGen/AMDGPU/machinelicm-convergent.mir | 4 +-- .../CodeGen/AMDGPU/mad24-get-global-id.ll | 2 +- .../CodeGen/AMDGPU/madak-inline-constant.mir | 4 +-- llvm/test/CodeGen/AMDGPU/madmk.ll | 2 +- llvm/test/CodeGen/AMDGPU/max-sgprs.ll | 2 +- llvm/test/CodeGen/AMDGPU/max3.ll | 2 +- llvm/test/CodeGen/AMDGPU/med3-no-simplify.ll | 2 +- llvm/test/CodeGen/AMDGPU/mem-builtins.ll | 2 +- .../AMDGPU/merge-load-store-physreg.mir | 2 +- llvm/test/CodeGen/AMDGPU/merge-load-store.mir | 2 +- llvm/test/CodeGen/AMDGPU/merge-m0.mir | 2 +- llvm/test/CodeGen/AMDGPU/min3.ll | 2 +- .../CodeGen/AMDGPU/mir-print-dead-csr-fi.mir | 2 +- llvm/test/CodeGen/AMDGPU/movrels-bug.mir | 4 +-- .../CodeGen/AMDGPU/mubuf-offset-private.ll | 2 +- .../AMDGPU/new-pm-machine-analysis.mir | 2 +- .../CodeGen/AMDGPU/no-hsa-graphics-shaders.ll | 2 +- .../test/CodeGen/AMDGPU/no-shrink-extloads.ll | 2 +- .../AMDGPU/nullptr-long-address-spaces.ll | 2 +- llvm/test/CodeGen/AMDGPU/nullptr.ll | 2 +- llvm/test/CodeGen/AMDGPU/omod-nsz-flag.mir | 2 +- .../CodeGen/AMDGPU/opencl-image-metadata.ll | 2 +- llvm/test/CodeGen/AMDGPU/operand-spacing.ll | 2 +- .../CodeGen/AMDGPU/opt_exec_copy_fold.mir | 2 +- .../AMDGPU/optimize-if-exec-masking.mir | 2 +- .../optimize-negated-cond-exec-masking.mir | 2 +- ...partially-dead-super-register-immediate.ll | 2 +- .../CodeGen/AMDGPU/preserve-user-waitcnt.ll | 2 +- .../promote-alloca-stored-pointer-value.ll | 4 +-- .../AMDGPU/ran-out-of-registers-errors.ll | 10 +++--- .../AMDGPU/read-register-invalid-type-i32.ll | 2 +- .../AMDGPU/read-register-invalid-type-i64.ll | 2 +- .../AMDGPU/reduce-load-width-alignment.ll | 2 +- llvm/test/CodeGen/AMDGPU/reduce-saveexec.mir | 2 +- .../AMDGPU/reduce-store-width-alignment.ll | 2 +- .../AMDGPU/regcoal-subrange-join-seg.mir | 2 +- .../CodeGen/AMDGPU/regcoal-subrange-join.mir | 2 +- llvm/test/CodeGen/AMDGPU/regcoalesce-dbg.mir | 2 +- .../test/CodeGen/AMDGPU/regcoalesce-prune.mir | 2 +- .../CodeGen/AMDGPU/register-count-comments.ll | 4 +-- .../remaining-virtual-register-operands.mir | 2 +- ...ename-independent-subregs-mac-operands.mir | 4 +-- .../AMDGPU/rename-independent-subregs.mir | 2 +- llvm/test/CodeGen/AMDGPU/reorder-stores.ll | 2 +- llvm/test/CodeGen/AMDGPU/rotl.i64.ll | 2 +- llvm/test/CodeGen/AMDGPU/rotr.i64.ll | 2 +- llvm/test/CodeGen/AMDGPU/s_movk_i32.ll | 2 +- .../CodeGen/AMDGPU/sched-crash-dbg-value.mir | 4 +-- .../AMDGPU/sched.barrier.inverted.mask.ll | 2 +- .../CodeGen/AMDGPU/schedule-global-loads.ll | 2 +- .../CodeGen/AMDGPU/schedule-regpressure.mir | 4 +-- .../schedule-vs-if-nested-loop-failure.ll | 2 +- llvm/test/CodeGen/AMDGPU/scratch-buffer.ll | 2 +- llvm/test/CodeGen/AMDGPU/sdivrem24.ll | 2 +- llvm/test/CodeGen/AMDGPU/select-opt.ll | 2 +- llvm/test/CodeGen/AMDGPU/selectcc-opt.ll | 2 +- llvm/test/CodeGen/AMDGPU/set-wave-priority.ll | 8 ++--- llvm/test/CodeGen/AMDGPU/setcc-opt.ll | 2 +- llvm/test/CodeGen/AMDGPU/setcc-sext.ll | 2 +- llvm/test/CodeGen/AMDGPU/setcc64.ll | 2 +- llvm/test/CodeGen/AMDGPU/sext-in-reg.ll | 2 +- .../AMDGPU/sgpr-copy-duplicate-operand.ll | 2 +- .../AMDGPU/sgpr-spill-wrong-stack-id.mir | 4 +-- llvm/test/CodeGen/AMDGPU/sgprcopies.ll | 2 +- .../CodeGen/AMDGPU/shrink-vop3-carry-out.mir | 4 +-- .../CodeGen/AMDGPU/si-annotate-cf-noloop.ll | 2 +- .../AMDGPU/si-annotate-cf-unreachable.ll | 2 +- .../CodeGen/AMDGPU/si-fix-sgpr-copies.mir | 4 +-- .../AMDGPU/si-lower-control-flow-kill.ll | 2 +- .../CodeGen/AMDGPU/si-lower-sgpr-spills.mir | 2 +- llvm/test/CodeGen/AMDGPU/si-spill-cf.ll | 2 +- llvm/test/CodeGen/AMDGPU/sint_to_fp.ll | 2 +- llvm/test/CodeGen/AMDGPU/skip-branch-trap.ll | 2 +- llvm/test/CodeGen/AMDGPU/smed3.ll | 2 +- .../test/CodeGen/AMDGPU/spill-before-exec.mir | 2 +- .../AMDGPU/spill-csr-frame-ptr-reg-copy.ll | 2 +- llvm/test/CodeGen/AMDGPU/spill-m0.ll | 2 +- .../CodeGen/AMDGPU/split-scalar-i64-add.ll | 2 +- .../CodeGen/AMDGPU/stack-size-overflow.ll | 4 +-- llvm/test/CodeGen/AMDGPU/store-barrier.ll | 2 +- llvm/test/CodeGen/AMDGPU/store-v3i64.ll | 2 +- llvm/test/CodeGen/AMDGPU/subreg-intervals.mir | 4 +-- .../CodeGen/AMDGPU/subreg_interference.mir | 2 +- llvm/test/CodeGen/AMDGPU/target-cpu.ll | 2 +- llvm/test/CodeGen/AMDGPU/trap.ll | 36 +++++++++---------- .../CodeGen/AMDGPU/trunc-store-f64-to-f16.ll | 2 +- llvm/test/CodeGen/AMDGPU/trunc-store-i1.ll | 2 +- .../twoaddr-regsequence-keep-copy-on-use.mir | 4 +-- llvm/test/CodeGen/AMDGPU/uint_to_fp.ll | 2 +- llvm/test/CodeGen/AMDGPU/umed3.ll | 2 +- .../CodeGen/AMDGPU/unaligned-load-store.ll | 2 +- .../test/CodeGen/AMDGPU/undef-build-vector.ll | 2 +- .../unhandled-loop-condition-assertion.ll | 2 +- .../CodeGen/AMDGPU/unigine-liveness-crash.ll | 2 +- llvm/test/CodeGen/AMDGPU/unsupported-calls.ll | 4 +-- llvm/test/CodeGen/AMDGPU/v_cvt_pk_u8_f32.ll | 2 +- llvm/test/CodeGen/AMDGPU/v_mac.ll | 2 +- llvm/test/CodeGen/AMDGPU/verify-sop.mir | 4 +-- .../CodeGen/AMDGPU/vop-shrink-frame-index.mir | 4 +-- .../CodeGen/AMDGPU/vop-shrink-non-ssa.mir | 4 +-- 100 files changed, 142 insertions(+), 142 deletions(-) diff --git a/llvm/test/CodeGen/AMDGPU/machinelicm-convergent.mir b/llvm/test/CodeGen/AMDGPU/machinelicm-convergent.mir index 9dc44c6e195e4..4fc50b642e299 100644 --- a/llvm/test/CodeGen/AMDGPU/machinelicm-convergent.mir +++ b/llvm/test/CodeGen/AMDGPU/machinelicm-convergent.mir @@ -1,5 +1,5 @@ -# RUN: llc -mtriple=amdgcn -run-pass=early-machinelicm -o - %s | FileCheck %s -# RUN: llc -mtriple=amdgcn -passes=early-machinelicm -o - %s | FileCheck %s +# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -run-pass=early-machinelicm -o - %s | FileCheck %s +# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -passes=early-machinelicm -o - %s | FileCheck %s # Test to check machine LICM does not hoist convergent instructions, # DS_PERMUTE_B32 in this example. diff --git a/llvm/test/CodeGen/AMDGPU/mad24-get-global-id.ll b/llvm/test/CodeGen/AMDGPU/mad24-get-global-id.ll index 9d0e65bad8244..50347236bb7ae 100644 --- a/llvm/test/CodeGen/AMDGPU/mad24-get-global-id.ll +++ b/llvm/test/CodeGen/AMDGPU/mad24-get-global-id.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn--amdhsa < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx700 < %s | FileCheck -check-prefix=GCN %s ; If the workgroup id range is restricted, we should be able to use ; mad24 for the usual indexing pattern. diff --git a/llvm/test/CodeGen/AMDGPU/madak-inline-constant.mir b/llvm/test/CodeGen/AMDGPU/madak-inline-constant.mir index 6e7f5b5492148..fcc92dcd23b7c 100644 --- a/llvm/test/CodeGen/AMDGPU/madak-inline-constant.mir +++ b/llvm/test/CodeGen/AMDGPU/madak-inline-constant.mir @@ -1,5 +1,5 @@ -# RUN: llc -mtriple=amdgcn -run-pass peephole-opt -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s -# RUN: llc -mtriple=amdgcn -run-pass peephole-opt -verify-machineinstrs -o - %s -debugify-and-strip-all-safe | FileCheck -check-prefix=GCN %s +# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -run-pass peephole-opt -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s +# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -run-pass peephole-opt -verify-machineinstrs -o - %s -debugify-and-strip-all-safe | FileCheck -check-prefix=GCN %s # GCN-LABEL: bb.0: # GCN: S_MOV_B32 1082130432 diff --git a/llvm/test/CodeGen/AMDGPU/madmk.ll b/llvm/test/CodeGen/AMDGPU/madmk.ll index 7b96296172035..720b9834ea974 100644 --- a/llvm/test/CodeGen/AMDGPU/madmk.ll +++ b/llvm/test/CodeGen/AMDGPU/madmk.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn -mattr=+mad-mac-f32-insts < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx600 -mattr=+mad-mac-f32-insts < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s ; XUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; FIXME: None of these trigger madmk emission anymore. It is still diff --git a/llvm/test/CodeGen/AMDGPU/max-sgprs.ll b/llvm/test/CodeGen/AMDGPU/max-sgprs.ll index 429e3cb43328c..b6362a2763811 100644 --- a/llvm/test/CodeGen/AMDGPU/max-sgprs.ll +++ b/llvm/test/CodeGen/AMDGPU/max-sgprs.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -check-prefix=GCN %s ; GCN-LABEL: {{^}}max_sgprs_gfx10: ; GCN: NumSgprs: 108 diff --git a/llvm/test/CodeGen/AMDGPU/max3.ll b/llvm/test/CodeGen/AMDGPU/max3.ll index b922854b9c52a..5bbf6c8527a8d 100644 --- a/llvm/test/CodeGen/AMDGPU/max3.ll +++ b/llvm/test/CodeGen/AMDGPU/max3.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn < %s | FileCheck -check-prefixes=GCN,SI %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -check-prefixes=GCN,SI %s ; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=GCN,VI %s ; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9,GFX9_1250 %s ; RUN: llc -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GCN,GFX1250,GFX9_1250 %s diff --git a/llvm/test/CodeGen/AMDGPU/med3-no-simplify.ll b/llvm/test/CodeGen/AMDGPU/med3-no-simplify.ll index 1b3a62628abd6..7d5cb5d48ac6e 100644 --- a/llvm/test/CodeGen/AMDGPU/med3-no-simplify.ll +++ b/llvm/test/CodeGen/AMDGPU/med3-no-simplify.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn -amdgpu-scalar-ir-passes=false < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx600 -amdgpu-scalar-ir-passes=false < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global -amdgpu-scalar-ir-passes=false < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -mattr=-flat-for-global -amdgpu-scalar-ir-passes=false < %s | FileCheck -check-prefix=GCN %s diff --git a/llvm/test/CodeGen/AMDGPU/mem-builtins.ll b/llvm/test/CodeGen/AMDGPU/mem-builtins.ll index 99090da4da513..ba09608d61446 100644 --- a/llvm/test/CodeGen/AMDGPU/mem-builtins.ll +++ b/llvm/test/CodeGen/AMDGPU/mem-builtins.ll @@ -1,5 +1,5 @@ ; RUN: not llc -mtriple=r600 < %s 2>&1 | FileCheck -check-prefix=ERROR %s -; RUN: llc -mtriple=amdgcn < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -check-prefix=GCN %s declare hidden i32 @memcmp(ptr addrspace(1) readonly nocapture, ptr addrspace(1) readonly nocapture, i64) #0 declare hidden ptr addrspace(1) @memchr(ptr addrspace(1) readonly nocapture, i32, i64) #1 diff --git a/llvm/test/CodeGen/AMDGPU/merge-load-store-physreg.mir b/llvm/test/CodeGen/AMDGPU/merge-load-store-physreg.mir index 9c02c935b9498..68e9302ff2a57 100644 --- a/llvm/test/CodeGen/AMDGPU/merge-load-store-physreg.mir +++ b/llvm/test/CodeGen/AMDGPU/merge-load-store-physreg.mir @@ -1,4 +1,4 @@ -# RUN: llc -mtriple=amdgcn -verify-machineinstrs -run-pass si-load-store-opt -o - %s | FileCheck %s +# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -verify-machineinstrs -run-pass si-load-store-opt -o - %s | FileCheck %s # Check that SILoadStoreOptimizer honors physregs defs/uses between moved # instructions. diff --git a/llvm/test/CodeGen/AMDGPU/merge-load-store.mir b/llvm/test/CodeGen/AMDGPU/merge-load-store.mir index d8ee4712a8917..bd2b783d20e52 100644 --- a/llvm/test/CodeGen/AMDGPU/merge-load-store.mir +++ b/llvm/test/CodeGen/AMDGPU/merge-load-store.mir @@ -1,4 +1,4 @@ -# RUN: llc -mtriple=amdgcn -verify-machineinstrs -run-pass si-load-store-opt -o - %s | FileCheck %s +# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -verify-machineinstrs -run-pass si-load-store-opt -o - %s | FileCheck %s # Check that SILoadStoreOptimizer honors memory dependencies between moved # instructions. diff --git a/llvm/test/CodeGen/AMDGPU/merge-m0.mir b/llvm/test/CodeGen/AMDGPU/merge-m0.mir index 614ee6762a27b..721e69320dcb3 100644 --- a/llvm/test/CodeGen/AMDGPU/merge-m0.mir +++ b/llvm/test/CodeGen/AMDGPU/merge-m0.mir @@ -1,4 +1,4 @@ -# RUN: llc -mtriple=amdgcn -amdgpu-enable-merge-m0 -verify-machineinstrs -run-pass si-fix-sgpr-copies %s -o - | FileCheck -check-prefix=GCN %s +# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -amdgpu-enable-merge-m0 -verify-machineinstrs -run-pass si-fix-sgpr-copies %s -o - | FileCheck -check-prefix=GCN %s # GCN-LABEL: name: merge-m0-many-init # GCN: bb.0.entry: diff --git a/llvm/test/CodeGen/AMDGPU/min3.ll b/llvm/test/CodeGen/AMDGPU/min3.ll index 82452c861769b..de5527fe24c55 100644 --- a/llvm/test/CodeGen/AMDGPU/min3.ll +++ b/llvm/test/CodeGen/AMDGPU/min3.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn < %s | FileCheck -check-prefixes=GCN,SI %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -check-prefixes=GCN,SI %s ; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=GCN,VI %s ; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9,GFX9_1250 %s ; RUN: llc -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GCN,GFX1250,GFX9_1250 %s diff --git a/llvm/test/CodeGen/AMDGPU/mir-print-dead-csr-fi.mir b/llvm/test/CodeGen/AMDGPU/mir-print-dead-csr-fi.mir index 71c7e32ff23b3..206f5acb5789a 100644 --- a/llvm/test/CodeGen/AMDGPU/mir-print-dead-csr-fi.mir +++ b/llvm/test/CodeGen/AMDGPU/mir-print-dead-csr-fi.mir @@ -1,4 +1,4 @@ -# RUN: llc -mtriple=amdgcn-amd-amdhsa -run-pass=prologepilog -o - %s | FileCheck %s +# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -run-pass=prologepilog -o - %s | FileCheck %s # Make sure the MIR printer doesn't crash when there are dead frame indexes. The # CSR SGPR frame indexes are inserted, but deleted. diff --git a/llvm/test/CodeGen/AMDGPU/movrels-bug.mir b/llvm/test/CodeGen/AMDGPU/movrels-bug.mir index e20de8c745388..4ec56fbe28024 100644 --- a/llvm/test/CodeGen/AMDGPU/movrels-bug.mir +++ b/llvm/test/CodeGen/AMDGPU/movrels-bug.mir @@ -1,5 +1,5 @@ -# RUN: llc -mtriple=amdgcn -verify-machineinstrs -run-pass post-RA-sched %s -o - | FileCheck %s -# RUN: llc -mtriple=amdgcn -passes=post-RA-sched %s -o - | FileCheck %s +# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -verify-machineinstrs -run-pass post-RA-sched %s -o - | FileCheck %s +# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -passes=post-RA-sched %s -o - | FileCheck %s # This tests a situation where a sub-register of a killed super-register operand # of V_MOVRELS happens to have an undef use later on. This leads to the post RA diff --git a/llvm/test/CodeGen/AMDGPU/mubuf-offset-private.ll b/llvm/test/CodeGen/AMDGPU/mubuf-offset-private.ll index 7e2bfa666a19f..e4e037a17a57b 100644 --- a/llvm/test/CodeGen/AMDGPU/mubuf-offset-private.ll +++ b/llvm/test/CodeGen/AMDGPU/mubuf-offset-private.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn -mattr=+max-private-element-size-16 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SICIVI %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx600 -mattr=+max-private-element-size-16 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SICIVI %s ; RUN: llc -mtriple=amdgcn -mcpu=fiji -mattr=+max-private-element-size-16 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SICIVI %s ; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -mattr=+max-private-element-size-16 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s diff --git a/llvm/test/CodeGen/AMDGPU/new-pm-machine-analysis.mir b/llvm/test/CodeGen/AMDGPU/new-pm-machine-analysis.mir index d11ef50cbdc8f..03e1b3a0d2caf 100644 --- a/llvm/test/CodeGen/AMDGPU/new-pm-machine-analysis.mir +++ b/llvm/test/CodeGen/AMDGPU/new-pm-machine-analysis.mir @@ -1,4 +1,4 @@ -# RUN: llc -mtriple=amdgcn \ +# RUN: llc -mtriple=amdgcn -mcpu=gfx600 \ # RUN: "-passes=require<amdgpu-resource-usage>,invalidate<amdgpu-resource-usage>" \ # RUN: --print-pipeline-passes --filetype=null %s | FileCheck %s diff --git a/llvm/test/CodeGen/AMDGPU/no-hsa-graphics-shaders.ll b/llvm/test/CodeGen/AMDGPU/no-hsa-graphics-shaders.ll index 60d1df11bfddf..824264dfd61a4 100644 --- a/llvm/test/CodeGen/AMDGPU/no-hsa-graphics-shaders.ll +++ b/llvm/test/CodeGen/AMDGPU/no-hsa-graphics-shaders.ll @@ -1,4 +1,4 @@ -; RUN: not llc -mtriple=amdgcn-unknown-amdhsa -O0 -filetype=null < %s 2>&1 | FileCheck %s +; RUN: not llc -mtriple=amdgcn-unknown-amdhsa -mcpu=gfx700 -O0 -filetype=null < %s 2>&1 | FileCheck %s @I = global i32 42 @P = global ptr @I diff --git a/llvm/test/CodeGen/AMDGPU/no-shrink-extloads.ll b/llvm/test/CodeGen/AMDGPU/no-shrink-extloads.ll index afb289bd28ecf..3de4d29cd21ba 100644 --- a/llvm/test/CodeGen/AMDGPU/no-shrink-extloads.ll +++ b/llvm/test/CodeGen/AMDGPU/no-shrink-extloads.ll @@ -1,4 +1,4 @@ -; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s +; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone diff --git a/llvm/test/CodeGen/AMDGPU/nullptr-long-address-spaces.ll b/llvm/test/CodeGen/AMDGPU/nullptr-long-address-spaces.ll index e039225dba3e7..faf4b4077cc47 100644 --- a/llvm/test/CodeGen/AMDGPU/nullptr-long-address-spaces.ll +++ b/llvm/test/CodeGen/AMDGPU/nullptr-long-address-spaces.ll @@ -1,6 +1,6 @@ ; XFAIL: * ; REQUIRES: asserts -; RUN: llc -mtriple=amdgcn-- < %s +; RUN: llc -mtriple=amdgcn-- -mcpu=gfx600 < %s ; This is a temporary xfail, as the assembly printer is broken when dealing with ; lowerConstant() trying to return a value of size greater than 8 bytes. diff --git a/llvm/test/CodeGen/AMDGPU/nullptr.ll b/llvm/test/CodeGen/AMDGPU/nullptr.ll index 1552014dc24e0..79c11fb2a7c37 100644 --- a/llvm/test/CodeGen/AMDGPU/nullptr.ll +++ b/llvm/test/CodeGen/AMDGPU/nullptr.ll @@ -1,4 +1,4 @@ -;RUN: llc < %s -mtriple=amdgcn-- | FileCheck -check-prefixes=CHECK,GCN %s +;RUN: llc < %s -mtriple=amdgcn-- -mcpu=gfx600 | FileCheck -check-prefixes=CHECK,GCN %s ;RUN: llc < %s -mtriple=r600-- | FileCheck -check-prefixes=CHECK,R600 %s %struct.S = type { ptr addrspace(5), ptr addrspace(1), ptr addrspace(4), ptr addrspace(3), ptr, ptr addrspace(2)} diff --git a/llvm/test/CodeGen/AMDGPU/omod-nsz-flag.mir b/llvm/test/CodeGen/AMDGPU/omod-nsz-flag.mir index 1bcddf7d35946..c721b747a5c5a 100644 --- a/llvm/test/CodeGen/AMDGPU/omod-nsz-flag.mir +++ b/llvm/test/CodeGen/AMDGPU/omod-nsz-flag.mir @@ -1,4 +1,4 @@ -# RUN: llc -mtriple=amdgcn -verify-machineinstrs -run-pass si-fold-operands -mattr=+dx10-clamp-and-ieee-mode %s -o - | FileCheck -check-prefix=GCN %s +# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -verify-machineinstrs -run-pass si-fold-operands -mattr=+dx10-clamp-and-ieee-mode %s -o - | FileCheck -check-prefix=GCN %s --- diff --git a/llvm/test/CodeGen/AMDGPU/opencl-image-metadata.ll b/llvm/test/CodeGen/AMDGPU/opencl-image-metadata.ll index 000d3132171a3..fde295ef61f41 100644 --- a/llvm/test/CodeGen/AMDGPU/opencl-image-metadata.ll +++ b/llvm/test/CodeGen/AMDGPU/opencl-image-metadata.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=amdgcn | FileCheck --check-prefix=SI %s +; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx600 | FileCheck --check-prefix=SI %s ; RUN: llc < %s -mtriple=r600 -mcpu=redwood | FileCheck --check-prefix=EG %s ; Make sure the OpenCL Image lowering pass doesn't crash when argument metadata diff --git a/llvm/test/CodeGen/AMDGPU/operand-spacing.ll b/llvm/test/CodeGen/AMDGPU/operand-spacing.ll index 98d48e505fe6d..96c9f6bec4e69 100644 --- a/llvm/test/CodeGen/AMDGPU/operand-spacing.ll +++ b/llvm/test/CodeGen/AMDGPU/operand-spacing.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn < %s | FileCheck -strict-whitespace -check-prefix=SI -check-prefix=GCN %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -strict-whitespace -check-prefix=SI -check-prefix=GCN %s ; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -strict-whitespace -check-prefix=VI -check-prefix=GCN %s ; Make sure there isn't an extra space between the instruction name and first operands. diff --git a/llvm/test/CodeGen/AMDGPU/opt_exec_copy_fold.mir b/llvm/test/CodeGen/AMDGPU/opt_exec_copy_fold.mir index 8adbf284054d6..f8128cbe3e53d 100644 --- a/llvm/test/CodeGen/AMDGPU/opt_exec_copy_fold.mir +++ b/llvm/test/CodeGen/AMDGPU/opt_exec_copy_fold.mir @@ -1,4 +1,4 @@ -# RUN: llc -run-pass si-optimize-exec-masking-pre-ra -mtriple=amdgcn -verify-machineinstrs -o - %s | FileCheck --check-prefixes=GCN %s +# RUN: llc -run-pass si-optimize-exec-masking-pre-ra -mtriple=amdgcn -mcpu=gfx600 -verify-machineinstrs -o - %s | FileCheck --check-prefixes=GCN %s --- # GCN-LABEL: name: opt_exec_copy_fold # GCN: %2:vreg_64 = COPY $exec diff --git a/llvm/test/CodeGen/AMDGPU/optimize-if-exec-masking.mir b/llvm/test/CodeGen/AMDGPU/optimize-if-exec-masking.mir index 0d8334cf09606..efe1ca91fb29c 100644 --- a/llvm/test/CodeGen/AMDGPU/optimize-if-exec-masking.mir +++ b/llvm/test/CodeGen/AMDGPU/optimize-if-exec-masking.mir @@ -1,4 +1,4 @@ -# RUN: llc -mtriple=amdgcn -verify-machineinstrs -run-pass si-optimize-exec-masking -o - %s | FileCheck %s +# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -verify-machineinstrs -run-pass si-optimize-exec-masking -o - %s | FileCheck %s --- | define amdgpu_kernel void @optimize_if_and_saveexec_xor(i32 %z, i32 %v) { diff --git a/llvm/test/CodeGen/AMDGPU/optimize-negated-cond-exec-masking.mir b/llvm/test/CodeGen/AMDGPU/optimize-negated-cond-exec-masking.mir index e1b41bc868974..549668130236c 100644 --- a/llvm/test/CodeGen/AMDGPU/optimize-negated-cond-exec-masking.mir +++ b/llvm/test/CodeGen/AMDGPU/optimize-negated-cond-exec-masking.mir @@ -1,4 +1,4 @@ -# RUN: llc -mtriple=amdgcn -verify-machineinstrs -run-pass=si-optimize-exec-masking-pre-ra -o - %s | FileCheck -check-prefix=GCN %s +# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -verify-machineinstrs -run-pass=si-optimize-exec-masking-pre-ra -o - %s | FileCheck -check-prefix=GCN %s # GCN: name: negated_cond_vop2 # GCN: %0:sreg_64_xexec = IMPLICIT_DEF diff --git a/llvm/test/CodeGen/AMDGPU/partially-dead-super-register-immediate.ll b/llvm/test/CodeGen/AMDGPU/partially-dead-super-register-immediate.ll index c7b2125862b03..92a8a18a9aede 100644 --- a/llvm/test/CodeGen/AMDGPU/partially-dead-super-register-immediate.ll +++ b/llvm/test/CodeGen/AMDGPU/partially-dead-super-register-immediate.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn -verify-coalescing < %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx600 -verify-coalescing < %s ; The original and requires materializing a 64-bit immediate for ; s_and_b64. This is split into 2 x v_and_i32, part of the immediate diff --git a/llvm/test/CodeGen/AMDGPU/preserve-user-waitcnt.ll b/llvm/test/CodeGen/AMDGPU/preserve-user-waitcnt.ll index cd6ab0b210844..8cd62abf518fd 100644 --- a/llvm/test/CodeGen/AMDGPU/preserve-user-waitcnt.ll +++ b/llvm/test/CodeGen/AMDGPU/preserve-user-waitcnt.ll @@ -1,4 +1,4 @@ -; RUN: llc -O3 -mtriple=amdgcn < %s | FileCheck --check-prefix=CHECK %s +; RUN: llc -O3 -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck --check-prefix=CHECK %s ; SIInsertWaitcnts should preserve waitcnt instructions coming from the user diff --git a/llvm/test/CodeGen/AMDGPU/promote-alloca-stored-pointer-value.ll b/llvm/test/CodeGen/AMDGPU/promote-alloca-stored-pointer-value.ll index 0a9346326d7d4..1e9a4e83b510b 100644 --- a/llvm/test/CodeGen/AMDGPU/promote-alloca-stored-pointer-value.ll +++ b/llvm/test/CodeGen/AMDGPU/promote-alloca-stored-pointer-value.ll @@ -1,5 +1,5 @@ -; RUN: llc -mtriple=amdgcn -mattr=+max-private-element-size-4 < %s | FileCheck -check-prefix=GCN %s -; RUN: llc -mtriple=amdgcn -disable-promote-alloca-to-vector -disable-promote-alloca-to-lds -mattr=+max-private-element-size-4 < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx600 -mattr=+max-private-element-size-4 < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx600 -disable-promote-alloca-to-vector -disable-promote-alloca-to-lds -mattr=+max-private-element-size-4 < %s | FileCheck -check-prefix=GCN %s ; Pointer value is stored in a candidate for LDS usage. diff --git a/llvm/test/CodeGen/AMDGPU/ran-out-of-registers-errors.ll b/llvm/test/CodeGen/AMDGPU/ran-out-of-registers-errors.ll index bd1752d21507c..d27f45f5813db 100644 --- a/llvm/test/CodeGen/AMDGPU/ran-out-of-registers-errors.ll +++ b/llvm/test/CodeGen/AMDGPU/ran-out-of-registers-errors.ll @@ -1,9 +1,9 @@ -; RUN: not llc -mtriple=amdgcn-amd-amdhsa -stress-regalloc=1 -vgpr-regalloc=greedy -filetype=null %s 2>&1 | FileCheck -check-prefixes=CHECK,GREEDY -implicit-check-not=error %s -; RUN: not llc -mtriple=amdgcn-amd-amdhsa -stress-regalloc=1 -vgpr-regalloc=basic -filetype=null %s 2>&1 | FileCheck -implicit-check-not=error -check-prefixes=CHECK,BASIC %s -; RUN: not llc -mtriple=amdgcn-amd-amdhsa -stress-regalloc=1 -vgpr-regalloc=fast -filetype=null %s 2>&1 | FileCheck -implicit-check-not=error -check-prefixes=CHECK,FAST %s +; RUN: not llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -stress-regalloc=1 -vgpr-regalloc=greedy -filetype=null %s 2>&1 | FileCheck -check-prefixes=CHECK,GREEDY -implicit-check-not=error %s +; RUN: not llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -stress-regalloc=1 -vgpr-regalloc=basic -filetype=null %s 2>&1 | FileCheck -implicit-check-not=error -check-prefixes=CHECK,BASIC %s +; RUN: not llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -stress-regalloc=1 -vgpr-regalloc=fast -filetype=null %s 2>&1 | FileCheck -implicit-check-not=error -check-prefixes=CHECK,FAST %s ; RUN: opt -passes=debugify -o %t.bc %s -; RUN: not llc -mtriple=amdgcn-amd-amdhsa -stress-regalloc=1 -vgpr-regalloc=greedy -filetype=null %t.bc 2>&1 | FileCheck -implicit-check-not=error -check-prefixes=DBGINFO-CHECK,DBGINFO-GREEDY %s -; RUN: not llc -mtriple=amdgcn-amd-amdhsa -stress-regalloc=1 -vgpr-regalloc=basic -filetype=null %t.bc 2>&1 | FileCheck -implicit-check-not=error -check-prefixes=DBGINFO-CHECK,DBGINFO-BASIC %s +; RUN: not llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -stress-regalloc=1 -vgpr-regalloc=greedy -filetype=null %t.bc 2>&1 | FileCheck -implicit-check-not=error -check-prefixes=DBGINFO-CHECK,DBGINFO-GREEDY %s +; RUN: not llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -stress-regalloc=1 -vgpr-regalloc=basic -filetype=null %t.bc 2>&1 | FileCheck -implicit-check-not=error -check-prefixes=DBGINFO-CHECK,DBGINFO-BASIC %s ; FIXME: Asserts when using -O2 + -vgpr-regalloc=fast ; RUN: not llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -stress-regalloc=1 -O0 -filetype=null %t.bc 2>&1 | FileCheck -implicit-check-not=error -check-prefixes=DBGINFO-CHECK,DBGINFO-FAST %s diff --git a/llvm/test/CodeGen/AMDGPU/read-register-invalid-type-i32.ll b/llvm/test/CodeGen/AMDGPU/read-register-invalid-type-i32.ll index 8e78178da7230..9a6f0eadc1a06 100644 --- a/llvm/test/CodeGen/AMDGPU/read-register-invalid-type-i32.ll +++ b/llvm/test/CodeGen/AMDGPU/read-register-invalid-type-i32.ll @@ -1,4 +1,4 @@ -; RUN: not --crash llc -mtriple=amdgcn < %s 2>&1 | FileCheck %s +; RUN: not --crash llc -mtriple=amdgcn -mcpu=gfx600 < %s 2>&1 | FileCheck %s ; CHECK: invalid type for register "exec". diff --git a/llvm/test/CodeGen/AMDGPU/read-register-invalid-type-i64.ll b/llvm/test/CodeGen/AMDGPU/read-register-invalid-type-i64.ll index 8e0de52aaa6bc..52fd8e4faebfd 100644 --- a/llvm/test/CodeGen/AMDGPU/read-register-invalid-type-i64.ll +++ b/llvm/test/CodeGen/AMDGPU/read-register-invalid-type-i64.ll @@ -1,4 +1,4 @@ -; RUN: not --crash llc -mtriple=amdgcn < %s 2>&1 | FileCheck %s +; RUN: not --crash llc -mtriple=amdgcn -mcpu=gfx600 < %s 2>&1 | FileCheck %s ; CHECK: invalid type for register "m0". diff --git a/llvm/test/CodeGen/AMDGPU/reduce-load-width-alignment.ll b/llvm/test/CodeGen/AMDGPU/reduce-load-width-alignment.ll index 47f0c4cd35892..d26d39cc89f79 100644 --- a/llvm/test/CodeGen/AMDGPU/reduce-load-width-alignment.ll +++ b/llvm/test/CodeGen/AMDGPU/reduce-load-width-alignment.ll @@ -1,4 +1,4 @@ -; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=bonaire < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -check-prefix=GCN %s diff --git a/llvm/test/CodeGen/AMDGPU/reduce-saveexec.mir b/llvm/test/CodeGen/AMDGPU/reduce-saveexec.mir index 3f014ff558b51..bce9c0d96f3e5 100644 --- a/llvm/test/CodeGen/AMDGPU/reduce-saveexec.mir +++ b/llvm/test/CodeGen/AMDGPU/reduce-saveexec.mir @@ -1,4 +1,4 @@ -# RUN: llc -mtriple=amdgcn -verify-machineinstrs -run-pass si-optimize-exec-masking %s -o - | FileCheck -check-prefix=GCN %s +# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -verify-machineinstrs -run-pass si-optimize-exec-masking %s -o - | FileCheck -check-prefix=GCN %s --- # GCN-LABEL: name: reduce_and_saveexec diff --git a/llvm/test/CodeGen/AMDGPU/reduce-store-width-alignment.ll b/llvm/test/CodeGen/AMDGPU/reduce-store-width-alignment.ll index d73ab2bcf67e8..75d774df4c7dd 100644 --- a/llvm/test/CodeGen/AMDGPU/reduce-store-width-alignment.ll +++ b/llvm/test/CodeGen/AMDGPU/reduce-store-width-alignment.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -check-prefix=GCN %s ; GCN-LABEL: {{^}}store_v2i32_as_v4i16_align_4: ; GCN: s_load_dwordx2 diff --git a/llvm/test/CodeGen/AMDGPU/regcoal-subrange-join-seg.mir b/llvm/test/CodeGen/AMDGPU/regcoal-subrange-join-seg.mir index f0e5bb3f0faed..7f2fd9ac74fa9 100644 --- a/llvm/test/CodeGen/AMDGPU/regcoal-subrange-join-seg.mir +++ b/llvm/test/CodeGen/AMDGPU/regcoal-subrange-join-seg.mir @@ -1,4 +1,4 @@ -# RUN: llc -mtriple=amdgcn -run-pass register-coalescer -o - %s | FileCheck --check-prefix=GCN %s +# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -run-pass register-coalescer -o - %s | FileCheck --check-prefix=GCN %s # REQUIRES: asserts # # This test will provoke a Couldn't join subrange unreachable without the diff --git a/llvm/test/CodeGen/AMDGPU/regcoal-subrange-join.mir b/llvm/test/CodeGen/AMDGPU/regcoal-subrange-join.mir index a0c240671bebc..bddb8224c8228 100644 --- a/llvm/test/CodeGen/AMDGPU/regcoal-subrange-join.mir +++ b/llvm/test/CodeGen/AMDGPU/regcoal-subrange-join.mir @@ -1,4 +1,4 @@ -# RUN: llc -mtriple=amdgcn -run-pass register-coalescer -o - %s | FileCheck --check-prefix=GCN %s +# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -run-pass register-coalescer -o - %s | FileCheck --check-prefix=GCN %s # # See bug http://llvm.org/PR33524 for details of the problem being checked here # This test will provoke a subrange join (see annotations below) during register coalescing diff --git a/llvm/test/CodeGen/AMDGPU/regcoalesce-dbg.mir b/llvm/test/CodeGen/AMDGPU/regcoalesce-dbg.mir index b15b051331066..4e7b49d898d02 100644 --- a/llvm/test/CodeGen/AMDGPU/regcoalesce-dbg.mir +++ b/llvm/test/CodeGen/AMDGPU/regcoalesce-dbg.mir @@ -1,4 +1,4 @@ -# RUN: llc -mtriple=amdgcn -run-pass register-coalescer -o - %s | FileCheck %s +# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -run-pass register-coalescer -o - %s | FileCheck %s # Test that register coalescing does not allow a call to # LIS->getInstructionIndex with a DBG_VALUE instruction, which does not have diff --git a/llvm/test/CodeGen/AMDGPU/regcoalesce-prune.mir b/llvm/test/CodeGen/AMDGPU/regcoalesce-prune.mir index e18989c13476b..999d07146d563 100644 --- a/llvm/test/CodeGen/AMDGPU/regcoalesce-prune.mir +++ b/llvm/test/CodeGen/AMDGPU/regcoalesce-prune.mir @@ -1,4 +1,4 @@ -# RUN: llc -o - %s -mtriple=amdgcn-amd-amdhsa-opencl -run-pass=register-coalescer | FileCheck %s +# RUN: llc -o - %s -mtriple=amdgcn-amd-amdhsa-opencl -mcpu=gfx700 -run-pass=register-coalescer | FileCheck %s --- # Checks for a bug where subregister liveranges were not properly pruned for # an IMPLCITI_DEF that gets removed completely. diff --git a/llvm/test/CodeGen/AMDGPU/register-count-comments.ll b/llvm/test/CodeGen/AMDGPU/register-count-comments.ll index 4571f3278fefd..b6664f2cc1030 100644 --- a/llvm/test/CodeGen/AMDGPU/register-count-comments.ll +++ b/llvm/test/CodeGen/AMDGPU/register-count-comments.ll @@ -1,5 +1,5 @@ -; RUN: llc -mtriple=amdgcn -asm-verbose < %s | FileCheck -check-prefix=SI %s -; RUN: llc -mtriple=amdgcn-unknown-amdhsa -asm-verbose -mattr=-flat-for-global < %s | FileCheck -check-prefix=SI %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx600 -asm-verbose < %s | FileCheck -check-prefix=SI %s +; RUN: llc -mtriple=amdgcn-unknown-amdhsa -mcpu=gfx700 -asm-verbose -mattr=-flat-for-global < %s | FileCheck -check-prefix=SI %s declare i32 @llvm.amdgcn.mbcnt.lo(i32, i32) #0 declare i32 @llvm.amdgcn.mbcnt.hi(i32, i32) #0 diff --git a/llvm/test/CodeGen/AMDGPU/remaining-virtual-register-operands.mir b/llvm/test/CodeGen/AMDGPU/remaining-virtual-register-operands.mir index f6c5d6930415d..2613f7d8757a1 100644 --- a/llvm/test/CodeGen/AMDGPU/remaining-virtual-register-operands.mir +++ b/llvm/test/CodeGen/AMDGPU/remaining-virtual-register-operands.mir @@ -1,4 +1,4 @@ -# RUN: not llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -start-before=greedy,2 -filetype=null %s 2>&1 | FileCheck %s +# RUN: not llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -verify-machineinstrs -start-before=greedy,2 -filetype=null %s 2>&1 | FileCheck %s # This testcase fails register allocation at the same time it performs # virtual register splitting (by introducing VGPR to AGPR copies). We diff --git a/llvm/test/CodeGen/AMDGPU/rename-independent-subregs-mac-operands.mir b/llvm/test/CodeGen/AMDGPU/rename-independent-subregs-mac-operands.mir index daa9997f69f6c..570ff239f0609 100644 --- a/llvm/test/CodeGen/AMDGPU/rename-independent-subregs-mac-operands.mir +++ b/llvm/test/CodeGen/AMDGPU/rename-independent-subregs-mac-operands.mir @@ -1,5 +1,5 @@ -# RUN: llc -mtriple=amdgcn -verify-machineinstrs -run-pass=register-coalescer,rename-independent-subregs -o - %s | FileCheck -check-prefix=GCN %s -# RUN: llc -mtriple=amdgcn -passes=register-coalescer,rename-independent-subregs -o - %s | FileCheck -check-prefix=GCN %s +# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -verify-machineinstrs -run-pass=register-coalescer,rename-independent-subregs -o - %s | FileCheck -check-prefix=GCN %s +# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -passes=register-coalescer,rename-independent-subregs -o - %s | FileCheck -check-prefix=GCN %s --- # GCN-LABEL: name: mac_invalid_operands diff --git a/llvm/test/CodeGen/AMDGPU/rename-independent-subregs.mir b/llvm/test/CodeGen/AMDGPU/rename-independent-subregs.mir index 60b69acf3d58a..94a8ad022b295 100644 --- a/llvm/test/CodeGen/AMDGPU/rename-independent-subregs.mir +++ b/llvm/test/CodeGen/AMDGPU/rename-independent-subregs.mir @@ -1,4 +1,4 @@ -# RUN: llc -mtriple=amdgcn -verify-machineinstrs -run-pass register-coalescer,rename-independent-subregs -o - %s | FileCheck %s +# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -verify-machineinstrs -run-pass register-coalescer,rename-independent-subregs -o - %s | FileCheck %s --- | define amdgpu_kernel void @test0() { ret void } define amdgpu_kernel void @test1() { ret void } diff --git a/llvm/test/CodeGen/AMDGPU/reorder-stores.ll b/llvm/test/CodeGen/AMDGPU/reorder-stores.ll index a06e54e79f72a..1ad6b0b49fb4d 100644 --- a/llvm/test/CodeGen/AMDGPU/reorder-stores.ll +++ b/llvm/test/CodeGen/AMDGPU/reorder-stores.ll @@ -1,4 +1,4 @@ -; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn < %s | FileCheck -check-prefixes=GCN,SI %s +; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -check-prefixes=GCN,SI %s ; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -check-prefixes=GCN,VI %s ; GCN-LABEL: {{^}}no_reorder_v2f64_global_load_store: diff --git a/llvm/test/CodeGen/AMDGPU/rotl.i64.ll b/llvm/test/CodeGen/AMDGPU/rotl.i64.ll index 5839fd2f99392..c535aad87ba7b 100644 --- a/llvm/test/CodeGen/AMDGPU/rotl.i64.ll +++ b/llvm/test/CodeGen/AMDGPU/rotl.i64.ll @@ -1,4 +1,4 @@ -; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn < %s | FileCheck -check-prefix=SI -check-prefix=BOTH %s +; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -check-prefix=SI -check-prefix=BOTH %s ; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=VI -check-prefix=BOTH %s ; BOTH-LABEL: {{^}}s_rotl_i64: diff --git a/llvm/test/CodeGen/AMDGPU/rotr.i64.ll b/llvm/test/CodeGen/AMDGPU/rotr.i64.ll index 76b57c67266f2..ab9c386e2af36 100644 --- a/llvm/test/CodeGen/AMDGPU/rotr.i64.ll +++ b/llvm/test/CodeGen/AMDGPU/rotr.i64.ll @@ -1,4 +1,4 @@ -; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn < %s | FileCheck -check-prefix=SI -check-prefix=BOTH %s +; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -check-prefix=SI -check-prefix=BOTH %s ; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=VI -check-prefix=BOTH %s ; BOTH-LABEL: {{^}}s_rotr_i64: diff --git a/llvm/test/CodeGen/AMDGPU/s_movk_i32.ll b/llvm/test/CodeGen/AMDGPU/s_movk_i32.ll index 8176e77bd8749..8cfddf6559611 100644 --- a/llvm/test/CodeGen/AMDGPU/s_movk_i32.ll +++ b/llvm/test/CodeGen/AMDGPU/s_movk_i32.ll @@ -1,4 +1,4 @@ -; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn < %s | FileCheck -check-prefix=SI %s +; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -check-prefix=SI %s ; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -check-prefix=SI %s ; SI-LABEL: {{^}}s_movk_i32_k0: diff --git a/llvm/test/CodeGen/AMDGPU/sched-crash-dbg-value.mir b/llvm/test/CodeGen/AMDGPU/sched-crash-dbg-value.mir index 89eb545cec023..64bb7093f0679 100644 --- a/llvm/test/CodeGen/AMDGPU/sched-crash-dbg-value.mir +++ b/llvm/test/CodeGen/AMDGPU/sched-crash-dbg-value.mir @@ -1,5 +1,5 @@ -# RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -run-pass=machine-scheduler -o - %s | FileCheck %s -# RUN: llc -mtriple=amdgcn-amd-amdhsa -passes=machine-scheduler -o - %s | FileCheck %s +# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -verify-machineinstrs -run-pass=machine-scheduler -o - %s | FileCheck %s +# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -passes=machine-scheduler -o - %s | FileCheck %s --- | %struct.widget.0 = type { float, i32, i32 } diff --git a/llvm/test/CodeGen/AMDGPU/sched.barrier.inverted.mask.ll b/llvm/test/CodeGen/AMDGPU/sched.barrier.inverted.mask.ll index ca802ac586668..e96485a27db33 100644 --- a/llvm/test/CodeGen/AMDGPU/sched.barrier.inverted.mask.ll +++ b/llvm/test/CodeGen/AMDGPU/sched.barrier.inverted.mask.ll @@ -1,6 +1,6 @@ ; REQUIRES: asserts -; RUN: llc -mtriple=amdgcn < %s -debug-only=igrouplp 2>&1 | FileCheck --check-prefixes=GCN %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s -debug-only=igrouplp 2>&1 | FileCheck --check-prefixes=GCN %s diff --git a/llvm/test/CodeGen/AMDGPU/schedule-global-loads.ll b/llvm/test/CodeGen/AMDGPU/schedule-global-loads.ll index e55cc7f72272f..b610a38e321b6 100644 --- a/llvm/test/CodeGen/AMDGPU/schedule-global-loads.ll +++ b/llvm/test/CodeGen/AMDGPU/schedule-global-loads.ll @@ -1,4 +1,4 @@ -; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn < %s | FileCheck -check-prefix=FUNC -check-prefix=SI %s +; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -check-prefix=FUNC -check-prefix=SI %s ; FIXME: This currently doesn't do a great job of clustering the ; loads, which end up with extra moves between them. Right now, it diff --git a/llvm/test/CodeGen/AMDGPU/schedule-regpressure.mir b/llvm/test/CodeGen/AMDGPU/schedule-regpressure.mir index 04c2092783473..0859e2fe98dc0 100644 --- a/llvm/test/CodeGen/AMDGPU/schedule-regpressure.mir +++ b/llvm/test/CodeGen/AMDGPU/schedule-regpressure.mir @@ -1,5 +1,5 @@ -# RUN: llc -mtriple=amdgcn -misched=converge -run-pass machine-scheduler %s -o - -debug-only=machine-scheduler 2>&1 | FileCheck %s -# RUN: llc -mtriple=amdgcn -misched-regpressure=false -run-pass machine-scheduler %s -o - -debug-only=machine-scheduler 2>&1 | FileCheck %s --check-prefix=NORP +# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -misched=converge -run-pass machine-scheduler %s -o - -debug-only=machine-scheduler 2>&1 | FileCheck %s +# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -misched-regpressure=false -run-pass machine-scheduler %s -o - -debug-only=machine-scheduler 2>&1 | FileCheck %s --check-prefix=NORP # REQUIRES: asserts diff --git a/llvm/test/CodeGen/AMDGPU/schedule-vs-if-nested-loop-failure.ll b/llvm/test/CodeGen/AMDGPU/schedule-vs-if-nested-loop-failure.ll index 92d31e44314ba..702fb22ad3da5 100644 --- a/llvm/test/CodeGen/AMDGPU/schedule-vs-if-nested-loop-failure.ll +++ b/llvm/test/CodeGen/AMDGPU/schedule-vs-if-nested-loop-failure.ll @@ -1,4 +1,4 @@ -; RUN: llc -O0 -mtriple=amdgcn < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -O0 -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -O0 -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=GCN %s declare void @llvm.amdgcn.s.barrier() nounwind convergent diff --git a/llvm/test/CodeGen/AMDGPU/scratch-buffer.ll b/llvm/test/CodeGen/AMDGPU/scratch-buffer.ll index d38294bfda019..65bb98e14f2da 100644 --- a/llvm/test/CodeGen/AMDGPU/scratch-buffer.ll +++ b/llvm/test/CodeGen/AMDGPU/scratch-buffer.ll @@ -1,4 +1,4 @@ -; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn < %s | FileCheck -enable-var-scope -check-prefix=GCN %s +; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -enable-var-scope -check-prefix=GCN %s ; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -enable-var-scope -check-prefix=GCN %s ; When a frame index offset is more than 12-bits, make sure we don't store diff --git a/llvm/test/CodeGen/AMDGPU/sdivrem24.ll b/llvm/test/CodeGen/AMDGPU/sdivrem24.ll index 84f67c1a6f342..fe556ddf0774f 100644 --- a/llvm/test/CodeGen/AMDGPU/sdivrem24.ll +++ b/llvm/test/CodeGen/AMDGPU/sdivrem24.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -mtriple=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s diff --git a/llvm/test/CodeGen/AMDGPU/select-opt.ll b/llvm/test/CodeGen/AMDGPU/select-opt.ll index 87fdbab45d35a..84bedb0e7158f 100644 --- a/llvm/test/CodeGen/AMDGPU/select-opt.ll +++ b/llvm/test/CodeGen/AMDGPU/select-opt.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -check-prefix=GCN %s ; Make sure to test with f32 and i32 compares. If we have to use float ; compares, we always have multiple condition registers. If we can do diff --git a/llvm/test/CodeGen/AMDGPU/selectcc-opt.ll b/llvm/test/CodeGen/AMDGPU/selectcc-opt.ll index cb768e341bd70..c0fb521dbb512 100644 --- a/llvm/test/CodeGen/AMDGPU/selectcc-opt.ll +++ b/llvm/test/CodeGen/AMDGPU/selectcc-opt.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -mtriple=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s diff --git a/llvm/test/CodeGen/AMDGPU/set-wave-priority.ll b/llvm/test/CodeGen/AMDGPU/set-wave-priority.ll index a27d1217031ca..9c817b6f009f0 100644 --- a/llvm/test/CodeGen/AMDGPU/set-wave-priority.ll +++ b/llvm/test/CodeGen/AMDGPU/set-wave-priority.ll @@ -1,9 +1,9 @@ -; RUN: llc -mtriple=amdgcn -amdgpu-set-wave-priority=true -o - %s | \ +; RUN: llc -mtriple=amdgcn -mcpu=gfx600 -amdgpu-set-wave-priority=true -o - %s | \ ; RUN: FileCheck %s -; RUN: llc -mtriple=amdgcn -stop-after=si-late-branch-lowering -o - %s | \ -; RUN: llc -x mir -mtriple=amdgcn -passes=amdgpu-set-wave-priority -o - | \ -; RUN: llc -x mir -mtriple=amdgcn -start-after=si-late-branch-lowering -o - | \ +; RUN: llc -mtriple=amdgcn -mcpu=gfx600 -stop-after=si-late-branch-lowering -o - %s | \ +; RUN: llc -x mir -mtriple=amdgcn -mcpu=gfx600 -passes=amdgpu-set-wave-priority -o - | \ +; RUN: llc -x mir -mtriple=amdgcn -mcpu=gfx600 -start-after=si-late-branch-lowering -o - | \ ; RUN: FileCheck %s ; CHECK-LABEL: no_setprio: diff --git a/llvm/test/CodeGen/AMDGPU/setcc-opt.ll b/llvm/test/CodeGen/AMDGPU/setcc-opt.ll index 031a55a2dc758..1ff095886f42b 100644 --- a/llvm/test/CodeGen/AMDGPU/setcc-opt.ll +++ b/llvm/test/CodeGen/AMDGPU/setcc-opt.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=FUNC %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=FUNC %s ; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -check-prefix=VI -check-prefix=GCN -check-prefix=FUNC %s ; RUN: llc -mtriple=r600 -mcpu=cypress < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s diff --git a/llvm/test/CodeGen/AMDGPU/setcc-sext.ll b/llvm/test/CodeGen/AMDGPU/setcc-sext.ll index 83c39575f50b0..bc3730e4be872 100644 --- a/llvm/test/CodeGen/AMDGPU/setcc-sext.ll +++ b/llvm/test/CodeGen/AMDGPU/setcc-sext.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -check-prefix=GCN %s ; GCN-LABEL: {{^}}setcc_sgt_true_sext: ; GCN: v_cmp_le_u32_e{{32|64}} [[CC:[^,]+]], v{{[0-9]+}}, v{{[0-9]+}} diff --git a/llvm/test/CodeGen/AMDGPU/setcc64.ll b/llvm/test/CodeGen/AMDGPU/setcc64.ll index b36ed3e91c573..c0ecd1827bc73 100644 --- a/llvm/test/CodeGen/AMDGPU/setcc64.ll +++ b/llvm/test/CodeGen/AMDGPU/setcc64.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn < %s| FileCheck -check-prefixes=GCN,SI %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s| FileCheck -check-prefixes=GCN,SI %s ; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -check-prefixes=GCN,VI %s ; XXX: Merge this into setcc, once R600 supports 64-bit operations diff --git a/llvm/test/CodeGen/AMDGPU/sext-in-reg.ll b/llvm/test/CodeGen/AMDGPU/sext-in-reg.ll index 65fa2ca4dbe9c..71a43de93bb11 100644 --- a/llvm/test/CodeGen/AMDGPU/sext-in-reg.ll +++ b/llvm/test/CodeGen/AMDGPU/sext-in-reg.ll @@ -1,4 +1,4 @@ -; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn-- < %s | FileCheck -enable-var-scope --check-prefixes=GCN,SI,FUNC %s +; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn-- -mcpu=gfx600 < %s | FileCheck -enable-var-scope --check-prefixes=GCN,SI,FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn-- -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -enable-var-scope --check-prefixes=GCN,GFX89,FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn-- -mcpu=gfx900 -mattr=-flat-for-global < %s | FileCheck -enable-var-scope --check-prefixes=GCN,GFX9,GFX89,FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=r600-- -mcpu=cypress < %s | FileCheck -enable-var-scope --check-prefixes=EG,FUNC %s diff --git a/llvm/test/CodeGen/AMDGPU/sgpr-copy-duplicate-operand.ll b/llvm/test/CodeGen/AMDGPU/sgpr-copy-duplicate-operand.ll index 63fd450810d56..1fc125866df65 100644 --- a/llvm/test/CodeGen/AMDGPU/sgpr-copy-duplicate-operand.ll +++ b/llvm/test/CodeGen/AMDGPU/sgpr-copy-duplicate-operand.ll @@ -1,4 +1,4 @@ -; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn < %s | FileCheck -check-prefix=SI %s +; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -check-prefix=SI %s ; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=SI %s ; Copy VGPR -> SGPR used twice as an instruction operand, which is then diff --git a/llvm/test/CodeGen/AMDGPU/sgpr-spill-wrong-stack-id.mir b/llvm/test/CodeGen/AMDGPU/sgpr-spill-wrong-stack-id.mir index 6202535561d46..884125772b955 100644 --- a/llvm/test/CodeGen/AMDGPU/sgpr-spill-wrong-stack-id.mir +++ b/llvm/test/CodeGen/AMDGPU/sgpr-spill-wrong-stack-id.mir @@ -1,5 +1,5 @@ -# RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -stress-regalloc=3 -run-pass=greedy,virtregrewriter,stack-slot-coloring -o - %s | FileCheck -check-prefixes=SHARE,GCN %s -# RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -stress-regalloc=3 -run-pass=greedy,virtregrewriter,stack-slot-coloring -no-stack-slot-sharing -o - %s | FileCheck -check-prefixes=NOSHARE,GCN %s +# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -verify-machineinstrs -stress-regalloc=3 -run-pass=greedy,virtregrewriter,stack-slot-coloring -o - %s | FileCheck -check-prefixes=SHARE,GCN %s +# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -verify-machineinstrs -stress-regalloc=3 -run-pass=greedy,virtregrewriter,stack-slot-coloring -no-stack-slot-sharing -o - %s | FileCheck -check-prefixes=NOSHARE,GCN %s # -run-pass is used to artifically avoid using split register allocation, which would avoid stressing StackSlotColoring. diff --git a/llvm/test/CodeGen/AMDGPU/sgprcopies.ll b/llvm/test/CodeGen/AMDGPU/sgprcopies.ll index c2ea52684b7f7..1a349c8d99c82 100644 --- a/llvm/test/CodeGen/AMDGPU/sgprcopies.ll +++ b/llvm/test/CodeGen/AMDGPU/sgprcopies.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=amdgcn | FileCheck -check-prefix=GCN %s +; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx600 | FileCheck -check-prefix=GCN %s ; GCN-LABEL: {{^}}checkTwoBlocksWithUniformBranch ; GCN: BB0_2 diff --git a/llvm/test/CodeGen/AMDGPU/shrink-vop3-carry-out.mir b/llvm/test/CodeGen/AMDGPU/shrink-vop3-carry-out.mir index 9c74d94a1afef..c474ec53fc65c 100644 --- a/llvm/test/CodeGen/AMDGPU/shrink-vop3-carry-out.mir +++ b/llvm/test/CodeGen/AMDGPU/shrink-vop3-carry-out.mir @@ -1,5 +1,5 @@ -# RUN: llc -verify-machineinstrs -mtriple=amdgcn -run-pass si-shrink-instructions -o - %s | FileCheck -check-prefix=GCN %s -# RUN: llc -verify-machineinstrs -mtriple=amdgcn -passes si-shrink-instructions -o - %s | FileCheck -check-prefix=GCN %s +# RUN: llc -verify-machineinstrs -mtriple=amdgcn -mcpu=gfx600 -run-pass si-shrink-instructions -o - %s | FileCheck -check-prefix=GCN %s +# RUN: llc -verify-machineinstrs -mtriple=amdgcn -mcpu=gfx600 -passes si-shrink-instructions -o - %s | FileCheck -check-prefix=GCN %s # Check that add with carry out isn't incorrectly reduced to e32 when # the carry out is a virtual register. diff --git a/llvm/test/CodeGen/AMDGPU/si-annotate-cf-noloop.ll b/llvm/test/CodeGen/AMDGPU/si-annotate-cf-noloop.ll index 4a863cf77ebba..e7fb6d773248b 100644 --- a/llvm/test/CodeGen/AMDGPU/si-annotate-cf-noloop.ll +++ b/llvm/test/CodeGen/AMDGPU/si-annotate-cf-noloop.ll @@ -1,6 +1,6 @@ ; RUN: opt -mtriple=amdgcn-- -S -structurizecfg -si-annotate-control-flow -simplifycfg-require-and-preserve-domtree=1 %s | FileCheck -check-prefix=OPT %s ; RUN: opt -mtriple=amdgcn-- -S -passes=structurizecfg,si-annotate-control-flow -simplifycfg-require-and-preserve-domtree=1 %s | FileCheck -check-prefix=OPT %s -; RUN: llc -mtriple=amdgcn -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx600 -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -check-prefix=GCN %s ; OPT-LABEL: @annotate_unreachable_noloop( ; OPT-NOT: call i1 @llvm.amdgcn.loop diff --git a/llvm/test/CodeGen/AMDGPU/si-annotate-cf-unreachable.ll b/llvm/test/CodeGen/AMDGPU/si-annotate-cf-unreachable.ll index 707c30807d5ec..1bbb8f0e28973 100644 --- a/llvm/test/CodeGen/AMDGPU/si-annotate-cf-unreachable.ll +++ b/llvm/test/CodeGen/AMDGPU/si-annotate-cf-unreachable.ll @@ -1,6 +1,6 @@ ; RUN: opt -mtriple=amdgcn-- -S -structurizecfg -si-annotate-control-flow %s | FileCheck -check-prefix=OPT %s ; RUN: opt -mtriple=amdgcn-- -S -passes=structurizecfg,si-annotate-control-flow %s | FileCheck -check-prefix=OPT %s -; RUN: llc -mtriple=amdgcn < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -check-prefix=GCN %s ; OPT-LABEL: @annotate_unreachable( diff --git a/llvm/test/CodeGen/AMDGPU/si-fix-sgpr-copies.mir b/llvm/test/CodeGen/AMDGPU/si-fix-sgpr-copies.mir index 9b9601e1e3962..bad989832b4f0 100644 --- a/llvm/test/CodeGen/AMDGPU/si-fix-sgpr-copies.mir +++ b/llvm/test/CodeGen/AMDGPU/si-fix-sgpr-copies.mir @@ -1,5 +1,5 @@ -# RUN: llc -mtriple=amdgcn -run-pass si-fix-sgpr-copies %s -o - | FileCheck %s -check-prefixes=GCN -# RUN: llc -mtriple=amdgcn -passes=si-fix-sgpr-copies %s -o - | FileCheck %s -check-prefixes=GCN +# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -run-pass si-fix-sgpr-copies %s -o - | FileCheck %s -check-prefixes=GCN +# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -passes=si-fix-sgpr-copies %s -o - | FileCheck %s -check-prefixes=GCN --- diff --git a/llvm/test/CodeGen/AMDGPU/si-lower-control-flow-kill.ll b/llvm/test/CodeGen/AMDGPU/si-lower-control-flow-kill.ll index 44dcbc5e803e1..86212508882ee 100644 --- a/llvm/test/CodeGen/AMDGPU/si-lower-control-flow-kill.ll +++ b/llvm/test/CodeGen/AMDGPU/si-lower-control-flow-kill.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -check-prefix=GCN %s ; GCN-LABEL: {{^}}if_with_kill: ; GCN: s_and_saveexec_b64 [[SAVEEXEC:s\[[0-9:]+\]]], diff --git a/llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills.mir b/llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills.mir index 2f769d94f174d..d30d83009d267 100644 --- a/llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills.mir +++ b/llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills.mir @@ -1,4 +1,4 @@ -# RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -run-pass=si-lower-sgpr-spills -o - %s | FileCheck %s +# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -verify-machineinstrs -run-pass=si-lower-sgpr-spills -o - %s | FileCheck %s # CHECK-LABEL: name: empty_entry_block # CHECK: SI_SPILL_S32_TO_VGPR diff --git a/llvm/test/CodeGen/AMDGPU/si-spill-cf.ll b/llvm/test/CodeGen/AMDGPU/si-spill-cf.ll index 931f00ec04ad8..25faee2a9b274 100644 --- a/llvm/test/CodeGen/AMDGPU/si-spill-cf.ll +++ b/llvm/test/CodeGen/AMDGPU/si-spill-cf.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn < %s | FileCheck -check-prefix=SI %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -check-prefix=SI %s ; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=SI %s ; If this occurs it is likely due to reordering and the restore was diff --git a/llvm/test/CodeGen/AMDGPU/sint_to_fp.ll b/llvm/test/CodeGen/AMDGPU/sint_to_fp.ll index 6d4f1b22eb086..c6509aae5b938 100644 --- a/llvm/test/CodeGen/AMDGPU/sint_to_fp.ll +++ b/llvm/test/CodeGen/AMDGPU/sint_to_fp.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -mtriple=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s diff --git a/llvm/test/CodeGen/AMDGPU/skip-branch-trap.ll b/llvm/test/CodeGen/AMDGPU/skip-branch-trap.ll index e3b8379015178..17ac0a826ceba 100644 --- a/llvm/test/CodeGen/AMDGPU/skip-branch-trap.ll +++ b/llvm/test/CodeGen/AMDGPU/skip-branch-trap.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn--amdhsa < %s | FileCheck -enable-var-scope -check-prefix=GCN %s +; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx700 < %s | FileCheck -enable-var-scope -check-prefix=GCN %s ; FIXME: merge with trap.ll diff --git a/llvm/test/CodeGen/AMDGPU/smed3.ll b/llvm/test/CodeGen/AMDGPU/smed3.ll index a9fb77904c641..e50d9673eb823 100644 --- a/llvm/test/CodeGen/AMDGPU/smed3.ll +++ b/llvm/test/CodeGen/AMDGPU/smed3.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s ; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -mattr=-flat-for-global < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 %s ; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-flat-for-global,-real-true16 < %s | FileCheck -check-prefixes=GFX11-FAKE16 %s diff --git a/llvm/test/CodeGen/AMDGPU/spill-before-exec.mir b/llvm/test/CodeGen/AMDGPU/spill-before-exec.mir index 81f72b70d1ecb..d500bba7119bf 100644 --- a/llvm/test/CodeGen/AMDGPU/spill-before-exec.mir +++ b/llvm/test/CodeGen/AMDGPU/spill-before-exec.mir @@ -1,5 +1,5 @@ # REQUIRES: asserts -# RUN: llc -mtriple=amdgcn-- -verify-machineinstrs -debug-only=regalloc -run-pass=greedy -filetype=null %s 2>&1 | FileCheck %s +# RUN: llc -mtriple=amdgcn-- -mcpu=gfx600 -verify-machineinstrs -debug-only=regalloc -run-pass=greedy -filetype=null %s 2>&1 | FileCheck %s --- # Check that physreg candidate is not used since cannot be spilled in a block, diff --git a/llvm/test/CodeGen/AMDGPU/spill-csr-frame-ptr-reg-copy.ll b/llvm/test/CodeGen/AMDGPU/spill-csr-frame-ptr-reg-copy.ll index 83bf3a7e4a951..95ed6456cd52b 100644 --- a/llvm/test/CodeGen/AMDGPU/spill-csr-frame-ptr-reg-copy.ll +++ b/llvm/test/CodeGen/AMDGPU/spill-csr-frame-ptr-reg-copy.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn-amd-amdhsa -stress-regalloc=1 < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -stress-regalloc=1 < %s | FileCheck -check-prefix=GCN %s ; GCN-LABEL: {{^}}spill_csr_s5_copy: ; GCN: s_mov_b32 [[FP_SCRATCH_COPY:s[0-9]+]], s33 diff --git a/llvm/test/CodeGen/AMDGPU/spill-m0.ll b/llvm/test/CodeGen/AMDGPU/spill-m0.ll index c53820e43f5a5..8ed5310f4ac94 100644 --- a/llvm/test/CodeGen/AMDGPU/spill-m0.ll +++ b/llvm/test/CodeGen/AMDGPU/spill-m0.ll @@ -1,4 +1,4 @@ -; RUN: llc -O0 -amdgpu-spill-sgpr-to-vgpr=1 -mtriple=amdgcn < %s | FileCheck -enable-var-scope -check-prefix=TOVGPR -check-prefix=GCN %s +; RUN: llc -O0 -amdgpu-spill-sgpr-to-vgpr=1 -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -enable-var-scope -check-prefix=TOVGPR -check-prefix=GCN %s ; RUN: llc -O0 -amdgpu-spill-sgpr-to-vgpr=1 -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -enable-var-scope -check-prefix=TOVGPR -check-prefix=GCN %s ; RUN: llc -O0 -amdgpu-spill-sgpr-to-vgpr=0 -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -enable-var-scope -check-prefix=TOVMEM -check-prefix=GCN %s ; RUN: llc -O0 -amdgpu-spill-sgpr-to-vgpr=0 -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -enable-var-scope -check-prefix=TOVMEM -check-prefix=GCN %s diff --git a/llvm/test/CodeGen/AMDGPU/split-scalar-i64-add.ll b/llvm/test/CodeGen/AMDGPU/split-scalar-i64-add.ll index dbecdb22042b9..b65ac0557217c 100644 --- a/llvm/test/CodeGen/AMDGPU/split-scalar-i64-add.ll +++ b/llvm/test/CodeGen/AMDGPU/split-scalar-i64-add.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s declare i32 @llvm.amdgcn.workitem.id.x() readnone diff --git a/llvm/test/CodeGen/AMDGPU/stack-size-overflow.ll b/llvm/test/CodeGen/AMDGPU/stack-size-overflow.ll index e378a83cff50d..266f08273e891 100644 --- a/llvm/test/CodeGen/AMDGPU/stack-size-overflow.ll +++ b/llvm/test/CodeGen/AMDGPU/stack-size-overflow.ll @@ -1,5 +1,5 @@ -; RUN: not llc -mtriple=amdgcn-- < %s 2>&1 | FileCheck -check-prefix=ERROR %s -; RUN: not llc -mtriple=amdgcn-- < %s | FileCheck -check-prefix=GCN %s +; RUN: not llc -mtriple=amdgcn-- -mcpu=gfx600 < %s 2>&1 | FileCheck -check-prefix=ERROR %s +; RUN: not llc -mtriple=amdgcn-- -mcpu=gfx600 < %s | FileCheck -check-prefix=GCN %s declare void @llvm.memset.p5.i32(ptr addrspace(5) nocapture, i8, i32, i32, i1) #1 diff --git a/llvm/test/CodeGen/AMDGPU/store-barrier.ll b/llvm/test/CodeGen/AMDGPU/store-barrier.ll index 163821f762308..5d77c7f938eb5 100644 --- a/llvm/test/CodeGen/AMDGPU/store-barrier.ll +++ b/llvm/test/CodeGen/AMDGPU/store-barrier.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn -mattr=+load-store-opt -enable-misched < %s | FileCheck %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx600 -mattr=+load-store-opt -enable-misched < %s | FileCheck %s ; RUN: llc -mtriple=amdgcn -mcpu=bonaire -mattr=+load-store-opt -enable-misched < %s | FileCheck %s ; This test is for a bug in the machine scheduler where stores without diff --git a/llvm/test/CodeGen/AMDGPU/store-v3i64.ll b/llvm/test/CodeGen/AMDGPU/store-v3i64.ll index 922ef848694d5..e933c8b888bcc 100644 --- a/llvm/test/CodeGen/AMDGPU/store-v3i64.ll +++ b/llvm/test/CodeGen/AMDGPU/store-v3i64.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=GCN -check-prefix=SI %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=GCN -check-prefix=SI %s ; RUN: llc -mtriple=amdgcn -mcpu=bonaire < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=GCN -check-prefix=CI %s ; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=GCN -check-prefix=VI %s diff --git a/llvm/test/CodeGen/AMDGPU/subreg-intervals.mir b/llvm/test/CodeGen/AMDGPU/subreg-intervals.mir index 09496ee323377..2d234b76689f9 100644 --- a/llvm/test/CodeGen/AMDGPU/subreg-intervals.mir +++ b/llvm/test/CodeGen/AMDGPU/subreg-intervals.mir @@ -1,5 +1,5 @@ -# RUN: llc -mtriple=amdgcn -run-pass liveintervals -debug-only=regalloc -verify-machineinstrs -filetype=null %s 2>&1 | FileCheck %s -# RUN: llc -mtriple=amdgcn --passes='print<live-intervals>' -debug-only=regalloc -filetype=null %s 2>&1 | FileCheck %s +# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -run-pass liveintervals -debug-only=regalloc -verify-machineinstrs -filetype=null %s 2>&1 | FileCheck %s +# RUN: llc -mtriple=amdgcn -mcpu=gfx600 --passes='print<live-intervals>' -debug-only=regalloc -filetype=null %s 2>&1 | FileCheck %s # REQUIRES: asserts # CHECK: INTERVALS diff --git a/llvm/test/CodeGen/AMDGPU/subreg_interference.mir b/llvm/test/CodeGen/AMDGPU/subreg_interference.mir index 77f1fc5c54734..207b848ea427f 100644 --- a/llvm/test/CodeGen/AMDGPU/subreg_interference.mir +++ b/llvm/test/CodeGen/AMDGPU/subreg_interference.mir @@ -1,4 +1,4 @@ -# RUN: llc -o - %s -mtriple=amdgcn--amdhsa -verify-machineinstrs -run-pass=greedy,virtregrewriter | FileCheck %s +# RUN: llc -o - %s -mtriple=amdgcn--amdhsa -mcpu=gfx700 -verify-machineinstrs -run-pass=greedy,virtregrewriter | FileCheck %s --- | define amdgpu_kernel void @func0() { diff --git a/llvm/test/CodeGen/AMDGPU/target-cpu.ll b/llvm/test/CodeGen/AMDGPU/target-cpu.ll index 660ea558f00a5..710bc25678acf 100644 --- a/llvm/test/CodeGen/AMDGPU/target-cpu.ll +++ b/llvm/test/CodeGen/AMDGPU/target-cpu.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn -disable-promote-alloca-to-vector < %s | FileCheck %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx600 -disable-promote-alloca-to-vector < %s | FileCheck %s declare ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr() #1 diff --git a/llvm/test/CodeGen/AMDGPU/trap.ll b/llvm/test/CodeGen/AMDGPU/trap.ll index abc108958d4af..ca27a389cdb5f 100644 --- a/llvm/test/CodeGen/AMDGPU/trap.ll +++ b/llvm/test/CodeGen/AMDGPU/trap.ll @@ -1,27 +1,27 @@ -; RUN: llc -global-isel=0 -mtriple=amdgcn--amdhsa < %s | FileCheck -check-prefix=GCN -check-prefix=HSA-TRAP %s -; RUN: llc -global-isel=1 -mtriple=amdgcn--amdhsa < %s | FileCheck -check-prefix=GCN -check-prefix=HSA-TRAP %s +; RUN: llc -global-isel=0 -mtriple=amdgcn--amdhsa -mcpu=gfx700 < %s | FileCheck -check-prefix=GCN -check-prefix=HSA-TRAP %s +; RUN: llc -global-isel=1 -mtriple=amdgcn--amdhsa -mcpu=gfx700 < %s | FileCheck -check-prefix=GCN -check-prefix=HSA-TRAP %s -; RUN: llc -global-isel=0 -mtriple=amdgcn--amdhsa -mattr=+trap-handler < %s | FileCheck -check-prefix=GCN -check-prefix=HSA-TRAP %s -; RUN: llc -global-isel=1 -mtriple=amdgcn--amdhsa -mattr=+trap-handler < %s | FileCheck -check-prefix=GCN -check-prefix=HSA-TRAP %s -; RUN: llc -global-isel=0 -mtriple=amdgcn--amdhsa -mattr=-trap-handler < %s | FileCheck -check-prefix=GCN -check-prefix=NO-HSA-TRAP %s -; RUN: llc -global-isel=1 -mtriple=amdgcn--amdhsa -mattr=-trap-handler < %s | FileCheck -check-prefix=GCN -check-prefix=NO-HSA-TRAP %s -; RUN: llc -global-isel=0 -mtriple=amdgcn--amdhsa -mattr=-trap-handler < %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=GCN-WARNING %s -; RUN: llc -global-isel=1 -mtriple=amdgcn--amdhsa -mattr=-trap-handler < %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=GCN-WARNING %s +; RUN: llc -global-isel=0 -mtriple=amdgcn--amdhsa -mcpu=gfx700 -mattr=+trap-handler < %s | FileCheck -check-prefix=GCN -check-prefix=HSA-TRAP %s +; RUN: llc -global-isel=1 -mtriple=amdgcn--amdhsa -mcpu=gfx700 -mattr=+trap-handler < %s | FileCheck -check-prefix=GCN -check-prefix=HSA-TRAP %s +; RUN: llc -global-isel=0 -mtriple=amdgcn--amdhsa -mcpu=gfx700 -mattr=-trap-handler < %s | FileCheck -check-prefix=GCN -check-prefix=NO-HSA-TRAP %s +; RUN: llc -global-isel=1 -mtriple=amdgcn--amdhsa -mcpu=gfx700 -mattr=-trap-handler < %s | FileCheck -check-prefix=GCN -check-prefix=NO-HSA-TRAP %s +; RUN: llc -global-isel=0 -mtriple=amdgcn--amdhsa -mcpu=gfx700 -mattr=-trap-handler < %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=GCN-WARNING %s +; RUN: llc -global-isel=1 -mtriple=amdgcn--amdhsa -mcpu=gfx700 -mattr=-trap-handler < %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=GCN-WARNING %s ; enable trap handler feature -; RUN: llc -global-isel=0 -mtriple=amdgcn-unknown-mesa3d -mattr=+trap-handler < %s | FileCheck -check-prefix=GCN -check-prefix=NO-MESA-TRAP -check-prefix=TRAP-BIT -check-prefix=MESA-TRAP %s -; RUN: llc -global-isel=1 -mtriple=amdgcn-unknown-mesa3d -mattr=+trap-handler < %s | FileCheck -check-prefix=GCN -check-prefix=NO-MESA-TRAP -check-prefix=TRAP-BIT -check-prefix=MESA-TRAP %s -; RUN: llc -global-isel=0 -mtriple=amdgcn-unknown-mesa3d -mattr=+trap-handler < %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=GCN-WARNING -check-prefix=TRAP-BIT %s -; RUN: llc -global-isel=1 -mtriple=amdgcn-unknown-mesa3d -mattr=+trap-handler < %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=GCN-WARNING -check-prefix=TRAP-BIT %s +; RUN: llc -global-isel=0 -mtriple=amdgcn-unknown-mesa3d -mcpu=gfx600 -mattr=+trap-handler < %s | FileCheck -check-prefix=GCN -check-prefix=NO-MESA-TRAP -check-prefix=TRAP-BIT -check-prefix=MESA-TRAP %s +; RUN: llc -global-isel=1 -mtriple=amdgcn-unknown-mesa3d -mcpu=gfx600 -mattr=+trap-handler < %s | FileCheck -check-prefix=GCN -check-prefix=NO-MESA-TRAP -check-prefix=TRAP-BIT -check-prefix=MESA-TRAP %s +; RUN: llc -global-isel=0 -mtriple=amdgcn-unknown-mesa3d -mcpu=gfx600 -mattr=+trap-handler < %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=GCN-WARNING -check-prefix=TRAP-BIT %s +; RUN: llc -global-isel=1 -mtriple=amdgcn-unknown-mesa3d -mcpu=gfx600 -mattr=+trap-handler < %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=GCN-WARNING -check-prefix=TRAP-BIT %s ; disable trap handler feature -; RUN: llc -global-isel=0 -mtriple=amdgcn-unknown-mesa3d -mattr=-trap-handler < %s | FileCheck -check-prefix=GCN -check-prefix=NO-MESA-TRAP -check-prefix=NO-TRAP-BIT -check-prefix=NOMESA-TRAP %s -; RUN: llc -global-isel=1 -mtriple=amdgcn-unknown-mesa3d -mattr=-trap-handler < %s | FileCheck -check-prefix=GCN -check-prefix=NO-MESA-TRAP -check-prefix=NO-TRAP-BIT -check-prefix=NOMESA-TRAP %s -; RUN: llc -global-isel=0 -mtriple=amdgcn-unknown-mesa3d -mattr=-trap-handler < %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=GCN-WARNING -check-prefix=NO-TRAP-BIT %s -; RUN: llc -global-isel=1 -mtriple=amdgcn-unknown-mesa3d -mattr=-trap-handler < %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=GCN-WARNING -check-prefix=NO-TRAP-BIT %s +; RUN: llc -global-isel=0 -mtriple=amdgcn-unknown-mesa3d -mcpu=gfx600 -mattr=-trap-handler < %s | FileCheck -check-prefix=GCN -check-prefix=NO-MESA-TRAP -check-prefix=NO-TRAP-BIT -check-prefix=NOMESA-TRAP %s +; RUN: llc -global-isel=1 -mtriple=amdgcn-unknown-mesa3d -mcpu=gfx600 -mattr=-trap-handler < %s | FileCheck -check-prefix=GCN -check-prefix=NO-MESA-TRAP -check-prefix=NO-TRAP-BIT -check-prefix=NOMESA-TRAP %s +; RUN: llc -global-isel=0 -mtriple=amdgcn-unknown-mesa3d -mcpu=gfx600 -mattr=-trap-handler < %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=GCN-WARNING -check-prefix=NO-TRAP-BIT %s +; RUN: llc -global-isel=1 -mtriple=amdgcn-unknown-mesa3d -mcpu=gfx600 -mattr=-trap-handler < %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=GCN-WARNING -check-prefix=NO-TRAP-BIT %s -; RUN: llc -global-isel=0 -mtriple=amdgcn < %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=GCN-WARNING %s -; RUN: llc -global-isel=1 -mtriple=amdgcn < %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=GCN-WARNING %s +; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx600 < %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=GCN-WARNING %s +; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx600 < %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=GCN-WARNING %s ; GCN-WARNING: warning: <unknown>:0:0: in function hsa_debugtrap void (ptr addrspace(1)): debugtrap handler not supported diff --git a/llvm/test/CodeGen/AMDGPU/trunc-store-f64-to-f16.ll b/llvm/test/CodeGen/AMDGPU/trunc-store-f64-to-f16.ll index 77d9d678b03af..f157ec7be4e1b 100644 --- a/llvm/test/CodeGen/AMDGPU/trunc-store-f64-to-f16.ll +++ b/llvm/test/CodeGen/AMDGPU/trunc-store-f64-to-f16.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -check-prefix=GCN %s ; GCN-LABEL: {{^}}global_truncstore_f64_to_f16: ; GCN: s_endpgm diff --git a/llvm/test/CodeGen/AMDGPU/trunc-store-i1.ll b/llvm/test/CodeGen/AMDGPU/trunc-store-i1.ll index ecc1defe6acac..0a2a3e70008a3 100644 --- a/llvm/test/CodeGen/AMDGPU/trunc-store-i1.ll +++ b/llvm/test/CodeGen/AMDGPU/trunc-store-i1.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn < %s | FileCheck -enable-var-scope --check-prefix=GCN %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -enable-var-scope --check-prefix=GCN %s ; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -enable-var-scope --check-prefix=GCN %s diff --git a/llvm/test/CodeGen/AMDGPU/twoaddr-regsequence-keep-copy-on-use.mir b/llvm/test/CodeGen/AMDGPU/twoaddr-regsequence-keep-copy-on-use.mir index f28310536bd49..d575be5cfd82c 100644 --- a/llvm/test/CodeGen/AMDGPU/twoaddr-regsequence-keep-copy-on-use.mir +++ b/llvm/test/CodeGen/AMDGPU/twoaddr-regsequence-keep-copy-on-use.mir @@ -1,5 +1,5 @@ -# RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -run-pass=twoaddressinstruction -o - %s | FileCheck -check-prefix=CHECK %s -# RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -run-pass=liveintervals,twoaddressinstruction -o - %s | FileCheck -check-prefix=LIS %s +# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -verify-machineinstrs -run-pass=twoaddressinstruction -o - %s | FileCheck -check-prefix=CHECK %s +# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -verify-machineinstrs -run-pass=liveintervals,twoaddressinstruction -o - %s | FileCheck -check-prefix=LIS %s # Checks that while lowering REG_SEQUENCE, undef COPY are not skipped if there is no LIS # information diff --git a/llvm/test/CodeGen/AMDGPU/uint_to_fp.ll b/llvm/test/CodeGen/AMDGPU/uint_to_fp.ll index 4603efb7f7fd6..6d44365ea3706 100644 --- a/llvm/test/CodeGen/AMDGPU/uint_to_fp.ll +++ b/llvm/test/CodeGen/AMDGPU/uint_to_fp.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=SI -check-prefix=FUNC %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -mtriple=r600 -mcpu=redwood < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=R600 -check-prefix=FUNC %s diff --git a/llvm/test/CodeGen/AMDGPU/umed3.ll b/llvm/test/CodeGen/AMDGPU/umed3.ll index 9d8a45ada87aa..207ae5a75c0bf 100644 --- a/llvm/test/CodeGen/AMDGPU/umed3.ll +++ b/llvm/test/CodeGen/AMDGPU/umed3.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s ; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -mattr=-flat-for-global < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 %s ; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-flat-for-global,-real-true16 < %s | FileCheck -check-prefix=GFX11-FAKE16 %s diff --git a/llvm/test/CodeGen/AMDGPU/unaligned-load-store.ll b/llvm/test/CodeGen/AMDGPU/unaligned-load-store.ll index 15065ebdc44d5..305eedfd83d25 100644 --- a/llvm/test/CodeGen/AMDGPU/unaligned-load-store.ll +++ b/llvm/test/CodeGen/AMDGPU/unaligned-load-store.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn < %s | FileCheck -check-prefixes=SI,MUBUF,ALIGNED %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -check-prefixes=SI,MUBUF,ALIGNED %s ; RUN: llc -mtriple=amdgcn -mcpu=bonaire -mattr=+unaligned-access-mode < %s | FileCheck -check-prefixes=SI,MUBUF,UNALIGNED %s ; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -check-prefixes=SI,MUBUF,ALIGNED %s ; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -mattr=-flat-for-global -mattr=+enable-flat-scratch < %s | FileCheck -check-prefixes=SI,FLATSCR,ALIGNED %s diff --git a/llvm/test/CodeGen/AMDGPU/undef-build-vector.ll b/llvm/test/CodeGen/AMDGPU/undef-build-vector.ll index 1d00ee956e3a2..81c9aa84482d2 100644 --- a/llvm/test/CodeGen/AMDGPU/undef-build-vector.ll +++ b/llvm/test/CodeGen/AMDGPU/undef-build-vector.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn < %s | FileCheck %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck %s ; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck %s ; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck %s diff --git a/llvm/test/CodeGen/AMDGPU/unhandled-loop-condition-assertion.ll b/llvm/test/CodeGen/AMDGPU/unhandled-loop-condition-assertion.ll index 1813acfb21a72..88f0a2d2965dd 100644 --- a/llvm/test/CodeGen/AMDGPU/unhandled-loop-condition-assertion.ll +++ b/llvm/test/CodeGen/AMDGPU/unhandled-loop-condition-assertion.ll @@ -1,4 +1,4 @@ -; RUN: llc -O0 -asm-verbose=0 -mtriple=amdgcn < %s | FileCheck -check-prefix=SI -check-prefix=COMMON %s +; RUN: llc -O0 -asm-verbose=0 -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -check-prefix=SI -check-prefix=COMMON %s ; RUN: llc -O0 -asm-verbose=0 -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=SI -check-prefix=COMMON %s ; XUN: llc -O0 -asm-verbose=0 -mtriple=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=COMMON %s diff --git a/llvm/test/CodeGen/AMDGPU/unigine-liveness-crash.ll b/llvm/test/CodeGen/AMDGPU/unigine-liveness-crash.ll index fd7e9f0ad660a..cebb8477a98d0 100644 --- a/llvm/test/CodeGen/AMDGPU/unigine-liveness-crash.ll +++ b/llvm/test/CodeGen/AMDGPU/unigine-liveness-crash.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx600 -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck %s ; ; This test used to crash with the following assertion: ; llc: include/llvm/ADT/IntervalMap.h:632: unsigned int llvm::IntervalMapImpl::LeafNode<llvm::SlotIndex, llvm::LiveInterval *, 8, llvm::IntervalMapInfo<llvm::SlotIndex> >::insertFrom(unsigned int &, unsigned int, KeyT, KeyT, ValT) [KeyT = llvm::SlotIndex, ValT = llvm::LiveInterval *, N = 8, Traits = llvm::IntervalMapInfo<llvm::SlotIndex>]: Assertion `(i == Size || Traits::stopLess(b, start(i))) && "Overlapping insert"' failed. diff --git a/llvm/test/CodeGen/AMDGPU/unsupported-calls.ll b/llvm/test/CodeGen/AMDGPU/unsupported-calls.ll index 721114ece56d1..675f279c367a2 100644 --- a/llvm/test/CodeGen/AMDGPU/unsupported-calls.ll +++ b/llvm/test/CodeGen/AMDGPU/unsupported-calls.ll @@ -1,5 +1,5 @@ -; RUN: not llc -mtriple=amdgcn-mesa-mesa3d -tailcallopt < %s 2>&1 | FileCheck --check-prefix=GCN %s -; RUN: not llc -mtriple=amdgcn--amdpal -tailcallopt < %s 2>&1 | FileCheck --check-prefix=GCN %s +; RUN: not llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx600 -tailcallopt < %s 2>&1 | FileCheck --check-prefix=GCN %s +; RUN: not llc -mtriple=amdgcn--amdpal -mcpu=gfx600 -tailcallopt < %s 2>&1 | FileCheck --check-prefix=GCN %s ; RUN: not llc -mtriple=r600-- -mcpu=cypress -tailcallopt < %s 2>&1 | FileCheck -check-prefix=R600 %s declare i32 @external_function(i32) nounwind diff --git a/llvm/test/CodeGen/AMDGPU/v_cvt_pk_u8_f32.ll b/llvm/test/CodeGen/AMDGPU/v_cvt_pk_u8_f32.ll index 8179c0f6e42cb..7a763cb43f402 100644 --- a/llvm/test/CodeGen/AMDGPU/v_cvt_pk_u8_f32.ll +++ b/llvm/test/CodeGen/AMDGPU/v_cvt_pk_u8_f32.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -mtriple=amdgcn -mcpu=fiji < %s | FileCheck -check-prefix=GCN %s declare i32 @llvm.amdgcn.cvt.pk.u8.f32(float, i32, i32) #0 diff --git a/llvm/test/CodeGen/AMDGPU/v_mac.ll b/llvm/test/CodeGen/AMDGPU/v_mac.ll index 4658332ac395d..8b952c196b144 100644 --- a/llvm/test/CodeGen/AMDGPU/v_mac.ll +++ b/llvm/test/CodeGen/AMDGPU/v_mac.ll @@ -1,4 +1,4 @@ -; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mattr=+mad-mac-f32-insts -denormal-fp-math-f32=preserve-sign < %s | FileCheck --check-prefixes=SI,GCN %s +; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx600 -mattr=+mad-mac-f32-insts -denormal-fp-math-f32=preserve-sign < %s | FileCheck --check-prefixes=SI,GCN %s ; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=tonga -denormal-fp-math=preserve-sign -denormal-fp-math-f32=preserve-sign -mattr=-flat-for-global < %s | FileCheck --check-prefixes=VI-FLUSH,GCN %s ; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=tonga -denormal-fp-math=ieee -denormal-fp-math-f32=preserve-sign -mattr=-flat-for-global < %s | FileCheck -check-prefix=GCN %s diff --git a/llvm/test/CodeGen/AMDGPU/verify-sop.mir b/llvm/test/CodeGen/AMDGPU/verify-sop.mir index e7fc19e9c9cc4..c52e5624653a8 100644 --- a/llvm/test/CodeGen/AMDGPU/verify-sop.mir +++ b/llvm/test/CodeGen/AMDGPU/verify-sop.mir @@ -1,5 +1,5 @@ -# RUN: not --crash llc -mtriple=amdgcn -run-pass machineverifier %s -o - 2>&1 | FileCheck %s -# RUN: not --crash llc -mtriple=amdgcn --passes='machine-function(verify)' %s -o - 2>&1 | FileCheck %s +# RUN: not --crash llc -mtriple=amdgcn -mcpu=gfx600 -run-pass machineverifier %s -o - 2>&1 | FileCheck %s +# RUN: not --crash llc -mtriple=amdgcn -mcpu=gfx600 --passes='machine-function(verify)' %s -o - 2>&1 | FileCheck %s # CHECK: *** Bad machine code: SOP2/SOPC instruction requires too many immediate constants # CHECK: - instruction: %0:sreg_32_xm0 = S_ADD_I32 diff --git a/llvm/test/CodeGen/AMDGPU/vop-shrink-frame-index.mir b/llvm/test/CodeGen/AMDGPU/vop-shrink-frame-index.mir index 7c032c2dc4972..4b67f10b79150 100644 --- a/llvm/test/CodeGen/AMDGPU/vop-shrink-frame-index.mir +++ b/llvm/test/CodeGen/AMDGPU/vop-shrink-frame-index.mir @@ -1,5 +1,5 @@ -# RUN: llc -mtriple=amdgcn -verify-machineinstrs -run-pass si-shrink-instructions -o - %s | FileCheck -check-prefix=GCN %s -# RUN: llc -mtriple=amdgcn -verify-machineinstrs -passes si-shrink-instructions -o - %s | FileCheck -check-prefix=GCN %s +# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -verify-machineinstrs -run-pass si-shrink-instructions -o - %s | FileCheck -check-prefix=GCN %s +# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -verify-machineinstrs -passes si-shrink-instructions -o - %s | FileCheck -check-prefix=GCN %s --- | define amdgpu_kernel void @fold_fi_vgpr() { diff --git a/llvm/test/CodeGen/AMDGPU/vop-shrink-non-ssa.mir b/llvm/test/CodeGen/AMDGPU/vop-shrink-non-ssa.mir index 292e96b4516fe..9e82fbb1835b7 100644 --- a/llvm/test/CodeGen/AMDGPU/vop-shrink-non-ssa.mir +++ b/llvm/test/CodeGen/AMDGPU/vop-shrink-non-ssa.mir @@ -1,5 +1,5 @@ -# RUN: llc -mtriple=amdgcn -verify-machineinstrs -run-pass si-shrink-instructions -o - %s | FileCheck -check-prefix=GCN %s -# RUN: llc -mtriple=amdgcn -verify-machineinstrs -passes si-shrink-instructions -o - %s | FileCheck -check-prefix=GCN %s +# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -verify-machineinstrs -run-pass si-shrink-instructions -o - %s | FileCheck -check-prefix=GCN %s +# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -verify-machineinstrs -passes si-shrink-instructions -o - %s | FileCheck -check-prefix=GCN %s ... # GCN-LABEL: name: fold_imm_non_ssa{{$}} # GCN: %0:vgpr_32 = V_MOV_B32_e32 123, implicit $exec _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
