[llvm-branch-commits] [llvm] [LoongArch] Add DAG combines for vector widening extends (PR #207316)

[via llvm-branch-commits]

================
@@ -8407,10 +8410,18 @@ static SDValue performEXTENDCombine(SDNode *N, 
SelectionDAG &DAG,
   EVT VT = N->getValueType(0);
   SDLoc DL(N);
 
-  if (VT.isVector())
+  if (VT.isVector()) {
     if (SDValue R = PromoteMaskArithmetic(SDValue(N, 0), DL, DAG, Subtarget))
       return R;
 
+    if (SDValue R = matchHalfOf128BitLanes(N->getOperand(0), false)) {
+      if (N->getOpcode() == ISD::SIGN_EXTEND)
+        return DAG.getNode(LoongArchISD::VEXTH, DL, VT, R);
+      else if (N->getOpcode() == ISD::ZERO_EXTEND)
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wangleiat wrote:

[Don’t use else after a return](https://llvm.org/docs/CodingStandards.html#id41)

https://github.com/llvm/llvm-project/pull/207316
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