https://github.com/gandhi56 updated https://github.com/llvm/llvm-project/pull/208624
>From 077fe473dd372abf7555f94e36bb14402601ed09 Mon Sep 17 00:00:00 2001 From: Anshil Gandhi <[email protected]> Date: Fri, 10 Jul 2026 00:20:22 -0500 Subject: [PATCH 1/2] [AMDGPU] Fix scratch address materialization in SVS frame index fallback --- llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | 20 ++++---------------- 1 file changed, 4 insertions(+), 16 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp index de1cae51db1b5..b3dc17e20d171 100644 --- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp @@ -3239,26 +3239,14 @@ bool SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI, : RS->scavengeRegisterBackwards(AMDGPU::SReg_32_XM0RegClass, MI, false, 0, !UseSGPR); - if ((!TmpSReg && !FrameReg) || (!TmpReg && !UseSGPR)) { + if (!TmpSReg || (!TmpReg && !UseSGPR)) { + assert(!FrameReg && "There is a frame register!"); int SVOpcode = AMDGPU::getFlatScratchInstSVfromSS(MI->getOpcode()); if (ST.hasFlatScratchSVSMode() && SVOpcode != -1) { Register TmpVGPR = RS->scavengeRegisterBackwards( AMDGPU::VGPR_32RegClass, MI, false, 0, /*AllowSpill=*/true); - - // Materialize the frame register. - auto MIB = - BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_MOV_B32_e32), TmpVGPR); - if (FrameReg) - MIB.addReg(FrameReg); - else - MIB.addImm(Offset); - - // Add the offset to the frame register. - if (FrameReg && Offset) - BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_ADD_U32_e32), FrameReg) - .addReg(FrameReg, RegState::Kill) - .addImm(Offset); - + BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_MOV_B32_e32), TmpVGPR) + .addImm(Offset); BuildMI(*MBB, MI, DL, TII->get(SVOpcode)) .add(MI->getOperand(0)) // $vdata .addReg(TmpVGPR) // $vaddr >From 960902e72f4f7e6c9981e292524592445e11e53d Mon Sep 17 00:00:00 2001 From: Anshil Gandhi <[email protected]> Date: Fri, 10 Jul 2026 14:55:12 -0400 Subject: [PATCH 2/2] Update llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp Co-authored-by: Shilei Tian <[email protected]> --- llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp index b3dc17e20d171..619db2f61e0e9 100644 --- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp @@ -3240,7 +3240,7 @@ bool SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI, MI, false, 0, !UseSGPR); if (!TmpSReg || (!TmpReg && !UseSGPR)) { - assert(!FrameReg && "There is a frame register!"); + assert(!FrameReg && "there is a frame register!"); int SVOpcode = AMDGPU::getFlatScratchInstSVfromSS(MI->getOpcode()); if (ST.hasFlatScratchSVSMode() && SVOpcode != -1) { Register TmpVGPR = RS->scavengeRegisterBackwards( _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
