llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-llvm-transforms @llvm/pr-subscribers-backend-amdgpu Author: Matt Arsenault (arsenm) <details> <summary>Changes</summary> Mechanically migrate the command-line target spelling on llc/opt RUN lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the redundant -mcpu. Co-Authored-By: Claude <noreply@<!-- -->anthropic.com> (Claude-Opus-4.8) --- Patch is 107.29 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/208893.diff 99 Files Affected: - (modified) llvm/test/CodeGen/AMDGPU/bug-deadlanes.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/bug-multi-operands-to-update-after-fold.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/bug-pk-f32-imm-fold.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/bug-sdag-emitcopyfromreg.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/bug-sdag-scheduler-cycle.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/bug-undef-spilled-agpr.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/bug-v4f64-subvector.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/bug-vopc-commute.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/build-vector-insert-elt-infloop.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/build-vector-packed-partial-undef.ll (+8-8) - (modified) llvm/test/CodeGen/AMDGPU/build_vector.gfx11plus.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/build_vector.ll (+5-5) - (modified) llvm/test/CodeGen/AMDGPU/bundle-breaks-phy-liveness.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/bundle-latency.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/bypass-div.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/byval-frame-setup.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/call-alias-register-usage-agpr.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/call-alias-register-usage0.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/call-alias-register-usage1.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/call-alias-register-usage2.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/call-alias-register-usage3.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/call-args-inreg-bfloat.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/call-args-inreg-no-sgpr-for-csrspill.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/call-args-inreg.ll (+4-4) - (modified) llvm/test/CodeGen/AMDGPU/call-argument-types.ll (+7-7) - (modified) llvm/test/CodeGen/AMDGPU/call-c-function.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/call-defs-mode-register.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/call-graph-register-usage.ll (+10-10) - (modified) llvm/test/CodeGen/AMDGPU/call-preserved-registers.ll (+8-8) - (modified) llvm/test/CodeGen/AMDGPU/call-reqd-group-size.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/call-return-types.ll (+7-7) - (modified) llvm/test/CodeGen/AMDGPU/call-skip.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/call-waitcnt.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/call-waw-waitcnt.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/callbr-intrinsics.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/callbr.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/callee-frame-setup.ll (+3-3) - (modified) llvm/test/CodeGen/AMDGPU/calling-conventions.ll (+6-6) - (modified) llvm/test/CodeGen/AMDGPU/captured-frame-index.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/carryout-selection.ll (+11-11) - (modified) llvm/test/CodeGen/AMDGPU/cc-entry.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/cc-inreg-sgpr0-3-mismatch.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/cc-sgpr-limit.ll (+3-3) - (modified) llvm/test/CodeGen/AMDGPU/cc-sgpr-over-limit.ll (+3-3) - (modified) llvm/test/CodeGen/AMDGPU/cc-update.ll (+4-4) - (modified) llvm/test/CodeGen/AMDGPU/cgp-addressing-modes-flat.ll (+8-8) - (modified) llvm/test/CodeGen/AMDGPU/cgp-addressing-modes-gfx1030.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/cgp-addressing-modes-smem.ll (+5-5) - (modified) llvm/test/CodeGen/AMDGPU/cgp-addressing-modes.ll (+8-8) - (modified) llvm/test/CodeGen/AMDGPU/cgp-bitfield-extract.ll (+4-4) - (modified) llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll (+8-8) - (modified) llvm/test/CodeGen/AMDGPU/chain-node-divergence-update-crash-issue-173885.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/change-scc-to-vcc.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/check-subtarget-features.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/clamp-modifier.ll (+5-5) - (modified) llvm/test/CodeGen/AMDGPU/clamp.ll (+7-7) - (modified) llvm/test/CodeGen/AMDGPU/clmul.ll (+7-7) - (modified) llvm/test/CodeGen/AMDGPU/cluster-dims.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/cluster-flat-loads-postra.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/cluster-flat-loads.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/cluster_stores.ll (+3-3) - (modified) llvm/test/CodeGen/AMDGPU/cmp_shrink.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/coalesce-copy-to-agpr-to-av-registers.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/coalesce-identity-copies-undef-subregs.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/coalesce-into-dead-subreg-copies.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/coalesce-liveout-undef-copy.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/coalesce-vgpr-alignment.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/coalescer-avoid-coalesce-class-with-no-registers.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/coalescer-avoid-coalesce-class-with-no-registers.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/coalescer-extend-pruned-subrange.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/coalescer-remat-dead-use.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/coalescer-removepartial-extend-undef-subrange.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/coalescer-subranges-another-copymi-not-live.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/coalescer-subranges-another-prune-error.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/coalescer-subranges-prune-kill-copy.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/coalescer-undef-subreg-use-invalid-lanemask.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/coalescer-with-subregs-bad-identical.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/coalescer_distribute.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/coalescing-subreg-was-undef-but-became-def.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/coalescing-with-subregs-in-loop-bug.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/coalescing_makes_lanes_undef.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/code-object-v3.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/code-size-estimate-gfx1250.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/code-size-estimate.ll (+6-6) - (modified) llvm/test/CodeGen/AMDGPU/code-size-estimate.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/codegen-internal-only-func.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/codegen-prepare-addrmode-sext.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/codegen-prepare-addrspacecast-non-null-vector.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/codegen-prepare-addrspacecast-non-null.ll (+3-3) - (modified) llvm/test/CodeGen/AMDGPU/coexec-rewrite-mfma.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/coexec-sched-effective-stall.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/coexec-sched-flavor-classification.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/coexec-sched-warning.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/coexec-scheduler.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/collapse-endcf.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/combine-add-zext-xor.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/combine-cond-add-sub.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/combine_andor_with_cmps.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/combine_andor_with_cmps_nnan.ll (+2-2) ``````````diff diff --git a/llvm/test/CodeGen/AMDGPU/bug-deadlanes.ll b/llvm/test/CodeGen/AMDGPU/bug-deadlanes.ll index 10ed7bd870491..13270435ebddb 100644 --- a/llvm/test/CodeGen/AMDGPU/bug-deadlanes.ll +++ b/llvm/test/CodeGen/AMDGPU/bug-deadlanes.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -amdgpu-codegenprepare-break-large-phis=false < %s | FileCheck %s +; RUN: llc -mtriple=amdgpu11.00 -amdgpu-codegenprepare-break-large-phis=false < %s | FileCheck %s ; CHECK-LABEL: {{^}}_amdgpu_ps_main: ; diff --git a/llvm/test/CodeGen/AMDGPU/bug-multi-operands-to-update-after-fold.mir b/llvm/test/CodeGen/AMDGPU/bug-multi-operands-to-update-after-fold.mir index d0c9740c6954e..19041ce0c930c 100644 --- a/llvm/test/CodeGen/AMDGPU/bug-multi-operands-to-update-after-fold.mir +++ b/llvm/test/CodeGen/AMDGPU/bug-multi-operands-to-update-after-fold.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 -# RUN: llc -mtriple=amdgcn-amd-hsa -mcpu=gfx1031 -run-pass=si-fold-operands -o - %s | FileCheck %s +# RUN: llc -mtriple=amdgpu10.31-amd-hsa -run-pass=si-fold-operands -o - %s | FileCheck %s --- name: snork body: | diff --git a/llvm/test/CodeGen/AMDGPU/bug-pk-f32-imm-fold.mir b/llvm/test/CodeGen/AMDGPU/bug-pk-f32-imm-fold.mir index a725fab5e40c1..10861bee99beb 100644 --- a/llvm/test/CodeGen/AMDGPU/bug-pk-f32-imm-fold.mir +++ b/llvm/test/CodeGen/AMDGPU/bug-pk-f32-imm-fold.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 -# RUN: llc -mtriple=amdgcn-amd-hsa -mcpu=gfx1250 -run-pass=si-fold-operands -o - %s | FileCheck %s +# RUN: llc -mtriple=amdgpu12.50-amd-hsa -run-pass=si-fold-operands -o - %s | FileCheck %s --- name: pk_add_f32_imm_fold diff --git a/llvm/test/CodeGen/AMDGPU/bug-sdag-emitcopyfromreg.ll b/llvm/test/CodeGen/AMDGPU/bug-sdag-emitcopyfromreg.ll index 0d35a966475ef..d50f4ca5ce1c8 100644 --- a/llvm/test/CodeGen/AMDGPU/bug-sdag-emitcopyfromreg.ll +++ b/llvm/test/CodeGen/AMDGPU/bug-sdag-emitcopyfromreg.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck %s -check-prefix=ISA -; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -stop-before=si-fix-sgpr-copies < %s | FileCheck %s -check-prefix=MIR +; RUN: llc -mtriple=amdgpu10.10 < %s | FileCheck %s -check-prefix=ISA +; RUN: llc -mtriple=amdgpu10.10 -stop-before=si-fix-sgpr-copies < %s | FileCheck %s -check-prefix=MIR define void @f(i32 %arg, ptr %ptr) { ; ISA-LABEL: f: diff --git a/llvm/test/CodeGen/AMDGPU/bug-sdag-scheduler-cycle.ll b/llvm/test/CodeGen/AMDGPU/bug-sdag-scheduler-cycle.ll index 93275d049893c..3e5ae99524781 100644 --- a/llvm/test/CodeGen/AMDGPU/bug-sdag-scheduler-cycle.ll +++ b/llvm/test/CodeGen/AMDGPU/bug-sdag-scheduler-cycle.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=amdgcn--amdpal -mcpu=gfx1010 | FileCheck %s --check-prefixes=CHECK +; RUN: llc < %s -mtriple=amdgpu10.10--amdpal | FileCheck %s --check-prefixes=CHECK ; This used to cause a circular chain dependency during ; SelectionDAG instruction scheduling. diff --git a/llvm/test/CodeGen/AMDGPU/bug-undef-spilled-agpr.mir b/llvm/test/CodeGen/AMDGPU/bug-undef-spilled-agpr.mir index 194f78b06613e..5c564decd1e7d 100644 --- a/llvm/test/CodeGen/AMDGPU/bug-undef-spilled-agpr.mir +++ b/llvm/test/CodeGen/AMDGPU/bug-undef-spilled-agpr.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -run-pass=si-lower-sgpr-spills,greedy,si-lower-wwm-copies,virtregrewriter,prolog-epilog -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s +# RUN: llc -mtriple=amdgpu9.08-amd-amdhsa -mcpu=gfx908 -run-pass=si-lower-sgpr-spills,greedy,si-lower-wwm-copies,virtregrewriter,prolog-epilog -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s --- name: widget diff --git a/llvm/test/CodeGen/AMDGPU/bug-v4f64-subvector.ll b/llvm/test/CodeGen/AMDGPU/bug-v4f64-subvector.ll index 3126491559d0a..d54c3f99107f6 100644 --- a/llvm/test/CodeGen/AMDGPU/bug-v4f64-subvector.ll +++ b/llvm/test/CodeGen/AMDGPU/bug-v4f64-subvector.ll @@ -1,5 +1,5 @@ -; RUN: llc < %s -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -start-before=amdgpu-isel -stop-after=amdgpu-isel | FileCheck %s --check-prefixes=CHECK -; RUN: llc < %s -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -start-before=amdgpu-isel -stop-after=amdgpu-isel -enable-new-pm | FileCheck %s --check-prefixes=CHECK +; RUN: llc < %s -mtriple=amdgpu9.00-amd-amdhsa -start-before=amdgpu-isel -stop-after=amdgpu-isel | FileCheck %s --check-prefixes=CHECK +; RUN: llc < %s -mtriple=amdgpu9.00-amd-amdhsa -start-before=amdgpu-isel -stop-after=amdgpu-isel -enable-new-pm | FileCheck %s --check-prefixes=CHECK ; This caused failure in infinite cycle in Selection DAG (combine) due to missing insert_subvector. ; diff --git a/llvm/test/CodeGen/AMDGPU/bug-vopc-commute.ll b/llvm/test/CodeGen/AMDGPU/bug-vopc-commute.ll index 21d4bcfcdc8c1..8922f4b3de2b2 100644 --- a/llvm/test/CodeGen/AMDGPU/bug-vopc-commute.ll +++ b/llvm/test/CodeGen/AMDGPU/bug-vopc-commute.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 -; RUN: llc -mtriple=amdgcn -mcpu=verde < %s | FileCheck -check-prefix=GFX6 %s -; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=GFX8 %s +; RUN: llc -mtriple=amdgpu6.01 < %s | FileCheck -check-prefix=GFX6 %s +; RUN: llc -mtriple=amdgpu8.02 < %s | FileCheck -check-prefix=GFX8 %s ; Test for compilation only. This generated an invalid machine instruction ; by trying to commute the operands of a V_CMP_EQ_i32_e32 instruction, both diff --git a/llvm/test/CodeGen/AMDGPU/build-vector-insert-elt-infloop.ll b/llvm/test/CodeGen/AMDGPU/build-vector-insert-elt-infloop.ll index 8f3e90528b2ce..c821e265b83c0 100644 --- a/llvm/test/CodeGen/AMDGPU/build-vector-insert-elt-infloop.ll +++ b/llvm/test/CodeGen/AMDGPU/build-vector-insert-elt-infloop.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu9.00-amd-amdhsa < %s | FileCheck -check-prefix=GCN %s ; There was an infinite loop in DAGCombiner from a target build_vector ; combine and a generic insert_vector_elt combine. diff --git a/llvm/test/CodeGen/AMDGPU/build-vector-packed-partial-undef.ll b/llvm/test/CodeGen/AMDGPU/build-vector-packed-partial-undef.ll index 9eff05237302e..1bfb37d01fcb1 100644 --- a/llvm/test/CodeGen/AMDGPU/build-vector-packed-partial-undef.ll +++ b/llvm/test/CodeGen/AMDGPU/build-vector-packed-partial-undef.ll @@ -1,12 +1,12 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=fiji < %s | FileCheck -enable-var-scope -check-prefixes=GFX8,GFX8-SDAG %s -; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn-amd-amdhsa -mcpu=fiji < %s | FileCheck -enable-var-scope -check-prefixes=GFX8,GFX8-GISEL %s -; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -enable-var-scope -check-prefixes=GFX9,GFX9-SDAG %s -; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -enable-var-scope -check-prefixes=GFX9,GFX9-GISEL %s -; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GFX11,GFX11-FAKE16,GFX11-FAKE16-SDAG %s -; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GFX11,GFX11-FAKE16,GFX11-FAKE16-GISEL %s -; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GFX11,GFX11-TRUE16,GFX11-TRUE16-SDAG %s -; RUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GFX11,GFX11-TRUE16,GFX11-TRUE16-GISEL %s +; RUN: llc -global-isel=0 -mtriple=amdgpu8.03-amd-amdhsa < %s | FileCheck -enable-var-scope -check-prefixes=GFX8,GFX8-SDAG %s +; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgpu8.03-amd-amdhsa < %s | FileCheck -enable-var-scope -check-prefixes=GFX8,GFX8-GISEL %s +; RUN: llc -global-isel=0 -mtriple=amdgpu9.00-amd-amdhsa < %s | FileCheck -enable-var-scope -check-prefixes=GFX9,GFX9-SDAG %s +; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgpu9.00-amd-amdhsa < %s | FileCheck -enable-var-scope -check-prefixes=GFX9,GFX9-GISEL %s +; RUN: llc -global-isel=0 -mtriple=amdgpu11.00-amd-amdhsa -mattr=-real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GFX11,GFX11-FAKE16,GFX11-FAKE16-SDAG %s +; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgpu11.00-amd-amdhsa -mattr=-real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GFX11,GFX11-FAKE16,GFX11-FAKE16-GISEL %s +; RUN: llc -global-isel=0 -mtriple=amdgpu11.00-amd-amdhsa -mattr=+real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GFX11,GFX11-TRUE16,GFX11-TRUE16-SDAG %s +; RUN: llc -global-isel=1 -mtriple=amdgpu11.00-amd-amdhsa -mattr=+real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GFX11,GFX11-TRUE16,GFX11-TRUE16-GISEL %s define void @undef_lo_v2i16(i16 %arg0) { ; GFX8-LABEL: undef_lo_v2i16: diff --git a/llvm/test/CodeGen/AMDGPU/build_vector.gfx11plus.ll b/llvm/test/CodeGen/AMDGPU/build_vector.gfx11plus.ll index 6940c437d13fe..f40a176b63eaa 100644 --- a/llvm/test/CodeGen/AMDGPU/build_vector.gfx11plus.ll +++ b/llvm/test/CodeGen/AMDGPU/build_vector.gfx11plus.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 -; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -stop-after=amdgpu-isel | FileCheck %s --check-prefixes=GFX11-REAL16 -; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -stop-after=amdgpu-isel | FileCheck %s --check-prefixes=GFX11-FAKE16 +; RUN: llc < %s -mtriple=amdgpu11.00 -mattr=+real-true16 -stop-after=amdgpu-isel | FileCheck %s --check-prefixes=GFX11-REAL16 +; RUN: llc < %s -mtriple=amdgpu11.00 -mattr=-real-true16 -stop-after=amdgpu-isel | FileCheck %s --check-prefixes=GFX11-FAKE16 ; Make sure no "vgpr32 = copy vgpr16" is generated diff --git a/llvm/test/CodeGen/AMDGPU/build_vector.ll b/llvm/test/CodeGen/AMDGPU/build_vector.ll index 62599aa9d7d08..34aec586aef78 100644 --- a/llvm/test/CodeGen/AMDGPU/build_vector.ll +++ b/llvm/test/CodeGen/AMDGPU/build_vector.ll @@ -1,9 +1,9 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 -; RUN: llc < %s -mtriple=amdgcn -mcpu=tahiti | FileCheck %s --check-prefixes=GFX6,GCN -; RUN: llc < %s -mtriple=amdgcn -mcpu=tonga | FileCheck %s --check-prefixes=GFX8,GCN -; RUN: llc < %s -mtriple=amdgcn-amd-amdpal -mcpu=gfx1030 | FileCheck %s --check-prefixes=GFX10,GCN -; RUN: llc < %s -mtriple=amdgcn-amd-amdpal -mcpu=gfx1100 -amdgpu-enable-vopd=0 | FileCheck %s --check-prefixes=GFX11,GCN -; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx942 | FileCheck %s --check-prefixes=GFX942,GCN +; RUN: llc < %s -mtriple=amdgpu6.00 | FileCheck %s --check-prefixes=GFX6,GCN +; RUN: llc < %s -mtriple=amdgpu8.02 | FileCheck %s --check-prefixes=GFX8,GCN +; RUN: llc < %s -mtriple=amdgpu10.30-amd-amdpal | FileCheck %s --check-prefixes=GFX10,GCN +; RUN: llc < %s -mtriple=amdgpu11.00-amd-amdpal -amdgpu-enable-vopd=0 | FileCheck %s --check-prefixes=GFX11,GCN +; RUN: llc < %s -mtriple=amdgpu9.42 | FileCheck %s --check-prefixes=GFX942,GCN define amdgpu_kernel void @build_vector2 (ptr addrspace(1) %out) { ; GFX6-LABEL: build_vector2: diff --git a/llvm/test/CodeGen/AMDGPU/bundle-breaks-phy-liveness.mir b/llvm/test/CodeGen/AMDGPU/bundle-breaks-phy-liveness.mir index 5c7dc8a079345..bc66f67cf37fa 100644 --- a/llvm/test/CodeGen/AMDGPU/bundle-breaks-phy-liveness.mir +++ b/llvm/test/CodeGen/AMDGPU/bundle-breaks-phy-liveness.mir @@ -1,6 +1,6 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 -# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -run-pass=si-insert-hard-clauses -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN-CLAUSE %s -# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -run-pass=si-post-ra-bundler -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN-BUNDLE %s +# RUN: llc -mtriple=amdgpu12.00 -run-pass=si-insert-hard-clauses -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN-CLAUSE %s +# RUN: llc -mtriple=amdgpu12.00 -run-pass=si-post-ra-bundler -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN-BUNDLE %s --- name: clause_implicit_def diff --git a/llvm/test/CodeGen/AMDGPU/bundle-latency.mir b/llvm/test/CodeGen/AMDGPU/bundle-latency.mir index 9f2c6d1b53bb8..35d5737bd51fd 100644 --- a/llvm/test/CodeGen/AMDGPU/bundle-latency.mir +++ b/llvm/test/CodeGen/AMDGPU/bundle-latency.mir @@ -1,6 +1,6 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass=post-RA-sched %s -o - | FileCheck -check-prefix=GCN %s -# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -passes=post-RA-sched %s -o - | FileCheck -check-prefix=GCN %s +# RUN: llc -mtriple=amdgpu9.00 -verify-machineinstrs -run-pass=post-RA-sched %s -o - | FileCheck -check-prefix=GCN %s +# RUN: llc -mtriple=amdgpu9.00 -passes=post-RA-sched %s -o - | FileCheck -check-prefix=GCN %s # Check that we move consumer further from producer, even if one of them is in a bundle. diff --git a/llvm/test/CodeGen/AMDGPU/bypass-div.ll b/llvm/test/CodeGen/AMDGPU/bypass-div.ll index d3cd1dad991f2..4010766d2add3 100644 --- a/llvm/test/CodeGen/AMDGPU/bypass-div.ll +++ b/llvm/test/CodeGen/AMDGPU/bypass-div.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s +; RUN: llc -mtriple=amdgpu9.00-amd-amdhsa < %s | FileCheck -check-prefix=GFX9 %s ; 64-bit divides and rems should be split into a fast and slow path ; where the fast path uses a 32-bit operation. diff --git a/llvm/test/CodeGen/AMDGPU/byval-frame-setup.ll b/llvm/test/CodeGen/AMDGPU/byval-frame-setup.ll index 1cc620903e904..7bddd1f15b037 100644 --- a/llvm/test/CodeGen/AMDGPU/byval-frame-setup.ll +++ b/llvm/test/CodeGen/AMDGPU/byval-frame-setup.ll @@ -1,5 +1,5 @@ -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -enable-ipra=0 < %s | FileCheck -enable-var-scope --check-prefix=GCN %s -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -enable-ipra=0 < %s | FileCheck -enable-var-scope --check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu8.03-amd-amdhsa -enable-ipra=0 < %s | FileCheck -enable-var-scope --check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu7.01-amd-amdhsa -enable-ipra=0 < %s | FileCheck -enable-var-scope --check-prefix=GCN %s %struct.ByValStruct = type { [4 x i32] } ; Make sure the offset is folded and function's frame register is used diff --git a/llvm/test/CodeGen/AMDGPU/call-alias-register-usage-agpr.ll b/llvm/test/CodeGen/AMDGPU/call-alias-register-usage-agpr.ll index ce9f65eee2c3b..4ee6585c0a84a 100644 --- a/llvm/test/CodeGen/AMDGPU/call-alias-register-usage-agpr.ll +++ b/llvm/test/CodeGen/AMDGPU/call-alias-register-usage-agpr.ll @@ -1,5 +1,5 @@ -; RUN: llc -O0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 < %s | FileCheck -check-prefix=ALL %s -; RUN: llc -O0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a < %s | FileCheck -check-prefixes=ALL,GFX90A %s +; RUN: llc -O0 -mtriple=amdgpu9.08-amd-amdhsa < %s | FileCheck -check-prefix=ALL %s +; RUN: llc -O0 -mtriple=amdgpu9.0a-amd-amdhsa < %s | FileCheck -check-prefixes=ALL,GFX90A %s ; CallGraphAnalysis, which CodeGenSCC order depends on, does not look ; through aliases. If GlobalOpt is never run, we do not see direct diff --git a/llvm/test/CodeGen/AMDGPU/call-alias-register-usage0.ll b/llvm/test/CodeGen/AMDGPU/call-alias-register-usage0.ll index b61e7d90d87bf..8e74dcdd9490f 100644 --- a/llvm/test/CodeGen/AMDGPU/call-alias-register-usage0.ll +++ b/llvm/test/CodeGen/AMDGPU/call-alias-register-usage0.ll @@ -1,4 +1,4 @@ -; RUN: llc -O0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck %s +; RUN: llc -O0 -mtriple=amdgpu9.00-amd-amdhsa < %s | FileCheck %s ; CallGraphAnalysis, which CodeGenSCC order depends on, does not look ; through aliases. If GlobalOpt is never run, we do not see direct diff --git a/llvm/test/CodeGen/AMDGPU/call-alias-register-usage1.ll b/llvm/test/CodeGen/AMDGPU/call-alias-register-usage1.ll index fe45043deaa0b..05412b343ecb7 100644 --- a/llvm/test/CodeGen/AMDGPU/call-alias-register-usage1.ll +++ b/llvm/test/CodeGen/AMDGPU/call-alias-register-usage1.ll @@ -1,4 +1,4 @@ -; RUN: llc -O0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck %s +; RUN: llc -O0 -mtriple=amdgpu9.00-amd-amdhsa < %s | FileCheck %s ; CallGraphAnalysis, which CodeGenSCC order depends on, does not look ; through aliases. If GlobalOpt is never run, we do not see direct diff --git a/llvm/test/CodeGen/AMDGPU/call-alias-register-usage2.ll b/llvm/test/CodeGen/AMDGPU/call-alias-register-usage2.ll index 0dc2780ae0444..5735ef21b084d 100644 --- a/llvm/test/CodeGen/AMDGPU/call-alias-register-usage2.ll +++ b/llvm/test/CodeGen/AMDGPU/call-alias-register-usage2.ll @@ -1,4 +1,4 @@ -; RUN: llc -O0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck %s +; RUN: llc -O0 -mtriple=amdgpu9.00-amd-amdhsa < %s | FileCheck %s ; CallGraphAnalysis, which CodeGenSCC order depends on, does not look ; through aliases. If GlobalOpt is never run, we do not see direct diff --git a/llvm/test/CodeGen/AMDGPU/call-alias-register-usage3.ll b/llvm/test/CodeGen/AMDGPU/call-alias-register-usage3.ll index 1ea9e7f2f8fee..7e6be8593e3c5 100644 --- a/llvm/test/CodeGen/AMDGPU/call-alias-register-usage3.ll +++ b/llvm/test/CodeGen/AMDGPU/call-alias-register-usage3.ll @@ -1,4 +1,4 @@ -; RUN: llc -O0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck %s +; RUN: llc -O0 -mtriple=amdgpu9.00-amd-amdhsa < %s | FileCheck %s ; CallGraphAnalysis, which CodeGenSCC order depends on, does not look ; through aliases. If GlobalOpt is never run, we do not see direct diff --git a/llvm/test/CodeGen/AMDGPU/call-args-inreg-bfloat.ll b/llvm/test/CodeGen/AMDGPU/call-args-inreg-bfloat.ll index 05adc43fe0463..fb1ac275301ed 100644 --- a/llvm/test/CodeGen/AMDGPU/call-args-inreg-bfloat.ll +++ b/llvm/test/CodeGen/AMDGPU/call-args-inreg-bfloat.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -enable-var-scope -check-prefix=GFX9 %s -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 < %s | FileCheck -enable-var-scope -check-prefix=GFX11 %s +; RUN: llc -mtriple=amdgpu9.00-amd-amdhsa < %s | FileCheck -enable-var-scope -check-prefix=GFX9 %s +; RUN: llc -mtriple=amdgpu11.00-amd-amdhsa < %s | FileCheck -enable-var-scope -check-prefix=GFX11 %s ; We've separated this file from call-args-inreg.ll since GlobalISel does not support the bfloat type. ; Ideally, we should merge the two files once that support lands. diff --git a/llvm/test/CodeGen/AMDGPU/call-args-inreg-no-sgpr-for-csrspill.ll b/llvm/test/CodeGen/AMDGPU/call-args-inreg-no-sgpr-for-csrspill.ll index 9ae866ea33226..ff7814fd28076 100644 --- a/llvm/test/CodeGen/AMDGPU/call-args-inreg-no-sgpr-for-csrspill.ll +++ b/llvm/test/CodeGen/AMDGPU/call-args-inreg-no-sgpr-for-csrspill.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -enable-var-scope %s +; RUN: llc -mtriple=amdgpu9.00-amd-amdhsa < %s | FileCheck -enable-var-scope %s define hidden void @external_void_func_a15i32_inreg([15 x i32] inreg %args) #0 { ; CHECK-LABEL: external_void_func_a15i32_inreg: diff --git a/llvm/test/CodeGen/AMDGPU/call-args-inreg.ll b/llvm/test/CodeGen/AMDGPU/call-args-inreg.ll index 0ad79da451b5b..aac43267b2785 100644 --- a/llvm/test/CodeGen/AMDGPU/call-args-inreg.ll +++ b/llvm/test/CodeGen/AMDGPU/call-args-inreg.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 -; RUN: ... [truncated] `````````` </details> https://github.com/llvm/llvm-project/pull/208893 _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
