llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-backend-amdgpu Author: Matt Arsenault (arsenm) <details> <summary>Changes</summary> Mechanically migrate the command-line target spelling on llc/opt RUN lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the redundant -mcpu. Co-Authored-By: Claude <noreply@<!-- -->anthropic.com> (Claude-Opus-4.8) --- Patch is 87.28 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/208894.diff 97 Files Affected: - (modified) llvm/test/CodeGen/AMDGPU/combine-ftrunc.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/combine-vload-extract.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/commute-compares-scalar-float.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/commute-frame-index-operand.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/commute-op-sel.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/commute-shifts.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/commute-vop3.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/compute-known-bits-nofpclass.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/computeKnownBits-scalar-to-vector-crash.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/computeNumSignBits-mul.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/concat_vectors.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/consecutive-loads-in-branch.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/constant-address-space-32bit.ll (+4-4) - (modified) llvm/test/CodeGen/AMDGPU/constant-fold-imm-immreg.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/constant-fold-mi-operands.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/constrained-shift.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/convergence-laneops.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/convergence-tokens.ll (+3-3) - (modified) llvm/test/CodeGen/AMDGPU/copy-hoist-no-spills.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/copy-illegal-type.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/copy-overlap-sgpr-kill.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/copy-overlap-vgpr-kill.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/copy-phys-reg-implicit-operand-kills-subregs.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/copy-to-reg-frameindex.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/copy-to-reg-scc-clobber.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/copy-to-reg.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/copy-vgpr-clobber-spill-vgpr.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/copy_phys_vgpr64.mir (+6-6) - (modified) llvm/test/CodeGen/AMDGPU/copy_to_scc.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/copysign-simplify-demanded-bits.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/copysign-to-disjoint-or-combine.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/couldnt-join-subrange-3.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/cross-block-use-is-not-abi-copy.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/cse-convergent.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/cse-phi-incoming-val.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/csr-gfx10.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/csr-sgpr-spill-live-ins.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/ctls.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/ctlz.ll (+6-6) - (modified) llvm/test/CodeGen/AMDGPU/ctlz_zero_poison.ll (+3-3) - (modified) llvm/test/CodeGen/AMDGPU/ctpop.ll (+4-4) - (modified) llvm/test/CodeGen/AMDGPU/ctpop16.ll (+4-4) - (modified) llvm/test/CodeGen/AMDGPU/ctpop64.ll (+3-3) - (modified) llvm/test/CodeGen/AMDGPU/cttz.ll (+4-4) - (modified) llvm/test/CodeGen/AMDGPU/cttz_zero_poison.ll (+3-3) - (modified) llvm/test/CodeGen/AMDGPU/cube.ll (+4-4) - (modified) llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll (+6-6) - (modified) llvm/test/CodeGen/AMDGPU/cvt_flr_i32_f32.ll (+4-4) - (modified) llvm/test/CodeGen/AMDGPU/cvt_rpi_i32_f32.ll (+4-4) - (modified) llvm/test/CodeGen/AMDGPU/d16-write-vgpr32.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/dag-divergence-atomic.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/dag-divergence.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/dag-preserve-disjoint-flag.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/dagcomb-extract-vec-elt-different-sizes.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/dagcomb-mullohi.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/dagcombine-fma-crash.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/dagcombine-fma-fmad.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll (+10-10) - (modified) llvm/test/CodeGen/AMDGPU/dagcombine-reassociate-multi-memop.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/dagcombine-select.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/dagcombine-setcc-select.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/dagcombine-v1i8-extractvecelt-crash.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/dbg-info-inline-at.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/dbg-value-ends-sched-region.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/dbg-value-starts-sched-region.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/dead-frame-index-dbg-value.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/dead-lane.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/dead-machine-elim-after-dead-lane.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/dead_bundle.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/dead_copy.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/debug-frame.ll (+4-4) - (modified) llvm/test/CodeGen/AMDGPU/debug-independence-dead-mi-elimination.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/debug-independence-exec-masking.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/debug-value-scheduler-crash.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/debug-value-scheduler-liveins.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/debug-value-scheduler.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/debug.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/default-flat-work-group-size-overrides-waves-per-eu.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/direct-indirect-call.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/disable_form_clauses.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/div-rem-by-constant-64.ll (+4-4) - (modified) llvm/test/CodeGen/AMDGPU/div-rem-fast-path.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/div_i128.ll (+4-4) - (modified) llvm/test/CodeGen/AMDGPU/diverge-extra-formal-args.ll (+3-3) - (modified) llvm/test/CodeGen/AMDGPU/diverge-interp-mov-lower.ll (+6-6) - (modified) llvm/test/CodeGen/AMDGPU/diverge-switch-default.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/divergence-at-use.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/divergence-driven-abs.ll (+4-4) - (modified) llvm/test/CodeGen/AMDGPU/divergence-driven-buildvector.ll (+5-5) - (modified) llvm/test/CodeGen/AMDGPU/divergence-driven-negsubinlineconst.ll (+4-4) - (modified) llvm/test/CodeGen/AMDGPU/divergence-driven-xnor.ll (+4-4) - (modified) llvm/test/CodeGen/AMDGPU/divergent-branch-uniform-condition.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/divrem24-assume.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/do-not-fold-copy.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/dpp_combine-true16.mir (+3-3) - (modified) llvm/test/CodeGen/AMDGPU/dpp_combine_gfx11.mir (+3-3) - (modified) llvm/test/CodeGen/AMDGPU/dpp_combine_gfx1250.mir (+1-1) ``````````diff diff --git a/llvm/test/CodeGen/AMDGPU/combine-ftrunc.ll b/llvm/test/CodeGen/AMDGPU/combine-ftrunc.ll index 8a01964382623..5cd1cdd20781b 100644 --- a/llvm/test/CodeGen/AMDGPU/combine-ftrunc.ll +++ b/llvm/test/CodeGen/AMDGPU/combine-ftrunc.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu8.02 < %s | FileCheck -check-prefix=GCN %s ; GCN-LABEL: {{^}}combine_ftrunc_frint_f64: ; GCN: v_rndne_f64_e32 [[RND:v\[[0-9:]+\]]], diff --git a/llvm/test/CodeGen/AMDGPU/combine-vload-extract.ll b/llvm/test/CodeGen/AMDGPU/combine-vload-extract.ll index 211174af632ee..a2bf889fe3297 100644 --- a/llvm/test/CodeGen/AMDGPU/combine-vload-extract.ll +++ b/llvm/test/CodeGen/AMDGPU/combine-vload-extract.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=amdgcn -mcpu=gfx90a < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu9.0a < %s | FileCheck -check-prefix=GCN %s define amdgpu_kernel void @vectorLoadCombine(ptr %in, ptr %out) { ; GCN-LABEL: vectorLoadCombine: diff --git a/llvm/test/CodeGen/AMDGPU/commute-compares-scalar-float.ll b/llvm/test/CodeGen/AMDGPU/commute-compares-scalar-float.ll index 369e3e796b273..6d8e78acdfc00 100644 --- a/llvm/test/CodeGen/AMDGPU/commute-compares-scalar-float.ll +++ b/llvm/test/CodeGen/AMDGPU/commute-compares-scalar-float.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=amdgcn -mcpu=gfx1150 -amdgpu-sdwa-peephole=0 < %s | FileCheck -check-prefix=SDAG %s -; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1150 -amdgpu-sdwa-peephole=0 < %s | FileCheck -check-prefix=GISEL %s +; RUN: llc -mtriple=amdgpu11.50 -amdgpu-sdwa-peephole=0 < %s | FileCheck -check-prefix=SDAG %s +; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgpu11.50 -amdgpu-sdwa-peephole=0 < %s | FileCheck -check-prefix=GISEL %s define amdgpu_vs void @fcmp_f32_olt_to_ogt(ptr addrspace(1) inreg %out, float inreg %a) { ; SDAG-LABEL: fcmp_f32_olt_to_ogt: diff --git a/llvm/test/CodeGen/AMDGPU/commute-frame-index-operand.mir b/llvm/test/CodeGen/AMDGPU/commute-frame-index-operand.mir index a891d8f18e861..a8c541e9450f6 100644 --- a/llvm/test/CodeGen/AMDGPU/commute-frame-index-operand.mir +++ b/llvm/test/CodeGen/AMDGPU/commute-frame-index-operand.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 -# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -run-pass=machine-cse -verify-machineinstrs %s -o - | FileCheck --check-prefix=GCN %s +# RUN: llc -mtriple=amdgpu9.00 -run-pass=machine-cse -verify-machineinstrs %s -o - | FileCheck --check-prefix=GCN %s # Check that invalid MIR is not produced with a frame index in a # commutable operand. diff --git a/llvm/test/CodeGen/AMDGPU/commute-op-sel.mir b/llvm/test/CodeGen/AMDGPU/commute-op-sel.mir index 9274c995dde92..322784815cf93 100644 --- a/llvm/test/CodeGen/AMDGPU/commute-op-sel.mir +++ b/llvm/test/CodeGen/AMDGPU/commute-op-sel.mir @@ -1,4 +1,4 @@ -# RUN: llc -mtriple=amdgcn -mcpu=gfx1030 -run-pass=machine-cse -verify-machineinstrs %s -o - 2>&1 | FileCheck --check-prefix=GCN %s +# RUN: llc -mtriple=amdgpu10.30 -run-pass=machine-cse -verify-machineinstrs %s -o - 2>&1 | FileCheck --check-prefix=GCN %s --- name: test_machine_cse_op_sel_v_add_nc_u16 diff --git a/llvm/test/CodeGen/AMDGPU/commute-shifts.ll b/llvm/test/CodeGen/AMDGPU/commute-shifts.ll index d1fe78de375d1..969d77e63a11d 100644 --- a/llvm/test/CodeGen/AMDGPU/commute-shifts.ll +++ b/llvm/test/CodeGen/AMDGPU/commute-shifts.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=amdgcn -mcpu=verde < %s | FileCheck -check-prefix=SI %s -; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=VI %s +; RUN: llc -mtriple=amdgpu6.01 < %s | FileCheck -check-prefix=SI %s +; RUN: llc -mtriple=amdgpu8.02 < %s | FileCheck -check-prefix=VI %s define amdgpu_ps float @main(float %arg0, float %arg1) #0 { ; SI-LABEL: main: diff --git a/llvm/test/CodeGen/AMDGPU/commute-vop3.mir b/llvm/test/CodeGen/AMDGPU/commute-vop3.mir index 9a8805effb5bd..7f93661f5482d 100644 --- a/llvm/test/CodeGen/AMDGPU/commute-vop3.mir +++ b/llvm/test/CodeGen/AMDGPU/commute-vop3.mir @@ -1,6 +1,6 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -run-pass=machine-cse -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX9 %s -# RUN: llc -run-pass=machine-cse -mtriple=amdgcn -mcpu=gfx1010 -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX10 %s +# RUN: llc -run-pass=machine-cse -mtriple=amdgpu9.00 -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX9 %s +# RUN: llc -run-pass=machine-cse -mtriple=amdgpu10.10 -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX10 %s --- diff --git a/llvm/test/CodeGen/AMDGPU/compute-known-bits-nofpclass.ll b/llvm/test/CodeGen/AMDGPU/compute-known-bits-nofpclass.ll index 244c3f7c2a96a..75276dc1df889 100644 --- a/llvm/test/CodeGen/AMDGPU/compute-known-bits-nofpclass.ll +++ b/llvm/test/CodeGen/AMDGPU/compute-known-bits-nofpclass.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck %s +; RUN: llc -mtriple=amdgpu9.00-amd-amdhsa < %s | FileCheck %s define i32 @known_positive(float nofpclass(nan ninf nzero nsub nnorm) %signbit.zero) #0 { ; CHECK-LABEL: known_positive: diff --git a/llvm/test/CodeGen/AMDGPU/computeKnownBits-scalar-to-vector-crash.ll b/llvm/test/CodeGen/AMDGPU/computeKnownBits-scalar-to-vector-crash.ll index b93ece7ca04f3..3a857395d69c8 100644 --- a/llvm/test/CodeGen/AMDGPU/computeKnownBits-scalar-to-vector-crash.ll +++ b/llvm/test/CodeGen/AMDGPU/computeKnownBits-scalar-to-vector-crash.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn -mcpu=gfx802 < %s | FileCheck %s +; RUN: llc -mtriple=amdgpu8.02 < %s | FileCheck %s ; CHECK: s_waitcnt define <2 x i16> @main(<2 x float>) #0 { diff --git a/llvm/test/CodeGen/AMDGPU/computeNumSignBits-mul.ll b/llvm/test/CodeGen/AMDGPU/computeNumSignBits-mul.ll index 11795cca18daa..7691944970f50 100644 --- a/llvm/test/CodeGen/AMDGPU/computeNumSignBits-mul.ll +++ b/llvm/test/CodeGen/AMDGPU/computeNumSignBits-mul.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -o - -amdgpu-codegenprepare-mul24=0 < %s | FileCheck -check-prefix=GFX9 %s +; RUN: llc -mtriple=amdgpu9.00-amd-amdhsa -o - -amdgpu-codegenprepare-mul24=0 < %s | FileCheck -check-prefix=GFX9 %s define i16 @num_sign_bits_mul_i48_0(i8 %X, i8 %Y, i8 %Z, i8 %W) { ; GFX9-LABEL: num_sign_bits_mul_i48_0: diff --git a/llvm/test/CodeGen/AMDGPU/concat_vectors.ll b/llvm/test/CodeGen/AMDGPU/concat_vectors.ll index 09f81011e03be..034139e2eef1c 100644 --- a/llvm/test/CodeGen/AMDGPU/concat_vectors.ll +++ b/llvm/test/CodeGen/AMDGPU/concat_vectors.ll @@ -1,5 +1,5 @@ -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -enable-var-scope --check-prefix=GCN %s -; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -check-prefixes=GCN,VI %s +; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck -enable-var-scope --check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu8.02 -mattr=-flat-for-global < %s | FileCheck -check-prefixes=GCN,VI %s ; GCN-LABEL: {{^}}test_concat_v1i32: ; 0x80f000 is the high 32 bits of the resource descriptor used by MUBUF diff --git a/llvm/test/CodeGen/AMDGPU/consecutive-loads-in-branch.ll b/llvm/test/CodeGen/AMDGPU/consecutive-loads-in-branch.ll index f9f481f56fa7c..ceef5614bc94e 100644 --- a/llvm/test/CodeGen/AMDGPU/consecutive-loads-in-branch.ll +++ b/llvm/test/CodeGen/AMDGPU/consecutive-loads-in-branch.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 < %s | FileCheck -check-prefix=GFX12 %s +; RUN: llc -mtriple=amdgpu12.00-amd-amdhsa < %s | FileCheck -check-prefix=GFX12 %s define amdgpu_kernel void @straightline_kernel(ptr addrspace(1) noalias %in, ptr addrspace(1) noalias %out, i32 %base, i1 %cond) { ; GFX12-LABEL: straightline_kernel: diff --git a/llvm/test/CodeGen/AMDGPU/constant-address-space-32bit.ll b/llvm/test/CodeGen/AMDGPU/constant-address-space-32bit.ll index 11edef2929d7d..22fbbe3fe33b8 100644 --- a/llvm/test/CodeGen/AMDGPU/constant-address-space-32bit.ll +++ b/llvm/test/CodeGen/AMDGPU/constant-address-space-32bit.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 -; RUN: llc -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefixes=GFX67,GFX6 %s -; RUN: llc -mtriple=amdgcn -mcpu=bonaire < %s | FileCheck -check-prefixes=GFX67,GFX7 %s -; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=GFX89,GFX8 %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX89,GFX9 %s +; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck -check-prefixes=GFX67,GFX6 %s +; RUN: llc -mtriple=amdgpu7.04 < %s | FileCheck -check-prefixes=GFX67,GFX7 %s +; RUN: llc -mtriple=amdgpu8.02 < %s | FileCheck -check-prefixes=GFX89,GFX8 %s +; RUN: llc -mtriple=amdgpu9.00 < %s | FileCheck -check-prefixes=GFX89,GFX9 %s define amdgpu_vs float @load_i32(ptr addrspace(6) inreg %p0, ptr addrspace(6) inreg %p1) #0 { ; GFX67-LABEL: load_i32: diff --git a/llvm/test/CodeGen/AMDGPU/constant-fold-imm-immreg.mir b/llvm/test/CodeGen/AMDGPU/constant-fold-imm-immreg.mir index e843de15b90ec..5a2b055a110f8 100644 --- a/llvm/test/CodeGen/AMDGPU/constant-fold-imm-immreg.mir +++ b/llvm/test/CodeGen/AMDGPU/constant-fold-imm-immreg.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6 -# RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx900 -verify-machineinstrs -run-pass si-fold-operands,dead-mi-elimination -o - %s | FileCheck -enable-var-scope -check-prefix=GCN %s +# RUN: llc -mtriple=amdgpu9.00--amdhsa -verify-machineinstrs -run-pass si-fold-operands,dead-mi-elimination -o - %s | FileCheck -enable-var-scope -check-prefix=GCN %s ... # GCN-LABEL: name: s_fold_and_imm_regimm_32{{$}} diff --git a/llvm/test/CodeGen/AMDGPU/constant-fold-mi-operands.ll b/llvm/test/CodeGen/AMDGPU/constant-fold-mi-operands.ll index 0691ae53d3bc5..d8e5935dc1323 100644 --- a/llvm/test/CodeGen/AMDGPU/constant-fold-mi-operands.ll +++ b/llvm/test/CodeGen/AMDGPU/constant-fold-mi-operands.ll @@ -1,5 +1,5 @@ -; RUN: llc -mtriple=amdgcn--amdpal -mcpu=verde < %s | FileCheck -check-prefix=GCN %s -; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu6.01--amdpal < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu8.02--amdpal -mattr=-flat-for-global < %s | FileCheck -check-prefix=GCN %s ; GCN-LABEL: {{^}}fold_mi_v_and_0: ; GCN: v_mov_b32_e32 [[RESULT:v[0-9]+]], 0{{$}} diff --git a/llvm/test/CodeGen/AMDGPU/constrained-shift.ll b/llvm/test/CodeGen/AMDGPU/constrained-shift.ll index d7a21ce245d75..d2fee5930dd9c 100644 --- a/llvm/test/CodeGen/AMDGPU/constrained-shift.ll +++ b/llvm/test/CodeGen/AMDGPU/constrained-shift.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -global-isel < %s | FileCheck -check-prefix=GISEL %s +; RUN: llc -mtriple=amdgpu9.00 < %s | FileCheck %s +; RUN: llc -mtriple=amdgpu9.00 -global-isel < %s | FileCheck -check-prefix=GISEL %s define i16 @csh_16(i16 %a, i16 %b) { ; CHECK-LABEL: csh_16: diff --git a/llvm/test/CodeGen/AMDGPU/convergence-laneops.ll b/llvm/test/CodeGen/AMDGPU/convergence-laneops.ll index 57ab371d5b6fc..64a6edcc72c93 100644 --- a/llvm/test/CodeGen/AMDGPU/convergence-laneops.ll +++ b/llvm/test/CodeGen/AMDGPU/convergence-laneops.ll @@ -1,5 +1,5 @@ -; RUN: llc -stop-after=amdgpu-isel -mtriple=amdgcn-- -mcpu=gfx1100 -verify-machineinstrs -o - %s | FileCheck --check-prefixes=CHECK,ISEL %s -; RUN: not --crash llc -mtriple=amdgcn--amdhsa -mcpu=gfx1100 -verify-machineinstrs < %s 2>&1 | FileCheck --check-prefix=CHECK-ERROR %s +; RUN: llc -stop-after=amdgpu-isel -mtriple=amdgpu11.00-- -verify-machineinstrs -o - %s | FileCheck --check-prefixes=CHECK,ISEL %s +; RUN: not --crash llc -mtriple=amdgpu11.00--amdhsa -verify-machineinstrs < %s 2>&1 | FileCheck --check-prefix=CHECK-ERROR %s ; FIXME: Merge these tests with existing lane op tests (llvm.amdgcn.readlane.ll, llvm.amdgcn.writelane.ll ...) once the crash is fixed. diff --git a/llvm/test/CodeGen/AMDGPU/convergence-tokens.ll b/llvm/test/CodeGen/AMDGPU/convergence-tokens.ll index 61d102d2222bd..78909952aeb70 100644 --- a/llvm/test/CodeGen/AMDGPU/convergence-tokens.ll +++ b/llvm/test/CodeGen/AMDGPU/convergence-tokens.ll @@ -1,6 +1,6 @@ -; RUN: llc -stop-after=amdgpu-isel -mtriple=amdgcn-- -mcpu=gfx900 -o - %s | FileCheck --check-prefixes=CHECK,ISEL %s -; RUN: llc -stop-after=dead-mi-elimination -mtriple=amdgcn-- -mcpu=gfx900 -o - %s | FileCheck --check-prefixes=CHECK,DEADMI %s -; RUN: llc -global-isel -stop-after=irtranslator -mtriple=amdgcn-- -mcpu=gfx900 -o - %s | FileCheck %s --check-prefixes=CHECK,GISEL +; RUN: llc -stop-after=amdgpu-isel -mtriple=amdgpu9.00-- -o - %s | FileCheck --check-prefixes=CHECK,ISEL %s +; RUN: llc -stop-after=dead-mi-elimination -mtriple=amdgpu9.00-- -o - %s | FileCheck --check-prefixes=CHECK,DEADMI %s +; RUN: llc -global-isel -stop-after=irtranslator -mtriple=amdgpu9.00-- -o - %s | FileCheck %s --check-prefixes=CHECK,GISEL ; CHECK-LABEL: name: basic_call ; CHECK: [[TOKEN:%[0-9]+]]{{[^ ]*}} = CONVERGENCECTRL_ENTRY diff --git a/llvm/test/CodeGen/AMDGPU/copy-hoist-no-spills.ll b/llvm/test/CodeGen/AMDGPU/copy-hoist-no-spills.ll index 5f0c5106a675b..3fecc516f2b13 100644 --- a/llvm/test/CodeGen/AMDGPU/copy-hoist-no-spills.ll +++ b/llvm/test/CodeGen/AMDGPU/copy-hoist-no-spills.ll @@ -1,5 +1,5 @@ ; NOTE: There must be no spill reload inside the loop starting with LBB0_1: -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 < %s | FileCheck %s +; RUN: llc -mtriple=amdgpu9.08-amd-amdhsa < %s | FileCheck %s define amdgpu_kernel void @foo(ptr %.sroa.1.0.copyload, ptr %0, ptr %1, ptr %2, ptr %3, ptr %4, ptr %5, ptr %6, ptr %7, ptr %8, ptr %9, ptr %10, ptr %11, ptr %12, ptr %13, ptr %14, ptr %15, ptr %16, ptr %17, ptr %18, ptr %19, ptr %20, ptr %21, ptr %22, ptr %23, ptr %24, ptr %25, ptr %26, ptr %27, ptr %28, ptr %29, ptr %30, ptr %31, ptr %32, ptr %33, double %34, double %35, double %36, float %37, float %38, float %39, float %40, ptr %41) { ; CHECK-LABEL: foo: diff --git a/llvm/test/CodeGen/AMDGPU/copy-illegal-type.ll b/llvm/test/CodeGen/AMDGPU/copy-illegal-type.ll index 7a576b1c58c55..8c2e0fa61d52e 100644 --- a/llvm/test/CodeGen/AMDGPU/copy-illegal-type.ll +++ b/llvm/test/CodeGen/AMDGPU/copy-illegal-type.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=SI %s -; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global -amdgpu-sdwa-peephole=0 < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=VI %s +; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=SI %s +; RUN: llc -mtriple=amdgpu8.02 -mattr=-flat-for-global -amdgpu-sdwa-peephole=0 < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=VI %s declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone declare i32 @llvm.amdgcn.workitem.id.y() nounwind readnone diff --git a/llvm/test/CodeGen/AMDGPU/copy-overlap-sgpr-kill.mir b/llvm/test/CodeGen/AMDGPU/copy-overlap-sgpr-kill.mir index 004830397c98b..41fce7e3a64bd 100644 --- a/llvm/test/CodeGen/AMDGPU/copy-overlap-sgpr-kill.mir +++ b/llvm/test/CodeGen/AMDGPU/copy-overlap-sgpr-kill.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -verify-machineinstrs -run-pass=postrapseudos -o - %s | FileCheck %s +# RUN: llc -mtriple=amdgpu9.06-amd-amdhsa -verify-machineinstrs -run-pass=postrapseudos -o - %s | FileCheck %s # Don't set a kill of the super register on the last instruction with # an overlapping copy. This would kill part of the values in the diff --git a/llvm/test/CodeGen/AMDGPU/copy-overlap-vgpr-kill.mir b/llvm/test/CodeGen/AMDGPU/copy-overlap-vgpr-kill.mir index 5286c6d34cf44..e4f1509f7770b 100644 --- a/llvm/test/CodeGen/AMDGPU/copy-overlap-vgpr-kill.mir +++ b/llvm/test/CodeGen/AMDGPU/copy-overlap-vgpr-kill.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -verify-machineinstrs -run-pass=postrapseudos -o - %s | FileCheck %s +# RUN: llc -mtriple=amdgpu9.06-amd-amdhsa -verify-machineinstrs -run-pass=postrapseudos -o - %s | FileCheck %s # Don't set a kill of the super register on the last instruction with # an overlapping copy. This would kill part of the values in the diff --git a/llvm/test/CodeGen/AMDGPU/copy-phys-reg-implicit-operand-kills-subregs.mir b/llvm/test/CodeGen/AMDGPU/copy-phys-reg-implicit-operand-kills-subregs.mir index 06a5cbbcb5238..ea1c308b7af02 100644 --- a/llvm/test/CodeGen/AMDGPU/copy-phys-reg-implicit-operand-kills-subregs.mir +++ b/llvm/test/CodeGen/AMDGPU/copy-phys-reg-implicit-operand-kills-subregs.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1031 -verify-machineinstrs -run-pass=postrapseudos -o - %s | FileCheck %s +# RUN: llc -mtriple=amdgpu10.31-amd-amdhsa -verify-machineinstrs -run-pass=postrapseudos -o - %s | FileCheck %s # The copy has an implicit def of a superregister which overlaps the # register it defines. We cannot preserve the kill on the tuple def diff --git a/llvm/test/CodeGen/AMDGPU/copy-to-reg-frameindex.ll b/llvm/test/CodeGen/AMDGPU/copy-to-reg-frameindex.ll index a13f3513c660e..f7e9b8724b682 100644 --- a/llvm/test/CodeGen/AMDGPU/copy-to-reg-frameindex.ll +++ b/llvm/test/CodeGen/AMDGPU/copy-to-reg-frameindex.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx90a | FileCheck %s +; RUN: llc < %s -mtriple=amdgpu9.0a | FileCheck %s define amdgpu_kernel void @copy_to_reg_frameindex(ptr addrspace(1) %out, i32 %a, i32 %b, i32 %c) { ; CHECK-LABEL: copy_to_reg_frameindex: diff --git a/llvm/test/CodeGen/AMDGPU/copy-to-reg-scc-clobber.ll b/llvm/test/CodeGen/AMDGPU/copy-to-reg-scc-clobber.ll index ac9a279491668..122c0f7068f4f 100644 --- a/llvm/test/CodeGen/AMDGPU/copy-to-reg-scc-clobber.ll +++ b/llvm/test/CodeGen/AMDGPU/copy-to-reg-scc-clobber.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=amdgcn -mcpu=gfx90a -O3 -pre-RA-sched=source < %s | FileCheck -check-prefix=RRLIST %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx90a -O3 -pre-RA-sched=fast < %s | FileCheck -check-prefix=FAST %s +; RUN: llc -mtriple=amdgpu9.0a -O3 -pre-RA-sched=source < %s | FileCheck -check-prefix=RRLIST %s +; RUN: llc -mtriple=amdgpu9.0a -O3 -pre-RA-sched=fast < %s | FileCheck -check-prefix=FAST %s define protected amdgpu_kernel void @sccClobber(ptr addrspace(1) %a, ptr addrspace(1) %b, ptr addrspace(1) %e, ptr addrspace(1) %f, ptr addrspace(1) %pout.coerce) { diff --git a/llvm/test/CodeGen/AMDGPU/copy-to-reg.ll b/llvm/test/CodeGen/AMDGPU/copy-to-reg.ll index f5223d5553c6a..6cc2af673f017 100644 --- a/llvm/test/CodeGen/AMDGPU/copy-to-reg.ll +++ b/llvm/test/CodeGen/AMDGPU/copy-to-reg.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 -; RUN: llc -mtriple=amdgcn -mcpu=hawaii -disable-promote-alloca-to-vector -disable-promote-alloca-to-lds < %s | FileCheck -check-prefix=GFX7 %s -; RUN: llc -mtriple=amdgcn -mcpu=tonga -disable-promote-alloca-to-vector -disable-promote-alloca-to-lds < %s | FileCheck -check-prefix=GFX8 %s +; RUN: llc -mtriple=amdgpu7.01 -... [truncated] `````````` </details> https://github.com/llvm/llvm-project/pull/208894 _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
