llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-backend-amdgpu Author: Matt Arsenault (arsenm) <details> <summary>Changes</summary> Mechanically migrate the command-line target spelling on llc/opt RUN lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the redundant -mcpu. Co-Authored-By: Claude <noreply@<!-- -->anthropic.com> (Claude-Opus-4.8) --- Patch is 139.50 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/208897.diff 100 Files Affected: - (modified) llvm/test/CodeGen/AMDGPU/fmax3-maximumnum.ll (+18-18) - (modified) llvm/test/CodeGen/AMDGPU/fmax3.f64.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/fmax3.ll (+11-11) - (modified) llvm/test/CodeGen/AMDGPU/fmax_legacy.f64.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/fmax_legacy.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/fmaximum.ll (+10-10) - (modified) llvm/test/CodeGen/AMDGPU/fmaximum3.ll (+6-6) - (modified) llvm/test/CodeGen/AMDGPU/fmaximum3.v2f16.ll (+4-4) - (modified) llvm/test/CodeGen/AMDGPU/fmaxnum.f64.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/fmaxnum.ll (+6-6) - (modified) llvm/test/CodeGen/AMDGPU/fmed3-cast-combine.ll (+6-6) - (modified) llvm/test/CodeGen/AMDGPU/fmed3.bf16.ll (+5-5) - (modified) llvm/test/CodeGen/AMDGPU/fmed3.ll (+10-10) - (modified) llvm/test/CodeGen/AMDGPU/fmin3-minimumnum.ll (+18-18) - (modified) llvm/test/CodeGen/AMDGPU/fmin3.ll (+11-11) - (modified) llvm/test/CodeGen/AMDGPU/fmin_fmax_legacy.amdgcn.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/fmin_legacy.f16.ll (+5-5) - (modified) llvm/test/CodeGen/AMDGPU/fmin_legacy.f64.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/fmin_legacy.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/fminimum.ll (+10-10) - (modified) llvm/test/CodeGen/AMDGPU/fminimum3.ll (+6-6) - (modified) llvm/test/CodeGen/AMDGPU/fminimum3.v2f16.ll (+4-4) - (modified) llvm/test/CodeGen/AMDGPU/fminnum.f64.ll (+3-3) - (modified) llvm/test/CodeGen/AMDGPU/fminnum.ll (+6-6) - (modified) llvm/test/CodeGen/AMDGPU/fmul-2-combine-multi-use.ll (+8-8) - (modified) llvm/test/CodeGen/AMDGPU/fmul-to-ldexp.ll (+8-8) - (modified) llvm/test/CodeGen/AMDGPU/fmul.f16.ll (+5-5) - (modified) llvm/test/CodeGen/AMDGPU/fmul.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/fmul64.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/fmuladd.f16.ll (+16-16) - (modified) llvm/test/CodeGen/AMDGPU/fmuladd.f64.ll (+6-6) - (modified) llvm/test/CodeGen/AMDGPU/fmuladd.v2f16.ll (+4-4) - (modified) llvm/test/CodeGen/AMDGPU/fncall-implicitdef.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/fnearbyint.ll (+5-5) - (modified) llvm/test/CodeGen/AMDGPU/fneg-combines-gfx1200.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/fneg-combines.f16.ll (+4-4) - (modified) llvm/test/CodeGen/AMDGPU/fneg-combines.legal.f16.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/fneg-combines.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/fneg-combines.si.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/fneg-fabs-divergence-driven-isel.ll (+4-4) - (modified) llvm/test/CodeGen/AMDGPU/fneg-fabs-v2f32.ll (+6-6) - (modified) llvm/test/CodeGen/AMDGPU/fneg-fabs.bf16.ll (+5-5) - (modified) llvm/test/CodeGen/AMDGPU/fneg-fabs.f16.ll (+5-5) - (modified) llvm/test/CodeGen/AMDGPU/fneg-fabs.f64.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/fneg-fabs.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/fneg-fold-legalize-dag-increase-insts.ll (+3-3) - (modified) llvm/test/CodeGen/AMDGPU/fneg-modifier-casting.ll (+4-4) - (modified) llvm/test/CodeGen/AMDGPU/fneg.bf16.ll (+5-5) - (modified) llvm/test/CodeGen/AMDGPU/fneg.f16.ll (+5-5) - (modified) llvm/test/CodeGen/AMDGPU/fneg.f64.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/fneg.ll (+4-4) - (modified) llvm/test/CodeGen/AMDGPU/fold-agpr-phis.mir (+3-3) - (modified) llvm/test/CodeGen/AMDGPU/fold-cndmask-wave32.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/fold-commute-sgpr.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/fold-fabs.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/fold-fmaak-bug.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/fold-freeze-fmul-to-fma.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/fold-gep-offset.ll (+14-14) - (modified) llvm/test/CodeGen/AMDGPU/fold-imm-copy-agpr.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/fold-imm-f16-f32.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/fold-imm-pk64.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/fold-int-pow2-with-fmul-or-fdiv.ll (+4-4) - (modified) llvm/test/CodeGen/AMDGPU/fold-literal-multiple-gfx10.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/fold-multiple-commute.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/fold-multiple.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/fold-omod-crash.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/fold-operands-frame-index-agpr.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/fold-operands-frame-index.gfx10.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/fold-operands-frame-index.mir (+3-3) - (modified) llvm/test/CodeGen/AMDGPU/fold-operands-order.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/fold-operands-remove-m0-redef.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/fold-operands-s-add-copy-to-vgpr.mir (+4-4) - (modified) llvm/test/CodeGen/AMDGPU/fold-operands-scalar-fmac.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/fold-reload-into-exec.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/fold-reload-into-m0.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/fold-restore-undef-use.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/fold-sgpr-copy.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/fold-sgpr-multi-imm.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/fold-short-64-bit-literals.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/fold-vgpr-copy.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/fold-vgpr-phyreg.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/fold-zero-high-bits-clear-kill-flags.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/fold-zero-high-bits-skips-non-reg.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/fold_acc_copy_into_valu.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/folding-of-i32-as-i64.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/force-alwaysinline-lds-global-address.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/force-wait-after-always-gds.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/fp-atomic-to-s_denormmode.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/fp-atomics-gfx1200.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/fp-atomics-gfx942.ll (+3-3) - (modified) llvm/test/CodeGen/AMDGPU/fp-atomics-gfx950.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/fp-classify.ll (+4-4) - (modified) llvm/test/CodeGen/AMDGPU/fp-min-max-buffer-atomics.ll (+12-12) - (modified) llvm/test/CodeGen/AMDGPU/fp_to_sint.f64.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/fp_to_sint.ll (+4-4) - (modified) llvm/test/CodeGen/AMDGPU/fp_to_uint.f64.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/fp_to_uint.ll (+4-4) - (modified) llvm/test/CodeGen/AMDGPU/fp_trunc_store_fp32_to_bf16.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/fp_trunc_store_fp64_to_bf16.ll (+1-1) ``````````diff diff --git a/llvm/test/CodeGen/AMDGPU/fmax3-maximumnum.ll b/llvm/test/CodeGen/AMDGPU/fmax3-maximumnum.ll index 1c4c59855ea98..7792ad7c6b161 100644 --- a/llvm/test/CodeGen/AMDGPU/fmax3-maximumnum.ll +++ b/llvm/test/CodeGen/AMDGPU/fmax3-maximumnum.ll @@ -1,23 +1,23 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 -; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdpal -mcpu=gfx600 < %s | FileCheck -check-prefixes=GFX6,GFX6-SDAG %s -; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdpal -mcpu=gfx700 < %s | FileCheck -check-prefixes=GFX7,GFX7-SDAG %s -; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdpal -mcpu=gfx803 < %s | FileCheck -check-prefixes=GFX8,GFX8-SDAG %s -; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX9,GFX950,GFX9-SDAG,GFX900-SDAG %s -; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdpal -mcpu=gfx950 < %s | FileCheck -check-prefixes=GFX9,GFX950,GFX9-SDAG,GFX950-SDAG %s -; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10,GFX10-SDAG %s -; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdpal -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-SDAG,GFX11-SDAG-TRUE16 %s -; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdpal -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-SDAG,GFX11-SDAG-FAKE16 %s -; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdpal -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG,GFX12-SDAG-TRUE16 %s -; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdpal -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG,GFX12-SDAG-FAKE16 %s +; RUN: llc -global-isel=0 -mtriple=amdgpu6.00-amd-amdpal < %s | FileCheck -check-prefixes=GFX6,GFX6-SDAG %s +; RUN: llc -global-isel=0 -mtriple=amdgpu7.00-amd-amdpal < %s | FileCheck -check-prefixes=GFX7,GFX7-SDAG %s +; RUN: llc -global-isel=0 -mtriple=amdgpu8.03-amd-amdpal < %s | FileCheck -check-prefixes=GFX8,GFX8-SDAG %s +; RUN: llc -global-isel=0 -mtriple=amdgpu9.00-amd-amdpal < %s | FileCheck -check-prefixes=GFX9,GFX950,GFX9-SDAG,GFX900-SDAG %s +; RUN: llc -global-isel=0 -mtriple=amdgpu9.50-amd-amdpal < %s | FileCheck -check-prefixes=GFX9,GFX950,GFX9-SDAG,GFX950-SDAG %s +; RUN: llc -global-isel=0 -mtriple=amdgpu10.10-amd-amdpal < %s | FileCheck -check-prefixes=GFX10,GFX10-SDAG %s +; RUN: llc -global-isel=0 -mtriple=amdgpu11.00-amd-amdpal -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-SDAG,GFX11-SDAG-TRUE16 %s +; RUN: llc -global-isel=0 -mtriple=amdgpu11.00-amd-amdpal -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-SDAG,GFX11-SDAG-FAKE16 %s +; RUN: llc -global-isel=0 -mtriple=amdgpu12.00-amd-amdpal -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG,GFX12-SDAG-TRUE16 %s +; RUN: llc -global-isel=0 -mtriple=amdgpu12.00-amd-amdpal -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG,GFX12-SDAG-FAKE16 %s -; xUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx600 < %s | FileCheck -check-prefixes=GFX6,GFX6-GISEL %s -; xUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx700 < %s | FileCheck -check-prefixes=GFX7,GFX7-GISEL %s -; xUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx803 < %s | FileCheck -check-prefixes=GFX8,GFX8-GISEL %s -; xUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX9,GFX950,GFX9-GISEL,GFX900-GISEL %s -; xUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx950 < %s | FileCheck -check-prefixes=GFX9,GFX950,GFX9-GISEL,GFX950-GISEL %s -; xUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10,GFX10-GISEL %s -; xUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL %s -; xUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL %s +; xUN: llc -global-isel -mtriple=amdgpu6.00-amd-amdpal < %s | FileCheck -check-prefixes=GFX6,GFX6-GISEL %s +; xUN: llc -global-isel -mtriple=amdgpu7.00-amd-amdpal < %s | FileCheck -check-prefixes=GFX7,GFX7-GISEL %s +; xUN: llc -global-isel -mtriple=amdgpu8.03-amd-amdpal < %s | FileCheck -check-prefixes=GFX8,GFX8-GISEL %s +; xUN: llc -global-isel -mtriple=amdgpu9.00-amd-amdpal < %s | FileCheck -check-prefixes=GFX9,GFX950,GFX9-GISEL,GFX900-GISEL %s +; xUN: llc -global-isel -mtriple=amdgpu9.50-amd-amdpal < %s | FileCheck -check-prefixes=GFX9,GFX950,GFX9-GISEL,GFX950-GISEL %s +; xUN: llc -global-isel -mtriple=amdgpu10.10-amd-amdpal < %s | FileCheck -check-prefixes=GFX10,GFX10-GISEL %s +; xUN: llc -global-isel -mtriple=amdgpu11.00-amd-amdpal -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL %s +; xUN: llc -global-isel -mtriple=amdgpu12.00-amd-amdpal -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL %s define float @v_max3_f32_maximumnum_maximumnum__v_v_v_0(float %a, float %b, float %c) { ; GFX6-LABEL: v_max3_f32_maximumnum_maximumnum__v_v_v_0: diff --git a/llvm/test/CodeGen/AMDGPU/fmax3.f64.ll b/llvm/test/CodeGen/AMDGPU/fmax3.f64.ll index c24b773f0d7ca..73a9c652caf87 100644 --- a/llvm/test/CodeGen/AMDGPU/fmax3.f64.ll +++ b/llvm/test/CodeGen/AMDGPU/fmax3.f64.ll @@ -1,5 +1,5 @@ -; RUN: llc -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefix=SI %s -; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -check-prefix=SI %s +; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck -check-prefix=SI %s +; RUN: llc -mtriple=amdgpu8.02 -mattr=-flat-for-global < %s | FileCheck -check-prefix=SI %s declare double @llvm.maxnum.f64(double, double) nounwind readnone diff --git a/llvm/test/CodeGen/AMDGPU/fmax3.ll b/llvm/test/CodeGen/AMDGPU/fmax3.ll index e539a608d0618..65c466f71140f 100644 --- a/llvm/test/CodeGen/AMDGPU/fmax3.ll +++ b/llvm/test/CodeGen/AMDGPU/fmax3.ll @@ -1,15 +1,15 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -enable-var-scope -check-prefixes=SI %s -; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -enable-var-scope -check-prefixes=VI %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -mattr=-flat-for-global < %s | FileCheck -enable-var-scope -check-prefixes=GFX9 %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -mattr=-flat-for-global < %s | FileCheck -enable-var-scope -check-prefixes=GFX11,GFX11-TRUE16 %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -mattr=-flat-for-global < %s | FileCheck -enable-var-scope -check-prefixes=GFX11,GFX11-FAKE16 %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx1170 -mattr=+real-true16 -mattr=-flat-for-global < %s | FileCheck -enable-var-scope -check-prefixes=GFX1170,GFX1170-TRUE16 %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx1170 -mattr=-real-true16 -mattr=-flat-for-global < %s | FileCheck -enable-var-scope -check-prefixes=GFX1170,GFX1170-FAKE16 %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 -mattr=-flat-for-global < %s | FileCheck -enable-var-scope -check-prefixes=GFX12,GFX12-TRUE16 %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 -mattr=-flat-for-global < %s | FileCheck -enable-var-scope -check-prefixes=GFX12,GFX12-FAKE16 %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx1250 -mattr=+real-true16 -mattr=-flat-for-global < %s | FileCheck -enable-var-scope -check-prefixes=GFX1250,GFX1250-TRUE16 %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx1250 -mattr=-real-true16 -mattr=-flat-for-global < %s | FileCheck -enable-var-scope -check-prefixes=GFX1250,GFX1250-FAKE16 %s +; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck -enable-var-scope -check-prefixes=SI %s +; RUN: llc -mtriple=amdgpu8.02 -mattr=-flat-for-global < %s | FileCheck -enable-var-scope -check-prefixes=VI %s +; RUN: llc -mtriple=amdgpu9.00 -mattr=-flat-for-global < %s | FileCheck -enable-var-scope -check-prefixes=GFX9 %s +; RUN: llc -mtriple=amdgpu11.00 -mattr=+real-true16 -mattr=-flat-for-global < %s | FileCheck -enable-var-scope -check-prefixes=GFX11,GFX11-TRUE16 %s +; RUN: llc -mtriple=amdgpu11.00 -mattr=-real-true16 -mattr=-flat-for-global < %s | FileCheck -enable-var-scope -check-prefixes=GFX11,GFX11-FAKE16 %s +; RUN: llc -mtriple=amdgpu11.70 -mattr=+real-true16 -mattr=-flat-for-global < %s | FileCheck -enable-var-scope -check-prefixes=GFX1170,GFX1170-TRUE16 %s +; RUN: llc -mtriple=amdgpu11.70 -mattr=-real-true16 -mattr=-flat-for-global < %s | FileCheck -enable-var-scope -check-prefixes=GFX1170,GFX1170-FAKE16 %s +; RUN: llc -mtriple=amdgpu12.00 -mattr=+real-true16 -mattr=-flat-for-global < %s | FileCheck -enable-var-scope -check-prefixes=GFX12,GFX12-TRUE16 %s +; RUN: llc -mtriple=amdgpu12.00 -mattr=-real-true16 -mattr=-flat-for-global < %s | FileCheck -enable-var-scope -check-prefixes=GFX12,GFX12-FAKE16 %s +; RUN: llc -mtriple=amdgpu12.50 -mattr=+real-true16 -mattr=-flat-for-global < %s | FileCheck -enable-var-scope -check-prefixes=GFX1250,GFX1250-TRUE16 %s +; RUN: llc -mtriple=amdgpu12.50 -mattr=-real-true16 -mattr=-flat-for-global < %s | FileCheck -enable-var-scope -check-prefixes=GFX1250,GFX1250-FAKE16 %s define amdgpu_kernel void @test_fmax3_olt_0_f32(ptr addrspace(1) %out, ptr addrspace(1) %aptr, ptr addrspace(1) %bptr, ptr addrspace(1) %cptr) #0 { ; SI-LABEL: test_fmax3_olt_0_f32: diff --git a/llvm/test/CodeGen/AMDGPU/fmax_legacy.f64.ll b/llvm/test/CodeGen/AMDGPU/fmax_legacy.f64.ll index c9b61e40c79e0..a97baa94c73e5 100644 --- a/llvm/test/CodeGen/AMDGPU/fmax_legacy.f64.ll +++ b/llvm/test/CodeGen/AMDGPU/fmax_legacy.f64.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=amdgcn-- -mcpu=tahiti < %s | FileCheck -check-prefix=SI %s -; RUN: llc -mtriple=amdgcn-- -mcpu=fiji < %s | FileCheck -check-prefix=VI %s +; RUN: llc -mtriple=amdgpu6.00-- < %s | FileCheck -check-prefix=SI %s +; RUN: llc -mtriple=amdgpu8.03-- < %s | FileCheck -check-prefix=VI %s ; Make sure we don't try to form FMAX_LEGACY nodes with f64 diff --git a/llvm/test/CodeGen/AMDGPU/fmax_legacy.ll b/llvm/test/CodeGen/AMDGPU/fmax_legacy.ll index b8442b89099ab..fd8116a08969d 100644 --- a/llvm/test/CodeGen/AMDGPU/fmax_legacy.ll +++ b/llvm/test/CodeGen/AMDGPU/fmax_legacy.ll @@ -1,6 +1,6 @@ -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -enable-var-scope -check-prefixes=SI,GCN,FUNC %s +; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck -enable-var-scope -check-prefixes=SI,GCN,FUNC %s -; RUN: llc -mtriple=amdgcn -mcpu=fiji < %s | FileCheck -enable-var-scope -check-prefixes=VI,GCN,FUNC %s +; RUN: llc -mtriple=amdgpu8.03 < %s | FileCheck -enable-var-scope -check-prefixes=VI,GCN,FUNC %s ; RUN: llc -mtriple=r600 -mcpu=redwood < %s | FileCheck -enable-var-scope --check-prefixes=EG,FUNC %s diff --git a/llvm/test/CodeGen/AMDGPU/fmaximum.ll b/llvm/test/CodeGen/AMDGPU/fmaximum.ll index d0e3ce4f1a430..64502fc2b3c11 100644 --- a/llvm/test/CodeGen/AMDGPU/fmaximum.ll +++ b/llvm/test/CodeGen/AMDGPU/fmaximum.ll @@ -1,14 +1,14 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -enable-var-scope -check-prefixes=GFX9,GFX9-SDAG %s -; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -enable-var-scope -check-prefixes=GFX9,GFX9-GISEL %s -; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1170 -mattr=+real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GFX1170,GFX1170-SDAG,GFX1170-SDAG-TRUE16 %s -; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1170 -mattr=-real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GFX1170,GFX1170-SDAG,GFX1170-SDAG-FAKE16 %s -; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1170 -mattr=+real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GFX1170,GFX1170-GISEL,GFX1170-GISEL-TRUE16 %s -; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1170 -mattr=-real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GFX1170,GFX1170-GISEL,GFX1170-GISEL-FAKE16 %s -; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GFX12,GFX12-SDAG,GFX12-SDAG-TRUE16 %s -; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GFX12,GFX12-SDAG,GFX12-SDAG-FAKE16 %s -; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-TRUE16 %s -; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-FAKE16 %s +; RUN: llc -global-isel=0 -mtriple=amdgpu9.00 < %s | FileCheck -enable-var-scope -check-prefixes=GFX9,GFX9-SDAG %s +; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgpu9.00 < %s | FileCheck -enable-var-scope -check-prefixes=GFX9,GFX9-GISEL %s +; RUN: llc -global-isel=0 -mtriple=amdgpu11.70 -mattr=+real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GFX1170,GFX1170-SDAG,GFX1170-SDAG-TRUE16 %s +; RUN: llc -global-isel=0 -mtriple=amdgpu11.70 -mattr=-real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GFX1170,GFX1170-SDAG,GFX1170-SDAG-FAKE16 %s +; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgpu11.70 -mattr=+real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GFX1170,GFX1170-GISEL,GFX1170-GISEL-TRUE16 %s +; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgpu11.70 -mattr=-real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GFX1170,GFX1170-GISEL,GFX1170-GISEL-FAKE16 %s +; RUN: llc -global-isel=0 -mtriple=amdgpu12.00 -mattr=+real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GFX12,GFX12-SDAG,GFX12-SDAG-TRUE16 %s +; RUN: llc -global-isel=0 -mtriple=amdgpu12.00 -mattr=-real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GFX12,GFX12-SDAG,GFX12-SDAG-FAKE16 %s +; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgpu12.00 -mattr=+real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-TRUE16 %s +; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgpu12.00 -mattr=-real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-FAKE16 %s define amdgpu_ps float @test_fmaximum_f32_vv(float %a, float %b) { ; GFX9-LABEL: test_fmaximum_f32_vv: diff --git a/llvm/test/CodeGen/AMDGPU/fmaximum3.ll b/llvm/test/CodeGen/AMDGPU/fmaximum3.ll index bdbd980cc166b..c534f89fd3d7e 100644 --- a/llvm/test/CodeGen/AMDGPU/fmaximum3.ll +++ b/llvm/test/CodeGen/AMDGPU/fmaximum3.ll @@ -1,10 +1,10 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 -; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-TRUE16 %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-FAKE16 %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx1170 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX1170,GFX1170-TRUE16 %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx1170 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX1170,GFX1170-FAKE16 %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx942 < %s | FileCheck -check-prefixes=GFX9,GFX942 %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx950 < %s | FileCheck -check-prefixes=GFX9,GFX950 %s +; RUN: llc -mtriple=amdgpu12.00 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-TRUE16 %s +; RUN: llc -mtriple=amdgpu12.00 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-FAKE16 %s +; RUN: llc -mtriple=amdgpu11.70 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX1170,GFX1170-TRUE16 %s +; RUN: llc -mtriple=amdgpu11.70 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX1170,GFX1170-FAKE16 %s +; RUN: llc -mtriple=amdgpu9.42 < %s | FileCheck -check-prefixes=GFX9,GFX942 %s +; RUN: llc -mtriple=amdgpu9.50 < %s | FileCheck -check-prefixes=GFX9,GFX950 %s define float @v_fmaximum3_f32(float %a, float %b, float %c) { ; GFX12-LABEL: v_fmaximum3_f32: diff --git a/llvm/test/CodeGen/AMDGPU/fmaximum3.v2f16.ll b/llvm/test/CodeGen/AMDGPU/fmaximum3.v2f16.ll index c9b3ff79366b5..5e95db262203d 100644 --- a/llvm/test/CodeGen/AMDGPU/fmaximum3.v2f16.ll +++ b/llvm/test/CodeGen/AMDGPU/fmaximum3.v2f16.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 -; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1250 -mattr=-real-true16 < %s | FileCheck --check-prefixes=GFX1250,GFX1250-SDAG,GFX1250-SDAG-FAKE16 %s -; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1250 -mattr=-real-true16 < %s | FileCheck --check-prefixes=GFX1250,GFX1250-GISEL,GFX1250-GISEL-FAKE16 %s -; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1250 -mattr=+real-true16 < %s | FileCheck --check-prefixes=GFX1250,GFX1250-SDAG,GFX1250-SDAG-REAL16 %s -; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1250 -mattr=+real-true16 < %s | FileCheck --check-prefixes=GFX1250,GFX1250-GISEL,GFX1250-GISEL-REAL16 %s +; RUN: llc -global-isel=0 -mtriple=amdgpu12.50 -mattr=-real-true16 < %s | FileCheck --check-prefixes=GFX1250,GFX1250-SDAG,GFX1250-SDAG-FAKE16 %s +; RUN: llc -global-isel=1 -mtriple=amdgpu12.50 -mattr=-real-true16 < %s | FileCheck --check-prefixes=GFX1250,GFX1250-GISEL,GFX1250-GISEL-FAKE16 %s +; RUN: llc -global-isel=0 -mtriple=amdgpu12.50 -mattr=+real-true16 < %s | FileCheck --check-prefixes=GFX1250,GFX1250-SDAG,GFX1250-SDAG-REAL16 %s +; RUN: llc -global-isel=1 -mtriple=amdgpu12.50 -mattr=+real-true16 < %s | FileCheck --check-prefixes=GFX1250,GFX1250-GISEL,GFX1250-GISEL-REAL16 %s define <2 x half> @fmaximum3_v2f16(<2 x half> %a, <2 x half> %b, <2 x half> %c) { ; GFX1250-SDAG-LABEL: fmaximum3_v2f16: diff --git a/llvm/test/CodeGen/AMDGPU/fmaxnum.f64.ll b/llvm/test/CodeGen/AMDGPU/fmaxnum.f64.ll index 1c426bf7edbe8..8dfd60285c6e3 100644 --- a/llvm/test/CodeGen/AMDGPU/fmaxnum.f64.ll +++ b/llvm/test/CodeGen/AMDGPU/fmaxnum.f64.ll @@ -1,5 +1,5 @@ -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s -; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s +; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s +; RUN: llc -mtriple=amdgpu8.02 -mattr=-flat-for-global < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s declare double @llvm.maxnum.f64(double, double) #0 declare <2 x double> @llvm.maxnum.v2f64(<2 x double>, <2 x double>) #0 diff --git a/llvm/test/CodeGen/AMDGPU/fmaxnum.ll b/llvm/test/CodeGen/AMDGPU/fmaxnum.ll index c7548cd331be0..fc3ee5b731322 100644 --- a/llvm/test/CodeGen/AMDGPU/fmaxnum.ll +++ b/llvm/test/CodeGen/AMDGPU/fmaxnum.ll @@ -1,10 +1,10 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 -; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -enable-var-scope -check-prefixes=GFX8,GFX8-SDAG %s -; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -enable-var-scope -check-prefixes=GFX8,GFX8-GISEL %s -; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx908 -mattr=-flat-for-global < %s | FileCheck -enable-var-scope -check-prefixes=GFX9,GFX9-SDAG %s -; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx908 -mattr=-flat-for-global < %s | FileCheck -enable-var-scope -check-prefixes=GFX9,GFX9-GISEL %s -; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-flat-for-global < %s | FileCheck -enable-var-scope -check-prefixes=GFX12,GFX12-SDAG %s -; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-flat-for-global < %s | FileCheck -enable-var-scope -check-prefixes=GFX12,GFX12-GISEL %s +; RUN: llc -global-isel=0 -mtriple=amdgpu8.02 -mattr=-flat-for-global < %s | FileCheck -enable-var-scope -check-prefixes=GFX8,GFX8-SDAG %s +; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgpu8.02 -mattr=-flat-for-global < %s | FileCheck -enable-var-scope -check-p... [truncated] `````````` </details> https://github.com/llvm/llvm-project/pull/208897 _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
