llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-backend-amdgpu Author: Matt Arsenault (arsenm) <details> <summary>Changes</summary> Mechanically migrate the command-line target spelling on llc/opt RUN lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the redundant -mcpu. Co-Authored-By: Claude <noreply@<!-- -->anthropic.com> (Claude-Opus-4.8) --- Patch is 101.71 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/209119.diff 100 Files Affected: - (modified) llvm/test/CodeGen/AMDGPU/idiv-licm.ll (+3-3) - (modified) llvm/test/CodeGen/AMDGPU/idot2-test.ll (+4-4) - (modified) llvm/test/CodeGen/AMDGPU/idot2.ll (+6-6) - (modified) llvm/test/CodeGen/AMDGPU/idot4-test.ll (+5-5) - (modified) llvm/test/CodeGen/AMDGPU/idot4s.ll (+8-8) - (modified) llvm/test/CodeGen/AMDGPU/idot4u.ll (+8-8) - (modified) llvm/test/CodeGen/AMDGPU/idot8s.ll (+8-8) - (modified) llvm/test/CodeGen/AMDGPU/idot8u.ll (+6-6) - (modified) llvm/test/CodeGen/AMDGPU/iglp-no-clobber.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/iglp.opt.reentry.ll (+3-3) - (modified) llvm/test/CodeGen/AMDGPU/illegal-eviction-assert.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/image-load-d16-tfe.ll (+4-4) - (modified) llvm/test/CodeGen/AMDGPU/image-sample-waterfall.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/image-schedule.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/img-nouse-adjust.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/imm.ll (+3-3) - (modified) llvm/test/CodeGen/AMDGPU/imm16.ll (+5-5) - (modified) llvm/test/CodeGen/AMDGPU/immv216.ll (+5-5) - (modified) llvm/test/CodeGen/AMDGPU/implicit-arg-block-count.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/implicit-arg-v5-opt.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/implicit-kernarg-backend-usage.ll (+6-6) - (modified) llvm/test/CodeGen/AMDGPU/implicit-kernel-argument-alignment.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/implicitarg-offset-attributes.ll (+3-3) - (modified) llvm/test/CodeGen/AMDGPU/indirect-addressing-si-gfx9.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll (+6-6) - (modified) llvm/test/CodeGen/AMDGPU/indirect-addressing-term.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/indirect-call-known-callees.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/indirect-call-set-from-other-function.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/indirect-private-64.ll (+5-5) - (modified) llvm/test/CodeGen/AMDGPU/indirect-reg-read-imm-idx.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/indirect-reg-read-imm-idx.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/infer-addrpace-pipeline.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/infer-addrspace-flat-atomic.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/infer-uniform-load-shader.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/infinite-loop.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/inflate-av-remat-imm.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/inflate-reg-class-vgpr-mfma-to-agpr-negative-tests.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/inflate-reg-class-vgpr-mfma-to-av-with-load-source.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/inflate-reg-class-vgpr-mfma-to-av.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/inflated-reg-class-snippet-copy-use-after-free.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/infloop-subrange-spill-inspect-subrange.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/infloop-subrange-spill.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/init-whole-wave-vgpr-count-large.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/init-whole-wave-vgpr-count-leaf.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/init-whole-wave-vgpr-count-use-inactive.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/init-whole-wave-vgpr-count.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/inline-asm-av-constraint-err.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/inline-asm-av-constraint.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/inline-asm-out-of-bounds-register.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/inline-asm-reserved-regs.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/inline-asm-vgpr-range-unsupported-width.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/inline-asm-vgpr-sgpr-copy.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/inline-asm.i128.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/inline-asm.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/inline-attr.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/inline-constraints.ll (+4-4) - (modified) llvm/test/CodeGen/AMDGPU/inline-maxbb.ll (+4-4) - (modified) llvm/test/CodeGen/AMDGPU/inlineasm-16-fake16.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/inlineasm-16-true16.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/inlineasm-16.ll (+3-3) - (modified) llvm/test/CodeGen/AMDGPU/inlineasm-illegal-type.ll (+3-3) - (modified) llvm/test/CodeGen/AMDGPU/inlineasm-mismatched-size-error.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/inlineasm-mismatched-size.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/inlineasm-packed.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/inlineasm-v16.ll (+3-3) - (modified) llvm/test/CodeGen/AMDGPU/insert-branch-w32.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/insert-delay-alu-attr.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/insert-delay-alu-bug.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/insert-delay-alu-literal.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/insert-delay-alu-parse.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/insert-delay-alu-wmma-xdl.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/insert-delay-alu.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/insert-handle-flat-vmem-ds.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/insert-skip-from-vcc.mir (+3-3) - (modified) llvm/test/CodeGen/AMDGPU/insert-skips-gfx10.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/insert-skips-gfx12.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/insert-skips-gfx1250.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/insert-skips-gws.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/insert-skips-ignored-insts.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/insert-waitcnts-callee.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/insert-waitcnts-crash.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/insert-waitcnts-fence-soft.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/insert-waitcnts-gfx12-wbinv.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/insert-waitcnts-hang.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/insert-waitcnts-merge.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/insert_subreg.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/insert_vector_elt.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2bf16.ll (+6-6) - (modified) llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll (+5-5) - (modified) llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.subtest-nosaddr.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.subtest-saddr.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/insert_waitcnt_for_precise_memory.ll (+6-6) - (modified) llvm/test/CodeGen/AMDGPU/inserted-wait-states.mir (+4-4) - (modified) llvm/test/CodeGen/AMDGPU/inst-prefetch-hint.ll (+6-6) - (modified) llvm/test/CodeGen/AMDGPU/inst-prefetch-inline-asm.ll (+6-6) - (modified) llvm/test/CodeGen/AMDGPU/integer-canonicalizing-src-modifiers.ll (+4-4) - (modified) llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll (+24-24) - (modified) llvm/test/CodeGen/AMDGPU/integer-select-src-modifiers.ll (+4-4) - (modified) llvm/test/CodeGen/AMDGPU/internalize.ll (+4-4) ``````````diff diff --git a/llvm/test/CodeGen/AMDGPU/idiv-licm.ll b/llvm/test/CodeGen/AMDGPU/idiv-licm.ll index 1f751ecbe6645..aeccbbf6c2d57 100644 --- a/llvm/test/CodeGen/AMDGPU/idiv-licm.ll +++ b/llvm/test/CodeGen/AMDGPU/idiv-licm.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -enable-var-scope -check-prefix=GFX9 %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -enable-var-scope -check-prefix=GFX10 %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -enable-var-scope -check-prefix=GFX11 %s +; RUN: llc -mtriple=amdgpu9.00 < %s | FileCheck -enable-var-scope -check-prefix=GFX9 %s +; RUN: llc -mtriple=amdgpu10.10 < %s | FileCheck -enable-var-scope -check-prefix=GFX10 %s +; RUN: llc -mtriple=amdgpu11.00 < %s | FileCheck -enable-var-scope -check-prefix=GFX11 %s define amdgpu_kernel void @udiv32_invariant_denom(ptr addrspace(1) nocapture %arg, i32 %arg1) { ; GFX9-LABEL: udiv32_invariant_denom: diff --git a/llvm/test/CodeGen/AMDGPU/idot2-test.ll b/llvm/test/CodeGen/AMDGPU/idot2-test.ll index 89876c62c4cd8..6f039ce19dc21 100644 --- a/llvm/test/CodeGen/AMDGPU/idot2-test.ll +++ b/llvm/test/CodeGen/AMDGPU/idot2-test.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=amdgcn -mcpu=gfx906 < %s | FileCheck --check-prefixes=GFX9-DL %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx1011 < %s | FileCheck --check-prefixes=GFX10-DL %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx950 < %s | FileCheck --check-prefixes=GFX950 %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck --check-prefixes=GFX9-NODL %s +; RUN: llc -mtriple=amdgpu9.06 < %s | FileCheck --check-prefixes=GFX9-DL %s +; RUN: llc -mtriple=amdgpu10.11 < %s | FileCheck --check-prefixes=GFX10-DL %s +; RUN: llc -mtriple=amdgpu9.50 < %s | FileCheck --check-prefixes=GFX950 %s +; RUN: llc -mtriple=amdgpu9.00 < %s | FileCheck --check-prefixes=GFX9-NODL %s ; Test dot2 patterns with saturating add (clamp) and without diff --git a/llvm/test/CodeGen/AMDGPU/idot2.ll b/llvm/test/CodeGen/AMDGPU/idot2.ll index de0e3f05e47fa..adf8f3dd31d8f 100644 --- a/llvm/test/CodeGen/AMDGPU/idot2.ll +++ b/llvm/test/CodeGen/AMDGPU/idot2.ll @@ -1,10 +1,10 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=amdgcn -mcpu=gfx700 < %s | FileCheck --check-prefixes=GFX7 %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx803 < %s | FileCheck --check-prefixes=GFX8 %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck --check-prefixes=GFX9-NODL %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx906 < %s | FileCheck --check-prefixes=GFX9-DL %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx1011 < %s | FileCheck --check-prefixes=GFX10-DL %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx1012 < %s | FileCheck --check-prefixes=GFX10-DL %s +; RUN: llc -mtriple=amdgpu7.00 < %s | FileCheck --check-prefixes=GFX7 %s +; RUN: llc -mtriple=amdgpu8.03 < %s | FileCheck --check-prefixes=GFX8 %s +; RUN: llc -mtriple=amdgpu9.00 < %s | FileCheck --check-prefixes=GFX9-NODL %s +; RUN: llc -mtriple=amdgpu9.06 < %s | FileCheck --check-prefixes=GFX9-DL %s +; RUN: llc -mtriple=amdgpu10.11 < %s | FileCheck --check-prefixes=GFX10-DL %s +; RUN: llc -mtriple=amdgpu10.12 < %s | FileCheck --check-prefixes=GFX10-DL %s ; add(mul(S0.x, S1.y), ; add (mul (S0.y, S1.y), S3)) -> v_dot2_{I|U}32_{I|U}16(S1, S2, S3) diff --git a/llvm/test/CodeGen/AMDGPU/idot4-test.ll b/llvm/test/CodeGen/AMDGPU/idot4-test.ll index 01de5507c0db2..7a11389b0393e 100644 --- a/llvm/test/CodeGen/AMDGPU/idot4-test.ll +++ b/llvm/test/CodeGen/AMDGPU/idot4-test.ll @@ -1,9 +1,9 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=amdgcn -mcpu=gfx906 < %s | FileCheck --check-prefixes=GFX9-DL %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx1011 < %s | FileCheck --check-prefixes=GFX10-DL %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx950 < %s | FileCheck --check-prefixes=GFX950 %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck --check-prefixes=GFX9-NODL %s -; RUN: opt -mtriple=amdgcn -mcpu=gfx906 -passes=amdgpu-codegenprepare -S < %s | FileCheck --check-prefixes=OPT %s +; RUN: llc -mtriple=amdgpu9.06 < %s | FileCheck --check-prefixes=GFX9-DL %s +; RUN: llc -mtriple=amdgpu10.11 < %s | FileCheck --check-prefixes=GFX10-DL %s +; RUN: llc -mtriple=amdgpu9.50 < %s | FileCheck --check-prefixes=GFX950 %s +; RUN: llc -mtriple=amdgpu9.00 < %s | FileCheck --check-prefixes=GFX9-NODL %s +; RUN: opt -mtriple=amdgpu9.06 -passes=amdgpu-codegenprepare -S < %s | FileCheck --check-prefixes=OPT %s ; Test dot4 patterns with saturating add (clamp) and without diff --git a/llvm/test/CodeGen/AMDGPU/idot4s.ll b/llvm/test/CodeGen/AMDGPU/idot4s.ll index 917dc51254396..c2037dc42affa 100644 --- a/llvm/test/CodeGen/AMDGPU/idot4s.ll +++ b/llvm/test/CodeGen/AMDGPU/idot4s.ll @@ -1,12 +1,12 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=amdgcn -mcpu=gfx700 < %s | FileCheck -check-prefixes=GFX7 %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx803 < %s | FileCheck -check-prefixes=GFX8 %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX9-NODL %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx906 < %s | FileCheck -check-prefixes=GFX9-DL %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx1011 < %s | FileCheck -check-prefixes=GFX10-DL %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx1012 < %s | FileCheck -check-prefixes=GFX10-DL %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11-DL,GFX11-DL-TRUE16 %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11-DL,GFX11-DL-FAKE16 %s +; RUN: llc -mtriple=amdgpu7.00 < %s | FileCheck -check-prefixes=GFX7 %s +; RUN: llc -mtriple=amdgpu8.03 < %s | FileCheck -check-prefixes=GFX8 %s +; RUN: llc -mtriple=amdgpu9.00 < %s | FileCheck -check-prefixes=GFX9-NODL %s +; RUN: llc -mtriple=amdgpu9.06 < %s | FileCheck -check-prefixes=GFX9-DL %s +; RUN: llc -mtriple=amdgpu10.11 < %s | FileCheck -check-prefixes=GFX10-DL %s +; RUN: llc -mtriple=amdgpu10.12 < %s | FileCheck -check-prefixes=GFX10-DL %s +; RUN: llc -mtriple=amdgpu11.00 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11-DL,GFX11-DL-TRUE16 %s +; RUN: llc -mtriple=amdgpu11.00 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11-DL,GFX11-DL-FAKE16 %s define amdgpu_kernel void @idot4_acc32(ptr addrspace(1) %src1, ; GFX7-LABEL: idot4_acc32: diff --git a/llvm/test/CodeGen/AMDGPU/idot4u.ll b/llvm/test/CodeGen/AMDGPU/idot4u.ll index 199f3c76a17e2..c3603090a3f16 100644 --- a/llvm/test/CodeGen/AMDGPU/idot4u.ll +++ b/llvm/test/CodeGen/AMDGPU/idot4u.ll @@ -1,12 +1,12 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=amdgcn -mcpu=gfx700 < %s | FileCheck -check-prefixes=GFX7 %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx803 < %s | FileCheck -check-prefixes=GFX8 %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX9-NODL %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx906 < %s | FileCheck -check-prefixes=GFX9-DL %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx1011 < %s | FileCheck -check-prefixes=GFX10-DL %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx1012 < %s | FileCheck -check-prefixes=GFX10-DL %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11-DL,GFX11-DL-TRUE16 %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11-DL,GFX11-DL-FAKE16 %s +; RUN: llc -mtriple=amdgpu7.00 < %s | FileCheck -check-prefixes=GFX7 %s +; RUN: llc -mtriple=amdgpu8.03 < %s | FileCheck -check-prefixes=GFX8 %s +; RUN: llc -mtriple=amdgpu9.00 < %s | FileCheck -check-prefixes=GFX9-NODL %s +; RUN: llc -mtriple=amdgpu9.06 < %s | FileCheck -check-prefixes=GFX9-DL %s +; RUN: llc -mtriple=amdgpu10.11 < %s | FileCheck -check-prefixes=GFX10-DL %s +; RUN: llc -mtriple=amdgpu10.12 < %s | FileCheck -check-prefixes=GFX10-DL %s +; RUN: llc -mtriple=amdgpu11.00 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11-DL,GFX11-DL-TRUE16 %s +; RUN: llc -mtriple=amdgpu11.00 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11-DL,GFX11-DL-FAKE16 %s define amdgpu_kernel void @udot4_acc32(ptr addrspace(1) %src1, ; GFX7-LABEL: udot4_acc32: diff --git a/llvm/test/CodeGen/AMDGPU/idot8s.ll b/llvm/test/CodeGen/AMDGPU/idot8s.ll index 51de68f60cd17..684a21f7ac077 100644 --- a/llvm/test/CodeGen/AMDGPU/idot8s.ll +++ b/llvm/test/CodeGen/AMDGPU/idot8s.ll @@ -1,12 +1,12 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=amdgcn -mcpu=gfx700 < %s | FileCheck -check-prefixes=GFX7 %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx803 < %s | FileCheck -check-prefixes=GFX8 %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX9 %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx906 < %s | FileCheck -check-prefixes=GFX9-DL %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx1011 < %s | FileCheck -check-prefixes=GFX10-DL-XNACK %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx1012 < %s | FileCheck -check-prefixes=GFX10-DL-XNACK %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx1030 < %s | FileCheck -check-prefixes=GFX10-DL-NOXNACK %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx1031 < %s | FileCheck -check-prefixes=GFX10-DL-NOXNACK %s +; RUN: llc -mtriple=amdgpu7.00 < %s | FileCheck -check-prefixes=GFX7 %s +; RUN: llc -mtriple=amdgpu8.03 < %s | FileCheck -check-prefixes=GFX8 %s +; RUN: llc -mtriple=amdgpu9.00 < %s | FileCheck -check-prefixes=GFX9 %s +; RUN: llc -mtriple=amdgpu9.06 < %s | FileCheck -check-prefixes=GFX9-DL %s +; RUN: llc -mtriple=amdgpu10.11 < %s | FileCheck -check-prefixes=GFX10-DL-XNACK %s +; RUN: llc -mtriple=amdgpu10.12 < %s | FileCheck -check-prefixes=GFX10-DL-XNACK %s +; RUN: llc -mtriple=amdgpu10.30 < %s | FileCheck -check-prefixes=GFX10-DL-NOXNACK %s +; RUN: llc -mtriple=amdgpu10.31 < %s | FileCheck -check-prefixes=GFX10-DL-NOXNACK %s define amdgpu_kernel void @idot8_acc32(ptr addrspace(1) %src1, ; GFX7-LABEL: idot8_acc32: diff --git a/llvm/test/CodeGen/AMDGPU/idot8u.ll b/llvm/test/CodeGen/AMDGPU/idot8u.ll index 5c9494662111b..646e9508164d4 100644 --- a/llvm/test/CodeGen/AMDGPU/idot8u.ll +++ b/llvm/test/CodeGen/AMDGPU/idot8u.ll @@ -1,10 +1,10 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=amdgcn -mcpu=gfx700 < %s | FileCheck -check-prefixes=GFX7 %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx803 < %s | FileCheck -check-prefixes=GFX8 %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX9 %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx906 < %s | FileCheck -check-prefixes=GFX9-DL %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx1011 < %s | FileCheck -check-prefixes=GFX10-DL %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx1012 < %s | FileCheck -check-prefixes=GFX10-DL %s +; RUN: llc -mtriple=amdgpu7.00 < %s | FileCheck -check-prefixes=GFX7 %s +; RUN: llc -mtriple=amdgpu8.03 < %s | FileCheck -check-prefixes=GFX8 %s +; RUN: llc -mtriple=amdgpu9.00 < %s | FileCheck -check-prefixes=GFX9 %s +; RUN: llc -mtriple=amdgpu9.06 < %s | FileCheck -check-prefixes=GFX9-DL %s +; RUN: llc -mtriple=amdgpu10.11 < %s | FileCheck -check-prefixes=GFX10-DL %s +; RUN: llc -mtriple=amdgpu10.12 < %s | FileCheck -check-prefixes=GFX10-DL %s define amdgpu_kernel void @udot8_acc32(ptr addrspace(1) %src1, ; GFX7-LABEL: udot8_acc32: diff --git a/llvm/test/CodeGen/AMDGPU/iglp-no-clobber.ll b/llvm/test/CodeGen/AMDGPU/iglp-no-clobber.ll index 9843774d55455..20eb38cd8816d 100644 --- a/llvm/test/CodeGen/AMDGPU/iglp-no-clobber.ll +++ b/llvm/test/CodeGen/AMDGPU/iglp-no-clobber.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 < %s | FileCheck %s +; RUN: llc -mtriple=amdgpu9.42-amd-amdhsa < %s | FileCheck %s ; iglp.opt should not be flagged as clobbering the memory operand for the global_load, and we should be able to ; lower into the scalar version (i.e. should not need to lower into vector version with waterfall loop) diff --git a/llvm/test/CodeGen/AMDGPU/iglp.opt.reentry.ll b/llvm/test/CodeGen/AMDGPU/iglp.opt.reentry.ll index a17e02b4226f9..082d6186b8f42 100644 --- a/llvm/test/CodeGen/AMDGPU/iglp.opt.reentry.ll +++ b/llvm/test/CodeGen/AMDGPU/iglp.opt.reentry.ll @@ -1,6 +1,6 @@ -; RUN: llc -mtriple=amdgcn -mcpu=gfx908 -O3 < %s | FileCheck %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx908 -O3 -misched=gcn-iterative-max-occupancy-experimental < %s | FileCheck %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx908 -O3 -misched=gcn-iterative-ilp < %s | FileCheck %s +; RUN: llc -mtriple=amdgpu9.08 -O3 < %s | FileCheck %s +; RUN: llc -mtriple=amdgpu9.08 -O3 -misched=gcn-iterative-max-occupancy-experimental < %s | FileCheck %s +; RUN: llc -mtriple=amdgpu9.08 -O3 -misched=gcn-iterative-ilp < %s | FileCheck %s ; Test should not result in build failure ; CHECK-LABEL: shouldNotReApply diff --git a/llvm/test/CodeGen/AMDGPU/illegal-eviction-assert.mir b/llvm/test/CodeGen/AMDGPU/illegal-eviction-assert.mir index ca2c8928bbc39..7666aa35a4214 100644 --- a/llvm/test/CodeGen/AMDGPU/illegal-eviction-assert.mir +++ b/llvm/test/CodeGen/AMDGPU/illegal-eviction-assert.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: not llc -mtriple=amdgcn -mcpu=gfx900 -start-before=greedy,0 -stop-after=virtregrewriter,2 -o - 2>%t.err %s | FileCheck %s +# RUN: not llc -mtriple=amdgpu9.00 -start-before=greedy,0 -stop-after=virtregrewriter,2 -o - 2>%t.err %s | FileCheck %s # RUN: FileCheck -check-prefix=ERR %s < %t.err # This testcase cannot be compiled. An attempted eviction legality diff --git a/llvm/test/CodeGen/AMDGPU/image-load-d16-tfe.ll b/llvm/test/CodeGen/AMDGPU/image-load-d16-tfe.ll index f9c679d22b094..3b2d08eb26695 100644 --- a/llvm/test/CodeGen/AMDGPU/image-load-d16-tfe.ll +++ b/llvm/test/CodeGen/AMDGPU/image-load-d16-tfe.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s -; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX10 %s -; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 < %s | FileCheck -check-prefix=GFX11 %s -; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tonga < %s | FileCheck -check-prefix=GFX8-UNPACKED %s +; RUN: llc -mtriple=amdgpu9.00-mesa-mesa3d < %s | FileCheck -check-prefix=GFX9 %s +; RUN: llc -mtriple=amdgpu10.10-mesa-mesa3d < %s | FileCheck -check-prefix=GFX10 %s +; RUN: llc -mtriple=amdgpu11.00-mesa-mesa3d < %s | FileCheck -check-prefix=GFX11 %s +; RUN: llc -mtriple=amdgpu8.02-mesa-mesa3d < %s | FileCheck -check-prefix=GFX8-UNPACKED %s define amdgpu_ps void @load_1d_f16_tfe_dmask0(<8 x i32> inreg %rsrc, i32 %s) { ; GFX9-LABEL: load_1d_f16_tfe_dmask0: diff --git a/llvm/test/CodeGen/AMDGPU/image-sample-waterfall.ll b/llvm/test/CodeGen/AMDGPU/image-sample-waterfall.ll index 3206e9593320e..1769e8932ec29 100644 --- a/llvm/test/CodeGen/AMDGPU/image-sample-waterfall.ll +++ b/llvm/test/CodeGen/AMDGPU/image-sample-waterfall.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn -mcpu=gfx906 < %s | FileCheck -check-prefixes=GCN %s +; RUN: llc -mtriple=amdgpu9.06 < %s | FileCheck -check-prefixes=GCN %s declare <4 x float> @llvm.amdgcn.image.gather4.2d.v4f32.f32(i32, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) diff --git a/llvm/test/CodeGen/AMDGPU/image-schedule.ll b/llvm/test/CodeGen/AMDGPU/image-schedule.ll index 9c44b7b34e305..a9188b476e1e0 100644 --- a/llvm/test/CodeGen/AMDGPU/image-schedule.ll +++ b/llvm/test/CodeGen/AMDGPU/image-schedule.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tonga < %s | FileCheck -check-prefixes=GCN %s +; RUN: llc -mtriple=amdgpu8.02--amdpal < %s | FileCheck -check-prefixes=GCN %s ; The first image store and the second image load use the same descriptor and ; the same coordinate. Check that they do not get swapped by the machine diff --git a/llvm/test/CodeGen/AMDGPU/img-nouse-adjust.ll b/llvm/test/CodeGen/AMDGPU/img-nouse-adjust.ll index b2d9a8825f58b..7ddbd771c7f5e 100644 --- a/llvm/test/CodeGen/AMDGPU/img-nouse-adjust.ll +++ b/llvm/test/CodeGen/AMDGPU/img-nouse-adjust.ll @@ -1,5 +1,5 @@ -; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -start-before=amdgpu-isel -stop-after=amdgpu-isel < %s | FileCheck %s --check-prefix=GCN -; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -start-before=amdgpu-isel -stop-after=amdgpu-isel -enable-new-pm < %s | FileCheck %s --check-prefix=GCN +; RUN: llc -mtriple=amdgpu9.00 -start-before=amdgpu-isel -stop-after=amdgpu-isel < %s | FileCheck %s --check-prefix=GCN +; RUN: llc -mtriple=amdgpu9.00 -start-before=amdgpu-isel -stop-after=amdgpu-isel -enable-new-pm < %s | FileCheck %s --check-prefix=GCN ; We're really just checking for no crashes ; The feature we're testing for in AdjustWriteMask leaves the image_load as an instruction just post amdgpu-isel diff --git a/llvm/test/CodeGen/AMDGPU/imm.ll b/llvm/test/CodeGen/AMDGPU/imm.ll index aea3375f0e8bd..8e2ae0f19727d 100644 --- a/llvm/test/CodeGen/AMDGPU/imm.ll +++ b/llvm/test/CodeGen/AMDGPU/imm.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=verde < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI %s -; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI %s -; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx942 -mattr=-flat-for-global < %s | FileCheck -enable-var-scope -check-prefixes=GFX942 %s +; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgpu6.01 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI %s +; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgpu8.02 -mattr=-flat-for-global < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI %s +; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgpu9.42 -mattr=-flat-for-global < %s | FileCheck -enable-var-scope -check-prefixes=GFX942 %s ; Use a 64-bit value with lo bits that can be represented as an inline constant define amdgpu_kernel void @i64_imm_inline_lo(ptr addrspace(1) %out) { diff --git a/llvm/test/CodeGen/AMDGPU/imm16.ll b/llvm/test/CodeGen/AMDGPU/imm16.ll index 0b2e5d540d463..3da0472b9759b 100644 --- a/llvm/test/CodeGen/AMDGPU/imm16.ll +++ b/llvm/test/CodeGen/AMDGPU/imm16.ll @@ -1,9 +1,9 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx1010 -mattr=-flat-for-global -mattr=-flat-for-global -show-mc-encoding < %s | FileCheck -check-prefix=GFX10 %s -; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx1100 -mattr=+real-true16 -mattr=-flat-for-global -mattr=-flat-for-global -show-mc-encoding < %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s -; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx1100 -mattr=-real-true16 -mattr=-flat-for-global -mattr=-flat-for-global -show-mc-encoding < %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s -; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=tonga -mattr=-flat-for-global -mattr=-flat-for-global -show-mc-encoding < %s | FileCheck -check-prefix=VI %s -; RUN: llc -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefix=SI %s +; RUN: llc -mtriple=amdgpu10.10--amdhsa -mattr=-flat-for-global -mattr=-flat-for-global -show-mc-encoding < %s | FileCheck -check-prefix=GFX10 %s +; RUN: llc -mtriple=amdgpu11.00--amdhsa -mattr=+real-true16 -mattr=-flat-for-global -mattr=-flat-for-global -show-mc-encoding < %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s +; RUN: llc -mtriple=amdgpu11.00--amdhsa -mattr=-real-true16 -mattr=-flat-for-global -mattr=-flat-for-global -show-mc-encoding < %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s +; RUN: llc -mtriple=amdgpu8.02--amdhsa -mattr=-flat-for-global -mattr=-flat-for-global -show-mc-encoding < %s | FileCheck -check-prefix=VI %s +; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck -check-prefix=SI %s ; FIXME: Merge into imm.ll diff --git a/llvm/test/CodeGen/AMDGPU/immv216.ll b/llvm/test/CodeGen/AMDGPU/immv216.ll index ae5199a3f7906..dac9e2abcdd86 100644 --- a/llvm/test/CodeGen/AMDGPU/immv216.ll +++ b/llvm/test/Cod... [truncated] `````````` </details> https://github.com/llvm/llvm-project/pull/209119 _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
