https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/209489
Mechanically migrate the command-line target spelling on llc/opt RUN lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the redundant -mcpu. Co-Authored-By: Claude <[email protected]> (Claude-Opus-4.8) >From bf9657628359f60386627acafe47cd461699adee Mon Sep 17 00:00:00 2001 From: Matt Arsenault <[email protected]> Date: Thu, 25 Jun 2026 09:57:30 +0200 Subject: [PATCH] AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (28) Mechanically migrate the command-line target spelling on llc/opt RUN lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the redundant -mcpu. Co-Authored-By: Claude <[email protected]> (Claude-Opus-4.8) --- .../AMDGPU/power-sched-no-instr-sunit.mir | 2 +- llvm/test/CodeGen/AMDGPU/pr51516.mir | 4 +-- .../preload-implicit-kernargs-IR-lowering.ll | 4 +-- .../preload-implicit-kernargs-debug-info.ll | 2 +- .../AMDGPU/preload-implicit-kernargs.ll | 8 +++--- .../AMDGPU/preload-kernargs-IR-lowering.ll | 8 +++--- llvm/test/CodeGen/AMDGPU/preload-kernargs.ll | 6 ++--- llvm/test/CodeGen/AMDGPU/preserve-hi16.ll | 12 ++++----- .../AMDGPU/preserve-only-inactive-lane.mir | 2 +- .../AMDGPU/preserve-wwm-copy-dst-reg.ll | 4 +-- .../CodeGen/AMDGPU/print-pipeline-passes.ll | 16 ++++++------ llvm/test/CodeGen/AMDGPU/printf-defined.ll | 2 +- .../AMDGPU/printf-existing-format-strings.ll | 2 +- .../AMDGPU/private-access-no-objects.ll | 8 +++--- llvm/test/CodeGen/AMDGPU/private-function.ll | 2 +- .../AMDGPU/prologue-epilogue-markers.ll | 4 +-- .../AMDGPU/promote-alloca-addrspacecast.ll | 2 +- .../AMDGPU/promote-alloca-array-aggregate.ll | 2 +- .../AMDGPU/promote-alloca-array-allocation.ll | 2 +- .../AMDGPU/promote-alloca-bitcast-function.ll | 2 +- .../AMDGPU/promote-alloca-calling-conv.ll | 4 +-- .../test/CodeGen/AMDGPU/promote-alloca-cfg.ll | 2 +- .../CodeGen/AMDGPU/promote-alloca-globals.ll | 4 +-- .../promote-alloca-invariant-markers.ll | 2 +- .../CodeGen/AMDGPU/promote-alloca-lifetime.ll | 2 +- .../AMDGPU/promote-alloca-loadstores.ll | 2 +- .../CodeGen/AMDGPU/promote-alloca-max-regs.ll | 6 ++--- .../AMDGPU/promote-alloca-mem-intrinsics.ll | 2 +- .../CodeGen/AMDGPU/promote-alloca-memset.ll | 2 +- .../CodeGen/AMDGPU/promote-alloca-multidim.ll | 2 +- .../AMDGPU/promote-alloca-negative-index.ll | 2 +- .../CodeGen/AMDGPU/promote-alloca-no-opts.ll | 4 +-- .../AMDGPU/promote-alloca-non-byte-sizes.ll | 2 +- .../promote-alloca-non-constant-index.ll | 2 +- .../promote-alloca-padding-size-estimate.ll | 2 +- .../promote-alloca-placeholder-replacement.ll | 2 +- .../AMDGPU/promote-alloca-pointer-array.ll | 2 +- ...promote-alloca-proper-value-replacement.ll | 2 +- .../CodeGen/AMDGPU/promote-alloca-scoring.ll | 2 +- ...promote-alloca-strip-abi-opt-attributes.ll | 2 +- .../CodeGen/AMDGPU/promote-alloca-subvecs.ll | 2 +- .../promote-alloca-to-lds-constantexpr-use.ll | 4 +-- .../AMDGPU/promote-alloca-to-lds-icmp.ll | 4 +-- .../AMDGPU/promote-alloca-to-lds-phi.ll | 2 +- .../AMDGPU/promote-alloca-to-lds-select.ll | 2 +- .../promote-alloca-unhandled-intrinsic.ll | 2 +- .../AMDGPU/promote-alloca-use-after-erase.ll | 2 +- .../AMDGPU/promote-alloca-user-mult.ll | 2 +- ...-alloca-vector-dynamic-idx-bitcasts-llc.ll | 6 ++--- ...mote-alloca-vector-dynamic-idx-bitcasts.ll | 2 +- .../promote-alloca-vector-gep-of-gep.ll | 2 +- .../AMDGPU/promote-alloca-vector-gep.ll | 2 +- .../AMDGPU/promote-alloca-vector-to-vector.ll | 6 ++--- .../AMDGPU/promote-alloca-vgpr-ratio.ll | 6 ++--- .../CodeGen/AMDGPU/promote-alloca-volatile.ll | 2 +- .../promote-constOffset-to-imm-gfx10.mir | 4 +-- .../promote-constOffset-to-imm-gfx12.ll | 2 +- .../promote-constOffset-to-imm-gfx12.mir | 2 +- .../promote-constOffset-to-imm-gfx90a.mir | 2 +- .../AMDGPU/promote-constOffset-to-imm.mir | 4 +-- .../test/CodeGen/AMDGPU/promote-vect3-load.ll | 2 +- .../propagate-attributes-bitcast-function.ll | 4 +-- .../AMDGPU/propagate-flat-work-group-size.ll | 2 +- .../CodeGen/AMDGPU/propagate-waves-per-eu.ll | 2 +- .../CodeGen/AMDGPU/ps-shader-arg-count.ll | 8 +++--- .../AMDGPU/pseudo-scalar-transcendental.ll | 6 ++--- .../AMDGPU/pseudo-scalar-transcendental.mir | 4 +-- llvm/test/CodeGen/AMDGPU/ptr-arg-dbg-value.ll | 2 +- .../AMDGPU/ptr-buffer-alias-scheduling.ll | 4 +-- llvm/test/CodeGen/AMDGPU/ptradd-sdag-mubuf.ll | 2 +- .../AMDGPU/ptradd-sdag-optimizations.ll | 2 +- .../AMDGPU/ptradd-sdag-undef-poison.ll | 2 +- llvm/test/CodeGen/AMDGPU/ptradd-sdag.ll | 10 +++---- llvm/test/CodeGen/AMDGPU/ptrmask.ll | 6 ++--- .../ra-inserted-scalar-instructions.mir | 2 +- ...ut-of-registers-error-all-regs-reserved.ll | 6 ++--- .../AMDGPU/ran-out-of-registers-errors.ll | 2 +- .../ran-out-of-sgprs-allocation-failure.mir | 2 +- llvm/test/CodeGen/AMDGPU/rcp-pattern.ll | 4 +-- .../AMDGPU/read-register-invalid-register.ll | 4 +-- .../AMDGPU/read-register-invalid-subtarget.ll | 2 +- .../read-write-register-illegal-type.ll | 2 +- llvm/test/CodeGen/AMDGPU/read_register.ll | 4 +-- llvm/test/CodeGen/AMDGPU/readcyclecounter.ll | 26 +++++++++---------- llvm/test/CodeGen/AMDGPU/readlane_exec0.mir | 4 +-- llvm/test/CodeGen/AMDGPU/readsteadycounter.ll | 10 +++---- .../AMDGPU/reassoc-mul-add-1-to-mad.ll | 20 +++++++------- llvm/test/CodeGen/AMDGPU/reassoc-scalar.ll | 4 +-- llvm/test/CodeGen/AMDGPU/recursion.ll | 6 ++--- .../AMDGPU/recursive-resource-usage-mcexpr.ll | 2 +- .../AMDGPU/recursive_global_initializer.ll | 2 +- 91 files changed, 181 insertions(+), 181 deletions(-) diff --git a/llvm/test/CodeGen/AMDGPU/power-sched-no-instr-sunit.mir b/llvm/test/CodeGen/AMDGPU/power-sched-no-instr-sunit.mir index 8adb2ba6b77e0..4351528ae496b 100644 --- a/llvm/test/CodeGen/AMDGPU/power-sched-no-instr-sunit.mir +++ b/llvm/test/CodeGen/AMDGPU/power-sched-no-instr-sunit.mir @@ -1,4 +1,4 @@ -# RUN: llc -mtriple=amdgcn -mcpu=gfx908 %s -run-pass=post-RA-sched -o - | FileCheck -check-prefix=GCN %s +# RUN: llc -mtriple=amdgpu9.08 %s -run-pass=post-RA-sched -o - | FileCheck -check-prefix=GCN %s # GCN-LABEL: name: test # GCN: V_MFMA_F32_32X32X1F32 diff --git a/llvm/test/CodeGen/AMDGPU/pr51516.mir b/llvm/test/CodeGen/AMDGPU/pr51516.mir index 69983faf2b154..033656354f2c1 100644 --- a/llvm/test/CodeGen/AMDGPU/pr51516.mir +++ b/llvm/test/CodeGen/AMDGPU/pr51516.mir @@ -1,6 +1,6 @@ # NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 -# RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx900 -amdgpu-disable-unclustered-high-rp-reschedule -verify-misched -start-before=machine-scheduler -stop-after=virtregrewriter,2 -o - %s | FileCheck -check-prefix=GCN %s -# RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx900 -amdgpu-disable-unclustered-high-rp-reschedule -amdgpu-use-amdgpu-trackers=1 -verify-misched -start-before=machine-scheduler -stop-after=virtregrewriter,2 -o - %s | FileCheck -check-prefix=GCN-GCNTRACKER %s +# RUN: llc -mtriple=amdgpu9.00--amdhsa -amdgpu-disable-unclustered-high-rp-reschedule -verify-misched -start-before=machine-scheduler -stop-after=virtregrewriter,2 -o - %s | FileCheck -check-prefix=GCN %s +# RUN: llc -mtriple=amdgpu9.00--amdhsa -amdgpu-disable-unclustered-high-rp-reschedule -amdgpu-use-amdgpu-trackers=1 -verify-misched -start-before=machine-scheduler -stop-after=virtregrewriter,2 -o - %s | FileCheck -check-prefix=GCN-GCNTRACKER %s # Check that %3 was not rematerialized before the last store since its operand %1 # is killed by that store. diff --git a/llvm/test/CodeGen/AMDGPU/preload-implicit-kernargs-IR-lowering.ll b/llvm/test/CodeGen/AMDGPU/preload-implicit-kernargs-IR-lowering.ll index 830d7cc840aeb..86b17eac16344 100644 --- a/llvm/test/CodeGen/AMDGPU/preload-implicit-kernargs-IR-lowering.ll +++ b/llvm/test/CodeGen/AMDGPU/preload-implicit-kernargs-IR-lowering.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5 -; RUN: opt -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 -passes='amdgpu-attributor,amdgpu-preload-kernel-arguments,function(amdgpu-lower-kernel-arguments)' -S < %s | FileCheck -check-prefix=NO-PRELOAD %s -; RUN: opt -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 -passes='amdgpu-attributor,amdgpu-preload-kernel-arguments,function(amdgpu-lower-kernel-arguments)' -amdgpu-kernarg-preload-count=16 -S < %s | FileCheck -check-prefix=PRELOAD %s +; RUN: opt -mtriple=amdgpu9.42-amd-amdhsa -passes='amdgpu-attributor,amdgpu-preload-kernel-arguments,function(amdgpu-lower-kernel-arguments)' -S < %s | FileCheck -check-prefix=NO-PRELOAD %s +; RUN: opt -mtriple=amdgpu9.42-amd-amdhsa -passes='amdgpu-attributor,amdgpu-preload-kernel-arguments,function(amdgpu-lower-kernel-arguments)' -amdgpu-kernarg-preload-count=16 -S < %s | FileCheck -check-prefix=PRELOAD %s define amdgpu_kernel void @preload_block_count_x(ptr addrspace(1) %out) { ; NO-PRELOAD-LABEL: define amdgpu_kernel void @preload_block_count_x( diff --git a/llvm/test/CodeGen/AMDGPU/preload-implicit-kernargs-debug-info.ll b/llvm/test/CodeGen/AMDGPU/preload-implicit-kernargs-debug-info.ll index 0f9a08a85a8cd..a93c12842c9cb 100644 --- a/llvm/test/CodeGen/AMDGPU/preload-implicit-kernargs-debug-info.ll +++ b/llvm/test/CodeGen/AMDGPU/preload-implicit-kernargs-debug-info.ll @@ -1,4 +1,4 @@ -; RUN: opt -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 -passes='amdgpu-attributor,amdgpu-preload-kernel-arguments,function(amdgpu-lower-kernel-arguments)' -amdgpu-kernarg-preload-count=16 -S < %s 2>&1 \ +; RUN: opt -mtriple=amdgpu9.42-amd-amdhsa -passes='amdgpu-attributor,amdgpu-preload-kernel-arguments,function(amdgpu-lower-kernel-arguments)' -amdgpu-kernarg-preload-count=16 -S < %s 2>&1 \ ; RUN: | FileCheck --match-full-lines --implicit-check-not='declare' %s ; Confirms we do not leave behind a declaration which references the same diff --git a/llvm/test/CodeGen/AMDGPU/preload-implicit-kernargs.ll b/llvm/test/CodeGen/AMDGPU/preload-implicit-kernargs.ll index a8db3da8b3216..096c59fb0a06a 100644 --- a/llvm/test/CodeGen/AMDGPU/preload-implicit-kernargs.ll +++ b/llvm/test/CodeGen/AMDGPU/preload-implicit-kernargs.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 -; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx942 < %s | FileCheck -check-prefixes=GFX942 %s -; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx90a < %s | FileCheck -check-prefixes=GFX90a %s -; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx1250 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-FAKE16 %s -; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx1250 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-REAL16 %s +; RUN: llc -mtriple=amdgpu9.42--amdhsa < %s | FileCheck -check-prefixes=GFX942 %s +; RUN: llc -mtriple=amdgpu9.0a--amdhsa < %s | FileCheck -check-prefixes=GFX90a %s +; RUN: llc -mtriple=amdgpu12.50--amdhsa -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-FAKE16 %s +; RUN: llc -mtriple=amdgpu12.50--amdhsa -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-REAL16 %s define amdgpu_kernel void @preload_block_count_x(ptr addrspace(1) inreg %out) #0 { ; GFX942-LABEL: preload_block_count_x: diff --git a/llvm/test/CodeGen/AMDGPU/preload-kernargs-IR-lowering.ll b/llvm/test/CodeGen/AMDGPU/preload-kernargs-IR-lowering.ll index 1a445af94b9ad..b6e8b769a4480 100644 --- a/llvm/test/CodeGen/AMDGPU/preload-kernargs-IR-lowering.ll +++ b/llvm/test/CodeGen/AMDGPU/preload-kernargs-IR-lowering.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature -; RUN: opt -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 -passes='amdgpu-attributor,amdgpu-preload-kernel-arguments,function(amdgpu-lower-kernel-arguments)' -S < %s | FileCheck -check-prefix=NO-PRELOAD %s -; RUN: opt -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 -passes='amdgpu-attributor,amdgpu-preload-kernel-arguments,function(amdgpu-lower-kernel-arguments)' -amdgpu-kernarg-preload-count=1 -S < %s | FileCheck -check-prefix=PRELOAD-1 %s -; RUN: opt -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 -passes='amdgpu-attributor,amdgpu-preload-kernel-arguments,function(amdgpu-lower-kernel-arguments)' -amdgpu-kernarg-preload-count=3 -S < %s | FileCheck -check-prefix=PRELOAD-3 %s -; RUN: opt -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 -passes='amdgpu-attributor,amdgpu-preload-kernel-arguments,function(amdgpu-lower-kernel-arguments)' -amdgpu-kernarg-preload-count=8 -S < %s | FileCheck -check-prefix=PRELOAD-8 %s +; RUN: opt -mtriple=amdgpu9.42-amd-amdhsa -passes='amdgpu-attributor,amdgpu-preload-kernel-arguments,function(amdgpu-lower-kernel-arguments)' -S < %s | FileCheck -check-prefix=NO-PRELOAD %s +; RUN: opt -mtriple=amdgpu9.42-amd-amdhsa -passes='amdgpu-attributor,amdgpu-preload-kernel-arguments,function(amdgpu-lower-kernel-arguments)' -amdgpu-kernarg-preload-count=1 -S < %s | FileCheck -check-prefix=PRELOAD-1 %s +; RUN: opt -mtriple=amdgpu9.42-amd-amdhsa -passes='amdgpu-attributor,amdgpu-preload-kernel-arguments,function(amdgpu-lower-kernel-arguments)' -amdgpu-kernarg-preload-count=3 -S < %s | FileCheck -check-prefix=PRELOAD-3 %s +; RUN: opt -mtriple=amdgpu9.42-amd-amdhsa -passes='amdgpu-attributor,amdgpu-preload-kernel-arguments,function(amdgpu-lower-kernel-arguments)' -amdgpu-kernarg-preload-count=8 -S < %s | FileCheck -check-prefix=PRELOAD-8 %s define amdgpu_kernel void @test_preload_IR_lowering_kernel_2(ptr addrspace(1) %in, ptr addrspace(1) %out) #0 { ; NO-PRELOAD-LABEL: define {{[^@]+}}@test_preload_IR_lowering_kernel_2 diff --git a/llvm/test/CodeGen/AMDGPU/preload-kernargs.ll b/llvm/test/CodeGen/AMDGPU/preload-kernargs.ll index 3cd240dce4a69..2f8a7b0ae9feb 100644 --- a/llvm/test/CodeGen/AMDGPU/preload-kernargs.ll +++ b/llvm/test/CodeGen/AMDGPU/preload-kernargs.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 -; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx942 < %s | FileCheck -check-prefixes=GFX942 %s -; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx90a < %s | FileCheck -check-prefixes=GFX90a %s -; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GFX1250 %s +; RUN: llc -mtriple=amdgpu9.42--amdhsa < %s | FileCheck -check-prefixes=GFX942 %s +; RUN: llc -mtriple=amdgpu9.0a--amdhsa < %s | FileCheck -check-prefixes=GFX90a %s +; RUN: llc -mtriple=amdgpu12.50--amdhsa < %s | FileCheck -check-prefixes=GFX1250 %s define amdgpu_kernel void @ptr1_i8(ptr addrspace(1) inreg %out, i8 inreg %arg0) #0 { ; GFX942-LABEL: ptr1_i8: diff --git a/llvm/test/CodeGen/AMDGPU/preserve-hi16.ll b/llvm/test/CodeGen/AMDGPU/preserve-hi16.ll index 4e343f7e2cd3f..451ac138be532 100644 --- a/llvm/test/CodeGen/AMDGPU/preserve-hi16.ll +++ b/llvm/test/CodeGen/AMDGPU/preserve-hi16.ll @@ -1,10 +1,10 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 -; RUN: llc -mtriple=amdgcn -mcpu=gfx803 < %s | FileCheck --check-prefixes=GFX8 %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck --check-prefixes=GFX9ALL,GFX900 %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx906 < %s | FileCheck --check-prefixes=GFX9ALL,GFX906 %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10 %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s +; RUN: llc -mtriple=amdgpu8.03 < %s | FileCheck --check-prefixes=GFX8 %s +; RUN: llc -mtriple=amdgpu9.00 < %s | FileCheck --check-prefixes=GFX9ALL,GFX900 %s +; RUN: llc -mtriple=amdgpu9.06 < %s | FileCheck --check-prefixes=GFX9ALL,GFX906 %s +; RUN: llc -mtriple=amdgpu10.10 < %s | FileCheck -check-prefixes=GFX10 %s +; RUN: llc -mtriple=amdgpu11.00 -amdgpu-enable-delay-alu=0 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s +; RUN: llc -mtriple=amdgpu11.00 -amdgpu-enable-delay-alu=0 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s define i16 @shl_i16(i16 %x, i16 %y) { ; GFX8-LABEL: shl_i16: diff --git a/llvm/test/CodeGen/AMDGPU/preserve-only-inactive-lane.mir b/llvm/test/CodeGen/AMDGPU/preserve-only-inactive-lane.mir index 788f9579d2e17..b5f87729eb167 100644 --- a/llvm/test/CodeGen/AMDGPU/preserve-only-inactive-lane.mir +++ b/llvm/test/CodeGen/AMDGPU/preserve-only-inactive-lane.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -verify-machineinstrs -run-pass=prolog-epilog -o - %s | FileCheck -check-prefix=GCN %s +# RUN: llc -mtriple=amdgpu9.06-amd-amdhsa -verify-machineinstrs -run-pass=prolog-epilog -o - %s | FileCheck -check-prefix=GCN %s # The scratch register vgpr0 is used here to spill sgpr35 register. # The function also returns a value that goes via. vgpr0. diff --git a/llvm/test/CodeGen/AMDGPU/preserve-wwm-copy-dst-reg.ll b/llvm/test/CodeGen/AMDGPU/preserve-wwm-copy-dst-reg.ll index 5255eb3bed12d..c22e48557b876 100644 --- a/llvm/test/CodeGen/AMDGPU/preserve-wwm-copy-dst-reg.ll +++ b/llvm/test/CodeGen/AMDGPU/preserve-wwm-copy-dst-reg.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 < %s | FileCheck -check-prefix=GFX906 %s -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 < %s | FileCheck -check-prefix=GFX908 %s +; RUN: llc -mtriple=amdgpu9.06-amd-amdhsa < %s | FileCheck -check-prefix=GFX906 %s +; RUN: llc -mtriple=amdgpu9.08-amd-amdhsa < %s | FileCheck -check-prefix=GFX908 %s ; Due to high register pressure, regalloc would split the liverange of wwm VGPR register used for SGPR spills ; and introduce a copy. The copy should be of whole-wave with exec mask manipulation around it. diff --git a/llvm/test/CodeGen/AMDGPU/print-pipeline-passes.ll b/llvm/test/CodeGen/AMDGPU/print-pipeline-passes.ll index b1fc76f457ece..0fe839585b67d 100644 --- a/llvm/test/CodeGen/AMDGPU/print-pipeline-passes.ll +++ b/llvm/test/CodeGen/AMDGPU/print-pipeline-passes.ll @@ -1,12 +1,12 @@ -; RUN: opt -mtriple=amdgcn--amdhsa -S -passes="lto<O0>" -print-pipeline-passes %s -o - | FileCheck --check-prefix=O0 %s -; RUN: opt -mtriple=amdgcn--amdhsa -S -passes="lto<O1>" -print-pipeline-passes %s -o - | FileCheck %s -; RUN: opt -mtriple=amdgcn--amdhsa -S -passes="lto<O2>" -print-pipeline-passes %s -o - | FileCheck %s -; RUN: opt -mtriple=amdgcn--amdhsa -S -passes="lto<O3>" -print-pipeline-passes %s -o - | FileCheck %s +; RUN: opt -mtriple=amdgpu--amdhsa -S -passes="lto<O0>" -print-pipeline-passes %s -o - | FileCheck --check-prefix=O0 %s +; RUN: opt -mtriple=amdgpu--amdhsa -S -passes="lto<O1>" -print-pipeline-passes %s -o - | FileCheck %s +; RUN: opt -mtriple=amdgpu--amdhsa -S -passes="lto<O2>" -print-pipeline-passes %s -o - | FileCheck %s +; RUN: opt -mtriple=amdgpu--amdhsa -S -passes="lto<O3>" -print-pipeline-passes %s -o - | FileCheck %s -; RUN: opt -mtriple=amdgcn--amdhsa -S -passes="lto-pre-link<O0>" -print-pipeline-passes -amdgpu-internalize-symbols %s -o - | FileCheck --check-prefix=PRE %s -; RUN: opt -mtriple=amdgcn--amdhsa -S -passes="lto-pre-link<O1>" -print-pipeline-passes -amdgpu-internalize-symbols %s -o - | FileCheck --check-prefix=PRE %s -; RUN: opt -mtriple=amdgcn--amdhsa -S -passes="lto-pre-link<O2>" -print-pipeline-passes -amdgpu-internalize-symbols %s -o - | FileCheck --check-prefix=PRE %s -; RUN: opt -mtriple=amdgcn--amdhsa -S -passes="lto-pre-link<O3>" -print-pipeline-passes -amdgpu-internalize-symbols %s -o - | FileCheck --check-prefix=PRE %s +; RUN: opt -mtriple=amdgpu--amdhsa -S -passes="lto-pre-link<O0>" -print-pipeline-passes -amdgpu-internalize-symbols %s -o - | FileCheck --check-prefix=PRE %s +; RUN: opt -mtriple=amdgpu--amdhsa -S -passes="lto-pre-link<O1>" -print-pipeline-passes -amdgpu-internalize-symbols %s -o - | FileCheck --check-prefix=PRE %s +; RUN: opt -mtriple=amdgpu--amdhsa -S -passes="lto-pre-link<O2>" -print-pipeline-passes -amdgpu-internalize-symbols %s -o - | FileCheck --check-prefix=PRE %s +; RUN: opt -mtriple=amdgpu--amdhsa -S -passes="lto-pre-link<O3>" -print-pipeline-passes -amdgpu-internalize-symbols %s -o - | FileCheck --check-prefix=PRE %s ; CHECK: amdgpu-attributor diff --git a/llvm/test/CodeGen/AMDGPU/printf-defined.ll b/llvm/test/CodeGen/AMDGPU/printf-defined.ll index 22740a008f900..4c1c18d7b595f 100644 --- a/llvm/test/CodeGen/AMDGPU/printf-defined.ll +++ b/llvm/test/CodeGen/AMDGPU/printf-defined.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt -mtriple=amdgcn-- -passes=amdgpu-printf-runtime-binding -mcpu=fiji -S < %s | FileCheck --check-prefix=GCN %s +; RUN: opt -mtriple=amdgpu8.03-- -passes=amdgpu-printf-runtime-binding -S < %s | FileCheck --check-prefix=GCN %s @format.str = private unnamed_addr addrspace(4) constant [8 x i8] c"arst %d\00", align 1 diff --git a/llvm/test/CodeGen/AMDGPU/printf-existing-format-strings.ll b/llvm/test/CodeGen/AMDGPU/printf-existing-format-strings.ll index 394ddeaa77b9f..7c41740507899 100644 --- a/llvm/test/CodeGen/AMDGPU/printf-existing-format-strings.ll +++ b/llvm/test/CodeGen/AMDGPU/printf-existing-format-strings.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals -; RUN: opt -mtriple=amdgcn-- -passes=amdgpu-printf-runtime-binding -S < %s | FileCheck --check-prefix=GCN %s +; RUN: opt -mtriple=amdgpu-- -passes=amdgpu-printf-runtime-binding -S < %s | FileCheck --check-prefix=GCN %s ; Make sure the correct index is used for newly added entries to ; llvm.printf.fmts if one already exists in the module. diff --git a/llvm/test/CodeGen/AMDGPU/private-access-no-objects.ll b/llvm/test/CodeGen/AMDGPU/private-access-no-objects.ll index f2c7abaf4fa40..4f2957bae571a 100644 --- a/llvm/test/CodeGen/AMDGPU/private-access-no-objects.ll +++ b/llvm/test/CodeGen/AMDGPU/private-access-no-objects.ll @@ -1,7 +1,7 @@ -; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=fiji < %s | FileCheck -enable-var-scope --check-prefixes=GCN,OPT %s -; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=hawaii < %s | FileCheck -enable-var-scope --check-prefixes=GCN,OPT %s -; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=iceland < %s | FileCheck -enable-var-scope --check-prefixes=GCN,OPT %s -; RUN: llc -O0 -mtriple=amdgcn--amdhsa -mcpu=fiji < %s | FileCheck -enable-var-scope --check-prefixes=GCN,OPTNONE %s +; RUN: llc -mtriple=amdgpu8.03--amdhsa < %s | FileCheck -enable-var-scope --check-prefixes=GCN,OPT %s +; RUN: llc -mtriple=amdgpu7.01--amdhsa < %s | FileCheck -enable-var-scope --check-prefixes=GCN,OPT %s +; RUN: llc -mtriple=amdgpu8.02--amdhsa < %s | FileCheck -enable-var-scope --check-prefixes=GCN,OPT %s +; RUN: llc -O0 -mtriple=amdgpu8.03--amdhsa < %s | FileCheck -enable-var-scope --check-prefixes=GCN,OPTNONE %s ; There are no stack objects, but still a private memory access. The ; private access regiters need to be correctly initialized anyway, and diff --git a/llvm/test/CodeGen/AMDGPU/private-function.ll b/llvm/test/CodeGen/AMDGPU/private-function.ll index 8eefc9dfc5d7e..94bafa1079ff4 100644 --- a/llvm/test/CodeGen/AMDGPU/private-function.ll +++ b/llvm/test/CodeGen/AMDGPU/private-function.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 -; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck %s +; RUN: llc -mtriple=amdgpu12.00 < %s | FileCheck %s define private void @foo() { ; CHECK-LABEL: foo: diff --git a/llvm/test/CodeGen/AMDGPU/prologue-epilogue-markers.ll b/llvm/test/CodeGen/AMDGPU/prologue-epilogue-markers.ll index ba460fc7b4266..199f2ed80d37a 100644 --- a/llvm/test/CodeGen/AMDGPU/prologue-epilogue-markers.ll +++ b/llvm/test/CodeGen/AMDGPU/prologue-epilogue-markers.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck %s -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -filetype=obj < %s | llvm-dwarfdump --debug-line - | FileCheck --check-prefix=DWARFLINE %s +; RUN: llc -mtriple=amdgpu9.00-amd-amdhsa < %s | FileCheck %s +; RUN: llc -mtriple=amdgpu9.00-amd-amdhsa -filetype=obj < %s | llvm-dwarfdump --debug-line - | FileCheck --check-prefix=DWARFLINE %s ; Test that the prologue end line directive is emitted after all the prologue instructions ; and also before the beginning of the epilogue instructions in a trivial function. diff --git a/llvm/test/CodeGen/AMDGPU/promote-alloca-addrspacecast.ll b/llvm/test/CodeGen/AMDGPU/promote-alloca-addrspacecast.ll index bf4e02d8d7e1c..259b2be1c915b 100644 --- a/llvm/test/CodeGen/AMDGPU/promote-alloca-addrspacecast.ll +++ b/llvm/test/CodeGen/AMDGPU/promote-alloca-addrspacecast.ll @@ -1,4 +1,4 @@ -; RUN: opt -S -mtriple=amdgcn-unknown-amdhsa -mcpu=kaveri -passes=amdgpu-promote-alloca < %s | FileCheck %s +; RUN: opt -S -mtriple=amdgpu7.00-unknown-amdhsa -passes=amdgpu-promote-alloca < %s | FileCheck %s ; The types of the users of the addrspacecast should not be changed. diff --git a/llvm/test/CodeGen/AMDGPU/promote-alloca-array-aggregate.ll b/llvm/test/CodeGen/AMDGPU/promote-alloca-array-aggregate.ll index 1edb7dae6f537..f0642942e9e7d 100644 --- a/llvm/test/CodeGen/AMDGPU/promote-alloca-array-aggregate.ll +++ b/llvm/test/CodeGen/AMDGPU/promote-alloca-array-aggregate.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -passes=sroa,amdgpu-promote-alloca < %s | FileCheck %s +; RUN: opt -S -mtriple=amdgpu-amd-amdhsa -passes=sroa,amdgpu-promote-alloca < %s | FileCheck %s ; Make sure that array alloca loaded and stored as multi-element aggregates are handled correctly ; Strictly the promote-alloca pass shouldn't have to deal with this case as it is non-canonical, but diff --git a/llvm/test/CodeGen/AMDGPU/promote-alloca-array-allocation.ll b/llvm/test/CodeGen/AMDGPU/promote-alloca-array-allocation.ll index a590bbc8023e0..afe849c891656 100644 --- a/llvm/test/CodeGen/AMDGPU/promote-alloca-array-allocation.ll +++ b/llvm/test/CodeGen/AMDGPU/promote-alloca-array-allocation.ll @@ -1,4 +1,4 @@ -; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -passes=amdgpu-promote-alloca < %s | FileCheck %s +; RUN: opt -S -mtriple=amdgpu-amd-amdhsa -passes=amdgpu-promote-alloca < %s | FileCheck %s ; Make sure this allocates the correct size if the alloca has a non-0 ; number of elements. diff --git a/llvm/test/CodeGen/AMDGPU/promote-alloca-bitcast-function.ll b/llvm/test/CodeGen/AMDGPU/promote-alloca-bitcast-function.ll index 5123940443c3b..868ac70dde335 100644 --- a/llvm/test/CodeGen/AMDGPU/promote-alloca-bitcast-function.ll +++ b/llvm/test/CodeGen/AMDGPU/promote-alloca-bitcast-function.ll @@ -1,4 +1,4 @@ -; RUN: opt -S -mtriple=amdgcn-unknown-unknown -passes=amdgpu-promote-alloca -disable-promote-alloca-to-vector < %s | FileCheck %s +; RUN: opt -S -mtriple=amdgpu-unknown-unknown -passes=amdgpu-promote-alloca -disable-promote-alloca-to-vector < %s | FileCheck %s ; Make sure that AMDGPUPromoteAlloca doesn't crash if the called ; function is a constantexpr cast of a function. diff --git a/llvm/test/CodeGen/AMDGPU/promote-alloca-calling-conv.ll b/llvm/test/CodeGen/AMDGPU/promote-alloca-calling-conv.ll index f4439022ffe38..8cec9aca0b837 100644 --- a/llvm/test/CodeGen/AMDGPU/promote-alloca-calling-conv.ll +++ b/llvm/test/CodeGen/AMDGPU/promote-alloca-calling-conv.ll @@ -1,5 +1,5 @@ -; RUN: opt -S -mtriple=amdgcn-unknown-unknown -passes=amdgpu-promote-alloca -disable-promote-alloca-to-vector < %s | FileCheck -check-prefix=IR %s -; RUN: llc -mtriple=amdgcn -mcpu=fiji -disable-promote-alloca-to-vector < %s | FileCheck -check-prefix=ASM %s +; RUN: opt -S -mtriple=amdgpu-unknown-unknown -passes=amdgpu-promote-alloca -disable-promote-alloca-to-vector < %s | FileCheck -check-prefix=IR %s +; RUN: llc -mtriple=amdgpu8.03 -disable-promote-alloca-to-vector < %s | FileCheck -check-prefix=ASM %s ; IR-LABEL: define amdgpu_vs void @promote_alloca_shaders(ptr addrspace(1) inreg %out, ptr addrspace(1) inreg %in) #0 { ; IR: alloca [5 x i32] diff --git a/llvm/test/CodeGen/AMDGPU/promote-alloca-cfg.ll b/llvm/test/CodeGen/AMDGPU/promote-alloca-cfg.ll index 10d98fd0a0610..1bcccc273670d 100644 --- a/llvm/test/CodeGen/AMDGPU/promote-alloca-cfg.ll +++ b/llvm/test/CodeGen/AMDGPU/promote-alloca-cfg.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt -S -mtriple=amdgcn-unknown-amdhsa -passes=amdgpu-promote-alloca < %s | FileCheck %s +; RUN: opt -S -mtriple=amdgpu-unknown-amdhsa -passes=amdgpu-promote-alloca < %s | FileCheck %s ; Checks that certain CFGs are handled correctly. diff --git a/llvm/test/CodeGen/AMDGPU/promote-alloca-globals.ll b/llvm/test/CodeGen/AMDGPU/promote-alloca-globals.ll index eee8f6a1b4561..b02c7c6dd6d7c 100644 --- a/llvm/test/CodeGen/AMDGPU/promote-alloca-globals.ll +++ b/llvm/test/CodeGen/AMDGPU/promote-alloca-globals.ll @@ -1,5 +1,5 @@ -; RUN: opt -S -mtriple=amdgcn-unknown-unknown -passes=amdgpu-promote-alloca < %s | FileCheck -check-prefix=IR %s -; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=ASM %s +; RUN: opt -S -mtriple=amdgpu-unknown-unknown -passes=amdgpu-promote-alloca < %s | FileCheck -check-prefix=IR %s +; RUN: llc -mtriple=amdgpu8.02 < %s | FileCheck -check-prefix=ASM %s @global_array0 = internal unnamed_addr addrspace(3) global [750 x [10 x i32]] poison, align 4 diff --git a/llvm/test/CodeGen/AMDGPU/promote-alloca-invariant-markers.ll b/llvm/test/CodeGen/AMDGPU/promote-alloca-invariant-markers.ll index e100e7a41472c..482189c23c700 100644 --- a/llvm/test/CodeGen/AMDGPU/promote-alloca-invariant-markers.ll +++ b/llvm/test/CodeGen/AMDGPU/promote-alloca-invariant-markers.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5 -; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -passes=amdgpu-promote-alloca %s -o - | FileCheck %s +; RUN: opt -S -mtriple=amdgpu-amd-amdhsa -passes=amdgpu-promote-alloca %s -o - | FileCheck %s declare ptr @llvm.invariant.start.p5(i64, ptr addrspace(5) nocapture) declare void @llvm.invariant.end.p5(ptr, i64, ptr addrspace(5) nocapture) diff --git a/llvm/test/CodeGen/AMDGPU/promote-alloca-lifetime.ll b/llvm/test/CodeGen/AMDGPU/promote-alloca-lifetime.ll index 2bd8a283e22b1..1dd85cafbaa06 100644 --- a/llvm/test/CodeGen/AMDGPU/promote-alloca-lifetime.ll +++ b/llvm/test/CodeGen/AMDGPU/promote-alloca-lifetime.ll @@ -1,4 +1,4 @@ -; RUN: opt -S -mtriple=amdgcn-unknown-amdhsa -passes=amdgpu-promote-alloca %s | FileCheck -check-prefix=OPT %s +; RUN: opt -S -mtriple=amdgpu-unknown-amdhsa -passes=amdgpu-promote-alloca %s | FileCheck -check-prefix=OPT %s declare void @llvm.lifetime.start.p5(i64, ptr addrspace(5) nocapture) #0 declare void @llvm.lifetime.end.p5(i64, ptr addrspace(5) nocapture) #0 diff --git a/llvm/test/CodeGen/AMDGPU/promote-alloca-loadstores.ll b/llvm/test/CodeGen/AMDGPU/promote-alloca-loadstores.ll index 598a954da0567..0773a60453de6 100644 --- a/llvm/test/CodeGen/AMDGPU/promote-alloca-loadstores.ll +++ b/llvm/test/CodeGen/AMDGPU/promote-alloca-loadstores.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2 -; RUN: opt -S -mtriple=amdgcn-unknown-amdhsa -passes=amdgpu-promote-alloca < %s | FileCheck %s +; RUN: opt -S -mtriple=amdgpu-unknown-amdhsa -passes=amdgpu-promote-alloca < %s | FileCheck %s define amdgpu_kernel void @test_overwrite(i64 %val, i1 %cond) { ; CHECK-LABEL: define amdgpu_kernel void @test_overwrite diff --git a/llvm/test/CodeGen/AMDGPU/promote-alloca-max-regs.ll b/llvm/test/CodeGen/AMDGPU/promote-alloca-max-regs.ll index c1123d7b515be..61d619d76700d 100644 --- a/llvm/test/CodeGen/AMDGPU/promote-alloca-max-regs.ll +++ b/llvm/test/CodeGen/AMDGPU/promote-alloca-max-regs.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5 -; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -passes=amdgpu-promote-alloca -disable-promote-alloca-to-lds=1 -amdgpu-promote-alloca-to-vector-max-regs=16 < %s | FileCheck --check-prefix=BASE --check-prefix=MAX16 %s -; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -passes=amdgpu-promote-alloca -disable-promote-alloca-to-lds=1 -amdgpu-promote-alloca-to-vector-max-regs=24 < %s | FileCheck --check-prefix=BASE %s --check-prefix=MAX24 -; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -passes=amdgpu-promote-alloca -disable-promote-alloca-to-lds=1 < %s | FileCheck --check-prefix=BASE %s --check-prefix=DEFAULT +; RUN: opt -S -mtriple=amdgpu-amd-amdhsa -passes=amdgpu-promote-alloca -disable-promote-alloca-to-lds=1 -amdgpu-promote-alloca-to-vector-max-regs=16 < %s | FileCheck --check-prefix=BASE --check-prefix=MAX16 %s +; RUN: opt -S -mtriple=amdgpu-amd-amdhsa -passes=amdgpu-promote-alloca -disable-promote-alloca-to-lds=1 -amdgpu-promote-alloca-to-vector-max-regs=24 < %s | FileCheck --check-prefix=BASE %s --check-prefix=MAX24 +; RUN: opt -S -mtriple=amdgpu-amd-amdhsa -passes=amdgpu-promote-alloca -disable-promote-alloca-to-lds=1 < %s | FileCheck --check-prefix=BASE %s --check-prefix=DEFAULT define amdgpu_kernel void @i32_24_elements(ptr %out) #0 { ; MAX16-LABEL: define amdgpu_kernel void @i32_24_elements( diff --git a/llvm/test/CodeGen/AMDGPU/promote-alloca-mem-intrinsics.ll b/llvm/test/CodeGen/AMDGPU/promote-alloca-mem-intrinsics.ll index ec04c6aa7f10d..09d9bb2e066ee 100644 --- a/llvm/test/CodeGen/AMDGPU/promote-alloca-mem-intrinsics.ll +++ b/llvm/test/CodeGen/AMDGPU/promote-alloca-mem-intrinsics.ll @@ -1,4 +1,4 @@ -; RUN: opt -S -mtriple=amdgcn-unknown-amdhsa -mcpu=kaveri -passes=amdgpu-promote-alloca -amdgpu-promote-alloca-to-vector-max-regs=16 < %s | FileCheck --enable-var-scope %s +; RUN: opt -S -mtriple=amdgpu7.00-unknown-amdhsa -passes=amdgpu-promote-alloca -amdgpu-promote-alloca-to-vector-max-regs=16 < %s | FileCheck --enable-var-scope %s declare void @llvm.memcpy.p5.p1.i32(ptr addrspace(5) nocapture, ptr addrspace(1) nocapture, i32, i1) #0 declare void @llvm.memcpy.p1.p5.i32(ptr addrspace(1) nocapture, ptr addrspace(5) nocapture, i32, i1) #0 diff --git a/llvm/test/CodeGen/AMDGPU/promote-alloca-memset.ll b/llvm/test/CodeGen/AMDGPU/promote-alloca-memset.ll index 81d6dba494cfc..5ad969050c2be 100644 --- a/llvm/test/CodeGen/AMDGPU/promote-alloca-memset.ll +++ b/llvm/test/CodeGen/AMDGPU/promote-alloca-memset.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt -S -mtriple=amdgcn-unknown-amdhsa -passes=amdgpu-promote-alloca < %s | FileCheck %s +; RUN: opt -S -mtriple=amdgpu-unknown-amdhsa -passes=amdgpu-promote-alloca < %s | FileCheck %s ; Checks that memsets don't block PromoteAlloca. diff --git a/llvm/test/CodeGen/AMDGPU/promote-alloca-multidim.ll b/llvm/test/CodeGen/AMDGPU/promote-alloca-multidim.ll index 7b64d8728cc24..bc77c69edc74a 100644 --- a/llvm/test/CodeGen/AMDGPU/promote-alloca-multidim.ll +++ b/llvm/test/CodeGen/AMDGPU/promote-alloca-multidim.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5 -; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -passes=amdgpu-promote-alloca -disable-promote-alloca-to-lds=1 < %s | FileCheck %s +; RUN: opt -S -mtriple=amdgpu-amd-amdhsa -passes=amdgpu-promote-alloca -disable-promote-alloca-to-lds=1 < %s | FileCheck %s define amdgpu_kernel void @i32_2d_load_store(ptr %out) { ; CHECK-LABEL: define amdgpu_kernel void @i32_2d_load_store( diff --git a/llvm/test/CodeGen/AMDGPU/promote-alloca-negative-index.ll b/llvm/test/CodeGen/AMDGPU/promote-alloca-negative-index.ll index 7ebb4ca262614..04296381923e9 100644 --- a/llvm/test/CodeGen/AMDGPU/promote-alloca-negative-index.ll +++ b/llvm/test/CodeGen/AMDGPU/promote-alloca-negative-index.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -passes=amdgpu-promote-alloca -disable-promote-alloca-to-lds=1 < %s | FileCheck %s +; RUN: opt -S -mtriple=amdgpu-amd-amdhsa -passes=amdgpu-promote-alloca -disable-promote-alloca-to-lds=1 < %s | FileCheck %s ; Check that the extracted index is correctly sign-extended when 32-bit scratch ; address arithmetic is promoted to 64-bit vector index arithmetic. diff --git a/llvm/test/CodeGen/AMDGPU/promote-alloca-no-opts.ll b/llvm/test/CodeGen/AMDGPU/promote-alloca-no-opts.ll index 53e04e2d27671..351a483a86699 100644 --- a/llvm/test/CodeGen/AMDGPU/promote-alloca-no-opts.ll +++ b/llvm/test/CodeGen/AMDGPU/promote-alloca-no-opts.ll @@ -1,5 +1,5 @@ -; RUN: llc -O0 -mtriple=amdgcn-unknown-amdhsa -mcpu=kaveri -disable-promote-alloca-to-vector=1 < %s | FileCheck -check-prefix=NOOPTS -check-prefix=ALL %s -; RUN: llc -O1 -mtriple=amdgcn-unknown-amdhsa -mcpu=kaveri -disable-promote-alloca-to-vector=1 < %s | FileCheck -check-prefix=OPTS -check-prefix=ALL %s +; RUN: llc -O0 -mtriple=amdgpu7.00-unknown-amdhsa -disable-promote-alloca-to-vector=1 < %s | FileCheck -check-prefix=NOOPTS -check-prefix=ALL %s +; RUN: llc -O1 -mtriple=amdgpu7.00-unknown-amdhsa -disable-promote-alloca-to-vector=1 < %s | FileCheck -check-prefix=OPTS -check-prefix=ALL %s ; ALL-LABEL: {{^}}promote_alloca_i32_array_array: ; NOOPTS: .amdhsa_group_segment_fixed_size 0 diff --git a/llvm/test/CodeGen/AMDGPU/promote-alloca-non-byte-sizes.ll b/llvm/test/CodeGen/AMDGPU/promote-alloca-non-byte-sizes.ll index 4095347d78624..7dc1a55ef7e60 100644 --- a/llvm/test/CodeGen/AMDGPU/promote-alloca-non-byte-sizes.ll +++ b/llvm/test/CodeGen/AMDGPU/promote-alloca-non-byte-sizes.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -passes=amdgpu-promote-alloca < %s | FileCheck %s +; RUN: opt -S -mtriple=amdgpu-amd-amdhsa -passes=amdgpu-promote-alloca < %s | FileCheck %s ; Check that types where the store/allocation sizes don't match the type size ; don't crash. diff --git a/llvm/test/CodeGen/AMDGPU/promote-alloca-non-constant-index.ll b/llvm/test/CodeGen/AMDGPU/promote-alloca-non-constant-index.ll index 391ca7c6d942b..f3ef2faa0d833 100644 --- a/llvm/test/CodeGen/AMDGPU/promote-alloca-non-constant-index.ll +++ b/llvm/test/CodeGen/AMDGPU/promote-alloca-non-constant-index.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 -; RUN: opt -S -mtriple=amdgcn-unknown-amdhsa -passes=amdgpu-promote-alloca < %s | FileCheck %s +; RUN: opt -S -mtriple=amdgpu-unknown-amdhsa -passes=amdgpu-promote-alloca < %s | FileCheck %s ; Check that promoting an alloca to a vector form works correctly when a variable ; vector index is used. diff --git a/llvm/test/CodeGen/AMDGPU/promote-alloca-padding-size-estimate.ll b/llvm/test/CodeGen/AMDGPU/promote-alloca-padding-size-estimate.ll index e29552a9e4f5a..f8adbdff68594 100644 --- a/llvm/test/CodeGen/AMDGPU/promote-alloca-padding-size-estimate.ll +++ b/llvm/test/CodeGen/AMDGPU/promote-alloca-padding-size-estimate.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=kaveri -disable-promote-alloca-to-vector -amdgpu-enable-lower-module-lds=0 < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu7.00-amd-amdhsa -disable-promote-alloca-to-vector -amdgpu-enable-lower-module-lds=0 < %s | FileCheck -check-prefix=GCN %s ; This shows that the amount LDS size estimate should try to not be ; sensitive to the order of the LDS globals. This should try to diff --git a/llvm/test/CodeGen/AMDGPU/promote-alloca-placeholder-replacement.ll b/llvm/test/CodeGen/AMDGPU/promote-alloca-placeholder-replacement.ll index f3993d1a66219..c816f5533efc1 100644 --- a/llvm/test/CodeGen/AMDGPU/promote-alloca-placeholder-replacement.ll +++ b/llvm/test/CodeGen/AMDGPU/promote-alloca-placeholder-replacement.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6 -; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -passes=amdgpu-promote-alloca %s | FileCheck %s +; RUN: opt -S -mtriple=amdgpu-amd-amdhsa -passes=amdgpu-promote-alloca %s | FileCheck %s ; This used to crash when we deplay the value replacement in AMDGPUPromoteAlloca. ; The test might be helpful to catch similar issue around placeholder replacement. diff --git a/llvm/test/CodeGen/AMDGPU/promote-alloca-pointer-array.ll b/llvm/test/CodeGen/AMDGPU/promote-alloca-pointer-array.ll index 9a2efabffecf9..62c245736ece3 100644 --- a/llvm/test/CodeGen/AMDGPU/promote-alloca-pointer-array.ll +++ b/llvm/test/CodeGen/AMDGPU/promote-alloca-pointer-array.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt -S -mtriple=amdgcn-- -mcpu=fiji -passes=amdgpu-promote-alloca < %s | FileCheck -check-prefix=OPT %s +; RUN: opt -S -mtriple=amdgpu8.03-- -passes=amdgpu-promote-alloca < %s | FileCheck -check-prefix=OPT %s define i64 @test_pointer_array(i64 %v) { ; OPT-LABEL: @test_pointer_array( diff --git a/llvm/test/CodeGen/AMDGPU/promote-alloca-proper-value-replacement.ll b/llvm/test/CodeGen/AMDGPU/promote-alloca-proper-value-replacement.ll index 05dd9d7387012..862be6ee61c70 100644 --- a/llvm/test/CodeGen/AMDGPU/promote-alloca-proper-value-replacement.ll +++ b/llvm/test/CodeGen/AMDGPU/promote-alloca-proper-value-replacement.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6 -; RUN: opt -S -mtriple=amdgcn-unknown-unknown -passes=amdgpu-promote-alloca < %s | FileCheck %s +; RUN: opt -S -mtriple=amdgpu-unknown-unknown -passes=amdgpu-promote-alloca < %s | FileCheck %s define void @alloca_value_cross_reference() { ; CHECK-LABEL: define void @alloca_value_cross_reference() { diff --git a/llvm/test/CodeGen/AMDGPU/promote-alloca-scoring.ll b/llvm/test/CodeGen/AMDGPU/promote-alloca-scoring.ll index ae6157af2cf4c..09643a826f003 100644 --- a/llvm/test/CodeGen/AMDGPU/promote-alloca-scoring.ll +++ b/llvm/test/CodeGen/AMDGPU/promote-alloca-scoring.ll @@ -1,4 +1,4 @@ -; RUN: opt -S -mtriple=amdgcn-unknown-amdhsa -mcpu=kaveri -debug-only=amdgpu-promote-alloca -amdgpu-promote-alloca-to-vector-limit=512 -passes=amdgpu-promote-alloca %s -o - 2>&1 | FileCheck %s +; RUN: opt -S -mtriple=amdgpu7.00-unknown-amdhsa -debug-only=amdgpu-promote-alloca -amdgpu-promote-alloca-to-vector-limit=512 -passes=amdgpu-promote-alloca %s -o - 2>&1 | FileCheck %s ; REQUIRES: asserts ; CHECK-LABEL: Analyzing: %simpleuser = alloca [4 x i64], align 4, addrspace(5) diff --git a/llvm/test/CodeGen/AMDGPU/promote-alloca-strip-abi-opt-attributes.ll b/llvm/test/CodeGen/AMDGPU/promote-alloca-strip-abi-opt-attributes.ll index 5cf49c00cac83..19ba0b57e2886 100644 --- a/llvm/test/CodeGen/AMDGPU/promote-alloca-strip-abi-opt-attributes.ll +++ b/llvm/test/CodeGen/AMDGPU/promote-alloca-strip-abi-opt-attributes.ll @@ -1,4 +1,4 @@ -; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -passes=amdgpu-promote-alloca -disable-promote-alloca-to-vector < %s | FileCheck %s +; RUN: opt -S -mtriple=amdgpu-amd-amdhsa -passes=amdgpu-promote-alloca -disable-promote-alloca-to-vector < %s | FileCheck %s ; This kernel starts with the amdgpu-no-workitem-id-* attributes, but ; need to be removed when these intrinsic uses are introduced. diff --git a/llvm/test/CodeGen/AMDGPU/promote-alloca-subvecs.ll b/llvm/test/CodeGen/AMDGPU/promote-alloca-subvecs.ll index 902eccf9e22d0..30cc3e2bac626 100644 --- a/llvm/test/CodeGen/AMDGPU/promote-alloca-subvecs.ll +++ b/llvm/test/CodeGen/AMDGPU/promote-alloca-subvecs.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2 -; RUN: opt -S -mtriple=amdgcn-unknown-amdhsa -passes=amdgpu-promote-alloca -amdgpu-promote-alloca-to-vector-limit=512 -amdgpu-promote-alloca-to-vector-max-regs=32 < %s | FileCheck %s +; RUN: opt -S -mtriple=amdgpu-unknown-amdhsa -passes=amdgpu-promote-alloca -amdgpu-promote-alloca-to-vector-limit=512 -amdgpu-promote-alloca-to-vector-max-regs=32 < %s | FileCheck %s define void @test_trivial_subvector(<2 x i64> %val.0, <2 x i64> %val.1) { ; CHECK-LABEL: define void @test_trivial_subvector diff --git a/llvm/test/CodeGen/AMDGPU/promote-alloca-to-lds-constantexpr-use.ll b/llvm/test/CodeGen/AMDGPU/promote-alloca-to-lds-constantexpr-use.ll index b2b2343d00ef8..187063fd79f03 100644 --- a/llvm/test/CodeGen/AMDGPU/promote-alloca-to-lds-constantexpr-use.ll +++ b/llvm/test/CodeGen/AMDGPU/promote-alloca-to-lds-constantexpr-use.ll @@ -1,5 +1,5 @@ -; RUN: opt -S -disable-promote-alloca-to-vector -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -passes=amdgpu-promote-alloca < %s | FileCheck -check-prefix=IR %s -; RUN: llc -disable-promote-alloca-to-vector -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -amdgpu-enable-lower-module-lds=false < %s | FileCheck -check-prefix=ASM %s +; RUN: opt -S -disable-promote-alloca-to-vector -mtriple=amdgpu9.00-amd-amdhsa -passes=amdgpu-promote-alloca < %s | FileCheck -check-prefix=IR %s +; RUN: llc -disable-promote-alloca-to-vector -mtriple=amdgpu9.00-amd-amdhsa -amdgpu-enable-lower-module-lds=false < %s | FileCheck -check-prefix=ASM %s @all_lds = internal unnamed_addr addrspace(3) global [16384 x i32] poison, align 4 @some_lds = internal unnamed_addr addrspace(3) global [32 x i32] poison, align 4 diff --git a/llvm/test/CodeGen/AMDGPU/promote-alloca-to-lds-icmp.ll b/llvm/test/CodeGen/AMDGPU/promote-alloca-to-lds-icmp.ll index 5ecafe1c1b880..80f3c62827605 100644 --- a/llvm/test/CodeGen/AMDGPU/promote-alloca-to-lds-icmp.ll +++ b/llvm/test/CodeGen/AMDGPU/promote-alloca-to-lds-icmp.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt -S -mtriple=amdgcn-unknown-amdhsa -mcpu=kaveri -passes=amdgpu-promote-alloca < %s | FileCheck %s -; RUN: opt -S -mtriple=amdgcn-unknown-amdhsa -mcpu=kaveri -passes=amdgpu-promote-alloca -disable-promote-alloca-to-lds< %s | FileCheck -check-prefix=NOLDS %s +; RUN: opt -S -mtriple=amdgpu7.00-unknown-amdhsa -passes=amdgpu-promote-alloca < %s | FileCheck %s +; RUN: opt -S -mtriple=amdgpu7.00-unknown-amdhsa -passes=amdgpu-promote-alloca -disable-promote-alloca-to-lds< %s | FileCheck -check-prefix=NOLDS %s ; This normally would be fixed by instcombine to be compare to the GEP ; indices diff --git a/llvm/test/CodeGen/AMDGPU/promote-alloca-to-lds-phi.ll b/llvm/test/CodeGen/AMDGPU/promote-alloca-to-lds-phi.ll index 8f34612735d91..394b79f0afe03 100644 --- a/llvm/test/CodeGen/AMDGPU/promote-alloca-to-lds-phi.ll +++ b/llvm/test/CodeGen/AMDGPU/promote-alloca-to-lds-phi.ll @@ -1,4 +1,4 @@ -; RUN: opt -S -mtriple=amdgcn-unknown-amdhsa -mcpu=kaveri -passes=amdgpu-promote-alloca < %s | FileCheck %s +; RUN: opt -S -mtriple=amdgpu7.00-unknown-amdhsa -passes=amdgpu-promote-alloca < %s | FileCheck %s ; CHECK-LABEL: @branch_ptr_var_same_alloca( diff --git a/llvm/test/CodeGen/AMDGPU/promote-alloca-to-lds-select.ll b/llvm/test/CodeGen/AMDGPU/promote-alloca-to-lds-select.ll index 5607ab51b3653..969033051117e 100644 --- a/llvm/test/CodeGen/AMDGPU/promote-alloca-to-lds-select.ll +++ b/llvm/test/CodeGen/AMDGPU/promote-alloca-to-lds-select.ll @@ -1,4 +1,4 @@ -; RUN: opt -S -mtriple=amdgcn-unknown-amdhsa -mcpu=kaveri -passes=amdgpu-promote-alloca < %s | FileCheck %s +; RUN: opt -S -mtriple=amdgpu7.00-unknown-amdhsa -passes=amdgpu-promote-alloca < %s | FileCheck %s ; CHECK-LABEL: @lds_promoted_alloca_select_invalid_pointer_operand( ; CHECK: %alloca = alloca i32 diff --git a/llvm/test/CodeGen/AMDGPU/promote-alloca-unhandled-intrinsic.ll b/llvm/test/CodeGen/AMDGPU/promote-alloca-unhandled-intrinsic.ll index 1fe1904592a7d..92ccaa837f874 100644 --- a/llvm/test/CodeGen/AMDGPU/promote-alloca-unhandled-intrinsic.ll +++ b/llvm/test/CodeGen/AMDGPU/promote-alloca-unhandled-intrinsic.ll @@ -1,4 +1,4 @@ -; RUN: opt -S -mtriple=amdgcn-unknown-amdhsa -passes=amdgpu-promote-alloca < %s | FileCheck %s +; RUN: opt -S -mtriple=amdgpu-unknown-amdhsa -passes=amdgpu-promote-alloca < %s | FileCheck %s ; This is just an arbitrary intrinisic that shouldn't be ; handled to ensure it doesn't crash. diff --git a/llvm/test/CodeGen/AMDGPU/promote-alloca-use-after-erase.ll b/llvm/test/CodeGen/AMDGPU/promote-alloca-use-after-erase.ll index 48f12ad334020..126276d78678e 100644 --- a/llvm/test/CodeGen/AMDGPU/promote-alloca-use-after-erase.ll +++ b/llvm/test/CodeGen/AMDGPU/promote-alloca-use-after-erase.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6 -; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -passes=amdgpu-promote-alloca %s | FileCheck %s +; RUN: opt -S -mtriple=amdgpu-amd-amdhsa -passes=amdgpu-promote-alloca %s | FileCheck %s define amdgpu_kernel void @kernel(ptr %p) { ; CHECK-LABEL: define amdgpu_kernel void @kernel( diff --git a/llvm/test/CodeGen/AMDGPU/promote-alloca-user-mult.ll b/llvm/test/CodeGen/AMDGPU/promote-alloca-user-mult.ll index 3f21c192553e0..717f29534e37b 100644 --- a/llvm/test/CodeGen/AMDGPU/promote-alloca-user-mult.ll +++ b/llvm/test/CodeGen/AMDGPU/promote-alloca-user-mult.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -passes=amdgpu-promote-alloca < %s | FileCheck %s +; RUN: opt -S -mtriple=amdgpu9.0a-amd-amdhsa -passes=amdgpu-promote-alloca < %s | FileCheck %s ; This tests the case where a memcpy has two pointer operands are promoted to LDS ; See `@llvm.memcpy.p5.p5.i64(... %alloca1, ... %alloca, ...)` below. diff --git a/llvm/test/CodeGen/AMDGPU/promote-alloca-vector-dynamic-idx-bitcasts-llc.ll b/llvm/test/CodeGen/AMDGPU/promote-alloca-vector-dynamic-idx-bitcasts-llc.ll index 03afc774398bf..5321d0cabf947 100644 --- a/llvm/test/CodeGen/AMDGPU/promote-alloca-vector-dynamic-idx-bitcasts-llc.ll +++ b/llvm/test/CodeGen/AMDGPU/promote-alloca-vector-dynamic-idx-bitcasts-llc.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx950 < %s | FileCheck %s --check-prefixes=GFX9 -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 < %s | FileCheck %s --check-prefixes=GFX11 -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 < %s | FileCheck %s --check-prefixes=GFX12 +; RUN: llc -mtriple=amdgpu9.50-amd-amdhsa < %s | FileCheck %s --check-prefixes=GFX9 +; RUN: llc -mtriple=amdgpu11.00-amd-amdhsa < %s | FileCheck %s --check-prefixes=GFX11 +; RUN: llc -mtriple=amdgpu12.00-amd-amdhsa < %s | FileCheck %s --check-prefixes=GFX12 define amdgpu_kernel void @test_bitcast_llc_v128i8_v16i8(ptr addrspace(1) %out, i32 %idx) { ; GFX9-LABEL: test_bitcast_llc_v128i8_v16i8: diff --git a/llvm/test/CodeGen/AMDGPU/promote-alloca-vector-dynamic-idx-bitcasts.ll b/llvm/test/CodeGen/AMDGPU/promote-alloca-vector-dynamic-idx-bitcasts.ll index d8bb5d70cdc5e..3365ca576b112 100644 --- a/llvm/test/CodeGen/AMDGPU/promote-alloca-vector-dynamic-idx-bitcasts.ll +++ b/llvm/test/CodeGen/AMDGPU/promote-alloca-vector-dynamic-idx-bitcasts.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6 -; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -passes=amdgpu-promote-alloca < %s | FileCheck %s +; RUN: opt -S -mtriple=amdgpu-amd-amdhsa -passes=amdgpu-promote-alloca < %s | FileCheck %s define amdgpu_kernel void @test_bitcast_gen_64i8_v16i8(ptr addrspace(1) %out, i32 %idx) #0 { ; CHECK-LABEL: define amdgpu_kernel void @test_bitcast_gen_64i8_v16i8( diff --git a/llvm/test/CodeGen/AMDGPU/promote-alloca-vector-gep-of-gep.ll b/llvm/test/CodeGen/AMDGPU/promote-alloca-vector-gep-of-gep.ll index f95a6a8ec9b45..bc47d6be5926c 100644 --- a/llvm/test/CodeGen/AMDGPU/promote-alloca-vector-gep-of-gep.ll +++ b/llvm/test/CodeGen/AMDGPU/promote-alloca-vector-gep-of-gep.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5 -; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -passes=amdgpu-promote-alloca < %s | FileCheck %s +; RUN: opt -S -mtriple=amdgpu-amd-amdhsa -passes=amdgpu-promote-alloca < %s | FileCheck %s define amdgpu_ps void @scalar_alloca_ptr_with_vector_gep_of_gep(i32 %idx, ptr addrspace(1) %output) #0 { ; CHECK-LABEL: define amdgpu_ps void @scalar_alloca_ptr_with_vector_gep_of_gep( ; CHECK-SAME: i32 [[IDX:%.*]], ptr addrspace(1) [[OUTPUT:%.*]]) #[[ATTR0:[0-9]+]] { diff --git a/llvm/test/CodeGen/AMDGPU/promote-alloca-vector-gep.ll b/llvm/test/CodeGen/AMDGPU/promote-alloca-vector-gep.ll index 4e9c28071c5af..7cc6acb46a243 100644 --- a/llvm/test/CodeGen/AMDGPU/promote-alloca-vector-gep.ll +++ b/llvm/test/CodeGen/AMDGPU/promote-alloca-vector-gep.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5 -; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -passes=amdgpu-promote-alloca < %s | FileCheck %s +; RUN: opt -S -mtriple=amdgpu-amd-amdhsa -passes=amdgpu-promote-alloca < %s | FileCheck %s ; Check that invalid IR is not produced on a vector typed ; getelementptr with a scalar alloca pointer base. diff --git a/llvm/test/CodeGen/AMDGPU/promote-alloca-vector-to-vector.ll b/llvm/test/CodeGen/AMDGPU/promote-alloca-vector-to-vector.ll index e815c41ae7ef4..cb44d2ba4bde6 100644 --- a/llvm/test/CodeGen/AMDGPU/promote-alloca-vector-to-vector.ll +++ b/llvm/test/CodeGen/AMDGPU/promote-alloca-vector-to-vector.ll @@ -1,6 +1,6 @@ -; RUN: llc -mtriple=amdgcn -mcpu=fiji < %s | FileCheck -enable-var-scope -check-prefix=GCN %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -enable-var-scope -check-prefix=GCN %s -; RUN: opt -S -mtriple=amdgcn-- -mcpu=fiji -passes=sroa,amdgpu-promote-alloca < %s | FileCheck -check-prefix=OPT %s +; RUN: llc -mtriple=amdgpu8.03 < %s | FileCheck -enable-var-scope -check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu9.00 < %s | FileCheck -enable-var-scope -check-prefix=GCN %s +; RUN: opt -S -mtriple=amdgpu8.03-- -passes=sroa,amdgpu-promote-alloca < %s | FileCheck -check-prefix=OPT %s ; GCN-LABEL: {{^}}float4_alloca_store4: ; OPT-LABEL: define amdgpu_kernel void @float4_alloca_store4 diff --git a/llvm/test/CodeGen/AMDGPU/promote-alloca-vgpr-ratio.ll b/llvm/test/CodeGen/AMDGPU/promote-alloca-vgpr-ratio.ll index 4bcc46861d66b..4f544162d7220 100644 --- a/llvm/test/CodeGen/AMDGPU/promote-alloca-vgpr-ratio.ll +++ b/llvm/test/CodeGen/AMDGPU/promote-alloca-vgpr-ratio.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5 -; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -passes=amdgpu-promote-alloca -disable-promote-alloca-to-lds=1 < %s | FileCheck --check-prefix=BASE --check-prefix=DEFAULT %s -; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -passes=amdgpu-promote-alloca -disable-promote-alloca-to-lds=1 -amdgpu-promote-alloca-to-vector-vgpr-ratio=2 < %s | FileCheck --check-prefix=BASE %s --check-prefix=RATIO2 -; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -passes=amdgpu-promote-alloca -disable-promote-alloca-to-lds=1 -amdgpu-promote-alloca-to-vector-vgpr-ratio=8 < %s | FileCheck --check-prefix=BASE %s --check-prefix=RATIO8 +; RUN: opt -S -mtriple=amdgpu-amd-amdhsa -passes=amdgpu-promote-alloca -disable-promote-alloca-to-lds=1 < %s | FileCheck --check-prefix=BASE --check-prefix=DEFAULT %s +; RUN: opt -S -mtriple=amdgpu-amd-amdhsa -passes=amdgpu-promote-alloca -disable-promote-alloca-to-lds=1 -amdgpu-promote-alloca-to-vector-vgpr-ratio=2 < %s | FileCheck --check-prefix=BASE %s --check-prefix=RATIO2 +; RUN: opt -S -mtriple=amdgpu-amd-amdhsa -passes=amdgpu-promote-alloca -disable-promote-alloca-to-lds=1 -amdgpu-promote-alloca-to-vector-vgpr-ratio=8 < %s | FileCheck --check-prefix=BASE %s --check-prefix=RATIO8 define amdgpu_kernel void @i32_24_elements(ptr %out) #0 { ; DEFAULT-LABEL: define amdgpu_kernel void @i32_24_elements( diff --git a/llvm/test/CodeGen/AMDGPU/promote-alloca-volatile.ll b/llvm/test/CodeGen/AMDGPU/promote-alloca-volatile.ll index 1cddc528b54e1..9c2e7a9600725 100644 --- a/llvm/test/CodeGen/AMDGPU/promote-alloca-volatile.ll +++ b/llvm/test/CodeGen/AMDGPU/promote-alloca-volatile.ll @@ -1,4 +1,4 @@ -; RUN: opt -S -mtriple=amdgcn-unknown-amdhsa -passes=amdgpu-promote-alloca < %s | FileCheck %s +; RUN: opt -S -mtriple=amdgpu-unknown-amdhsa -passes=amdgpu-promote-alloca < %s | FileCheck %s ; CHECK-LABEL: @volatile_load( ; CHECK: alloca [4 x i32] diff --git a/llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm-gfx10.mir b/llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm-gfx10.mir index 5f52113c2c2bf..920720161d863 100644 --- a/llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm-gfx10.mir +++ b/llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm-gfx10.mir @@ -1,5 +1,5 @@ -# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -verify-machineinstrs -run-pass si-load-store-opt -o - %s | FileCheck -check-prefixes=GCN,GFX10 %s -# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs -run-pass si-load-store-opt -o - %s | FileCheck -check-prefixes=GCN,GFX11 %s +# RUN: llc -mtriple=amdgpu10.10 -verify-machineinstrs -run-pass si-load-store-opt -o - %s | FileCheck -check-prefixes=GCN,GFX10 %s +# RUN: llc -mtriple=amdgpu11.00 -verify-machineinstrs -run-pass si-load-store-opt -o - %s | FileCheck -check-prefixes=GCN,GFX11 %s # GCN-LABEL: name: diffoporder_add # GCN: %{{[0-9]+}}:vreg_64 = GLOBAL_LOAD_DWORDX2 %{{[0-9]+}}, -2048, 0 diff --git a/llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm-gfx12.ll b/llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm-gfx12.ll index 85ccdf81bafa7..d34b60016761e 100644 --- a/llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm-gfx12.ll +++ b/llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm-gfx12.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GFX1250 %s +; RUN: llc -mtriple=amdgpu12.50 < %s | FileCheck -check-prefixes=GFX1250 %s declare void @llvm.amdgcn.global.load.async.to.lds.b128(ptr addrspace(1), ptr addrspace(3), i32, i32) declare i32 @llvm.amdgcn.workitem.id.x() diff --git a/llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm-gfx12.mir b/llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm-gfx12.mir index 5c043eadf6096..30ead36d13e3c 100644 --- a/llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm-gfx12.mir +++ b/llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm-gfx12.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn -mcpu=gfx1250 -start-before=si-load-store-opt -stop-before=si-insert-waitcnts -o - %s | FileCheck -check-prefixes=GFX1250 %s +# RUN: llc -mtriple=amdgpu12.50 -start-before=si-load-store-opt -stop-before=si-insert-waitcnts -o - %s | FileCheck -check-prefixes=GFX1250 %s --- name: promote_async_load_offset diff --git a/llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm-gfx90a.mir b/llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm-gfx90a.mir index 5e0b3139d4dbb..a07763a5ead8a 100644 --- a/llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm-gfx90a.mir +++ b/llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm-gfx90a.mir @@ -1,4 +1,4 @@ -# RUN: llc -mtriple=amdgcn -mcpu=gfx90a -verify-machineinstrs -run-pass si-load-store-opt -o - %s | FileCheck -check-prefix=GFX9 %s +# RUN: llc -mtriple=amdgpu9.0a -verify-machineinstrs -run-pass si-load-store-opt -o - %s | FileCheck -check-prefix=GFX9 %s # GFX9-LABEL: name: diffoporder_add diff --git a/llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.mir b/llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.mir index aa32e21b16939..801cabe164c23 100644 --- a/llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.mir +++ b/llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.mir @@ -1,5 +1,5 @@ -# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass si-load-store-opt -o - %s | FileCheck -check-prefixes=GCN,GFX9 %s -# RUN: llc -mtriple=amdgcn -mcpu=gfx803 -verify-machineinstrs -run-pass si-load-store-opt -o - %s | FileCheck -check-prefixes=GCN,GFX8 %s +# RUN: llc -mtriple=amdgpu9.00 -verify-machineinstrs -run-pass si-load-store-opt -o - %s | FileCheck -check-prefixes=GCN,GFX9 %s +# RUN: llc -mtriple=amdgpu8.03 -verify-machineinstrs -run-pass si-load-store-opt -o - %s | FileCheck -check-prefixes=GCN,GFX8 %s # GCN-LABEL: name: diffoporder_add # GFX9: %{{[0-9]+}}:vreg_64 = GLOBAL_LOAD_DWORDX2 %{{[0-9]+}}, -2048, 0 diff --git a/llvm/test/CodeGen/AMDGPU/promote-vect3-load.ll b/llvm/test/CodeGen/AMDGPU/promote-vect3-load.ll index 81b9222e5101e..ff66ffac5ff43 100644 --- a/llvm/test/CodeGen/AMDGPU/promote-vect3-load.ll +++ b/llvm/test/CodeGen/AMDGPU/promote-vect3-load.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN %s +; RUN: llc -mtriple=amdgpu9.00-amd-amdhsa < %s | FileCheck -check-prefixes=GCN %s ; The type promotion for the vector loads v3i32/v3f32 into v4i32/v4f32 is enabled ; only when the alignment is 8-byte or higher. diff --git a/llvm/test/CodeGen/AMDGPU/propagate-attributes-bitcast-function.ll b/llvm/test/CodeGen/AMDGPU/propagate-attributes-bitcast-function.ll index 4ad68350744ed..e5c798e9188e1 100644 --- a/llvm/test/CodeGen/AMDGPU/propagate-attributes-bitcast-function.ll +++ b/llvm/test/CodeGen/AMDGPU/propagate-attributes-bitcast-function.ll @@ -1,5 +1,5 @@ -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 < %s | FileCheck -check-prefix=GCN %s -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu10.10-amd-amdhsa < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu11.00-amd-amdhsa < %s | FileCheck -check-prefix=GCN %s ; GCN: foo1: ; v_cndmask_b32_e64 v0, 0, 1, vcc_lo{{$}} diff --git a/llvm/test/CodeGen/AMDGPU/propagate-flat-work-group-size.ll b/llvm/test/CodeGen/AMDGPU/propagate-flat-work-group-size.ll index e71eddbd7077a..4a14d2ddda4cd 100644 --- a/llvm/test/CodeGen/AMDGPU/propagate-flat-work-group-size.ll +++ b/llvm/test/CodeGen/AMDGPU/propagate-flat-work-group-size.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --check-globals -; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -passes=amdgpu-attributor %s | FileCheck %s +; RUN: opt -S -mtriple=amdgpu-amd-amdhsa -passes=amdgpu-attributor %s | FileCheck %s ; Check propagation of amdgpu-flat-work-group-size attribute. diff --git a/llvm/test/CodeGen/AMDGPU/propagate-waves-per-eu.ll b/llvm/test/CodeGen/AMDGPU/propagate-waves-per-eu.ll index a19fe155d1c0e..e69d9b182f649 100644 --- a/llvm/test/CodeGen/AMDGPU/propagate-waves-per-eu.ll +++ b/llvm/test/CodeGen/AMDGPU/propagate-waves-per-eu.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-attributes --check-globals --version 2 -; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -passes=amdgpu-attributor %s | FileCheck %s +; RUN: opt -S -mtriple=amdgpu-amd-amdhsa -passes=amdgpu-attributor %s | FileCheck %s ; Check propagation of amdgpu-flat-work-group-size attribute. diff --git a/llvm/test/CodeGen/AMDGPU/ps-shader-arg-count.ll b/llvm/test/CodeGen/AMDGPU/ps-shader-arg-count.ll index a466df21a5e71..a17945b6ddf22 100644 --- a/llvm/test/CodeGen/AMDGPU/ps-shader-arg-count.ll +++ b/llvm/test/CodeGen/AMDGPU/ps-shader-arg-count.ll @@ -1,7 +1,7 @@ -;RUN: llc -global-isel=1 < %s -mtriple=amdgcn-pal -mcpu=gfx1010 | FileCheck %s --check-prefixes=CHECK -;RUN: llc -global-isel=1 < %s -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 | FileCheck %s --check-prefixes=CHECK -;RUN: llc -global-isel=0 < %s -mtriple=amdgcn-pal -mcpu=gfx1010 | FileCheck %s --check-prefixes=CHECK -;RUN: llc -global-isel=0 < %s -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 | FileCheck %s --check-prefixes=CHECK +;RUN: llc -global-isel=1 < %s -mtriple=amdgpu10.10-pal | FileCheck %s --check-prefixes=CHECK +;RUN: llc -global-isel=1 < %s -mtriple=amdgpu10.10-mesa-mesa3d | FileCheck %s --check-prefixes=CHECK +;RUN: llc -global-isel=0 < %s -mtriple=amdgpu10.10-pal | FileCheck %s --check-prefixes=CHECK +;RUN: llc -global-isel=0 < %s -mtriple=amdgpu10.10-mesa-mesa3d | FileCheck %s --check-prefixes=CHECK ; ;CHECK-LABEL: {{^}}_amdgpu_ps_1_arg: ; ;CHECK: NumVgprs: 4 diff --git a/llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.ll b/llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.ll index 728966b6c3cbb..aa80c946124a4 100644 --- a/llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.ll +++ b/llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG %s -; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL %s -; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=fiji < %s | FileCheck -check-prefixes=GCN-GISEL %s +; RUN: llc -global-isel=0 -mtriple=amdgpu12.00 < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG %s +; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgpu12.00 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL %s +; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgpu8.03 < %s | FileCheck -check-prefixes=GCN-GISEL %s ; TODO: GlobalISel should avoid generating v_ldexp_f32. define amdgpu_cs float @v_s_exp_f32(float inreg %src) { diff --git a/llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.mir b/llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.mir index 19681a4346a13..1c03ca70af8c5 100644 --- a/llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.mir +++ b/llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.mir @@ -1,6 +1,6 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 -# RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx1170 -run-pass=si-fold-operands -verify-machineinstrs -o - %s | FileCheck --check-prefixes=GCN %s -# RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx1200 -run-pass=si-fold-operands -verify-machineinstrs -o - %s | FileCheck --check-prefixes=GCN %s +# RUN: llc -mtriple=amdgpu11.70-amd-amdpal -run-pass=si-fold-operands -verify-machineinstrs -o - %s | FileCheck --check-prefixes=GCN %s +# RUN: llc -mtriple=amdgpu12.00-amd-amdpal -run-pass=si-fold-operands -verify-machineinstrs -o - %s | FileCheck --check-prefixes=GCN %s # Do not use inline constants for f16 pseudo scalar transcendentals. # But allow literal constants. diff --git a/llvm/test/CodeGen/AMDGPU/ptr-arg-dbg-value.ll b/llvm/test/CodeGen/AMDGPU/ptr-arg-dbg-value.ll index f4c759842b920..581684095aeb6 100644 --- a/llvm/test/CodeGen/AMDGPU/ptr-arg-dbg-value.ll +++ b/llvm/test/CodeGen/AMDGPU/ptr-arg-dbg-value.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 < %s | FileCheck %s +; RUN: llc -mtriple=amdgpu9.08-amd-amdhsa < %s | FileCheck %s %struct.A = type { [100 x i32] } diff --git a/llvm/test/CodeGen/AMDGPU/ptr-buffer-alias-scheduling.ll b/llvm/test/CodeGen/AMDGPU/ptr-buffer-alias-scheduling.ll index 4355495621593..ac5abf1ab0c3b 100644 --- a/llvm/test/CodeGen/AMDGPU/ptr-buffer-alias-scheduling.ll +++ b/llvm/test/CodeGen/AMDGPU/ptr-buffer-alias-scheduling.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 -; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx900 | FileCheck %s --check-prefixes=SDAG -; RUN: llc < %s -global-isel -mtriple=amdgcn -mcpu=gfx900 | FileCheck %s --check-prefixes=GISEL +; RUN: llc < %s -mtriple=amdgpu9.00 | FileCheck %s --check-prefixes=SDAG +; RUN: llc < %s -global-isel -mtriple=amdgpu9.00 | FileCheck %s --check-prefixes=GISEL define amdgpu_kernel void @buffers_dont_alias(ptr addrspace(8) noalias %a, ptr addrspace(8) noalias %b) { ; SDAG-LABEL: buffers_dont_alias: diff --git a/llvm/test/CodeGen/AMDGPU/ptradd-sdag-mubuf.ll b/llvm/test/CodeGen/AMDGPU/ptradd-sdag-mubuf.ll index 40f39a24d7a99..b6facd94b0f2d 100644 --- a/llvm/test/CodeGen/AMDGPU/ptradd-sdag-mubuf.ll +++ b/llvm/test/CodeGen/AMDGPU/ptradd-sdag-mubuf.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=tahiti < %s | FileCheck --check-prefixes=GFX6 %s +; RUN: llc -mtriple=amdgpu6.00-amd-amdhsa < %s | FileCheck --check-prefixes=GFX6 %s ; Test PTRADD handling in AMDGPUDAGToDAGISel::SelectMUBUF. diff --git a/llvm/test/CodeGen/AMDGPU/ptradd-sdag-optimizations.ll b/llvm/test/CodeGen/AMDGPU/ptradd-sdag-optimizations.ll index fba7720b37bf6..79cd8d6fb05d2 100644 --- a/llvm/test/CodeGen/AMDGPU/ptradd-sdag-optimizations.ll +++ b/llvm/test/CodeGen/AMDGPU/ptradd-sdag-optimizations.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 -disable-separate-const-offset-from-gep=1 < %s | FileCheck --check-prefixes=GFX942 %s +; RUN: llc -mtriple=amdgpu9.42-amd-amdhsa -disable-separate-const-offset-from-gep=1 < %s | FileCheck --check-prefixes=GFX942 %s ; Tests for DAG combines and folds related to the ISD::PTRADD SelectionDAG ; opcode. The RUN lines uses -disable-separate-const-offset-from-gep to disable diff --git a/llvm/test/CodeGen/AMDGPU/ptradd-sdag-undef-poison.ll b/llvm/test/CodeGen/AMDGPU/ptradd-sdag-undef-poison.ll index e7c715f0a38bf..082bd654504a2 100644 --- a/llvm/test/CodeGen/AMDGPU/ptradd-sdag-undef-poison.ll +++ b/llvm/test/CodeGen/AMDGPU/ptradd-sdag-undef-poison.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 -start-before=amdgpu-isel < %s | FileCheck --check-prefixes=GFX942 %s +; RUN: llc -mtriple=amdgpu9.42-amd-amdhsa -start-before=amdgpu-isel < %s | FileCheck --check-prefixes=GFX942 %s ; Tests for undef and poison DAG folds for the ISD::PTRADD SelectionDAG opcode. ; If any additions are generated for these tests, the folds don't work. diff --git a/llvm/test/CodeGen/AMDGPU/ptradd-sdag.ll b/llvm/test/CodeGen/AMDGPU/ptradd-sdag.ll index 5a0ab4ef7b42b..42b4282dc2c5c 100644 --- a/llvm/test/CodeGen/AMDGPU/ptradd-sdag.ll +++ b/llvm/test/CodeGen/AMDGPU/ptradd-sdag.ll @@ -1,9 +1,9 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji < %s | FileCheck %s -check-prefixes=GFX8 -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 < %s | FileCheck %s -check-prefixes=GFX942 -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1030 < %s | FileCheck %s -check-prefixes=GFX10 -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 < %s | FileCheck %s -check-prefixes=GFX11 -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 < %s | FileCheck %s -check-prefixes=GFX12 +; RUN: llc -mtriple=amdgpu8.03-amd-amdhsa < %s | FileCheck %s -check-prefixes=GFX8 +; RUN: llc -mtriple=amdgpu9.42-amd-amdhsa < %s | FileCheck %s -check-prefixes=GFX942 +; RUN: llc -mtriple=amdgpu10.30-amd-amdhsa < %s | FileCheck %s -check-prefixes=GFX10 +; RUN: llc -mtriple=amdgpu11.00-amd-amdhsa < %s | FileCheck %s -check-prefixes=GFX11 +; RUN: llc -mtriple=amdgpu12.00-amd-amdhsa < %s | FileCheck %s -check-prefixes=GFX12 ; Tests for the ISD::PTRADD SelectionDAG opcode. This only tests 64-bit address ; spaces since PTRADD is currently only used for these. diff --git a/llvm/test/CodeGen/AMDGPU/ptrmask.ll b/llvm/test/CodeGen/AMDGPU/ptrmask.ll index 17c4eaa2736f4..c720ebe74303d 100644 --- a/llvm/test/CodeGen/AMDGPU/ptrmask.ll +++ b/llvm/test/CodeGen/AMDGPU/ptrmask.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 -; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -o - %s | FileCheck -check-prefix=GCN %s -; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -o - %s | FileCheck -check-prefixes=GFX10PLUS,GFX10 %s -; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 -o - %s | FileCheck -check-prefixes=GFX10PLUS,GFX11 %s +; RUN: llc -mtriple=amdgpu9.00-mesa-mesa3d -o - %s | FileCheck -check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu10.10-mesa-mesa3d -o - %s | FileCheck -check-prefixes=GFX10PLUS,GFX10 %s +; RUN: llc -mtriple=amdgpu11.00-mesa-mesa3d -amdgpu-enable-delay-alu=0 -o - %s | FileCheck -check-prefixes=GFX10PLUS,GFX11 %s define ptr addrspace(1) @v_ptrmask_global_variable_i64(ptr addrspace(1) %ptr, i64 %mask) { ; GCN-LABEL: v_ptrmask_global_variable_i64: diff --git a/llvm/test/CodeGen/AMDGPU/ra-inserted-scalar-instructions.mir b/llvm/test/CodeGen/AMDGPU/ra-inserted-scalar-instructions.mir index a781cfcd3f9ec..c670df94f616e 100644 --- a/llvm/test/CodeGen/AMDGPU/ra-inserted-scalar-instructions.mir +++ b/llvm/test/CodeGen/AMDGPU/ra-inserted-scalar-instructions.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4 -# RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx1030 -run-pass=greedy --stress-regalloc=6 --verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s +# RUN: llc -mtriple=amdgpu10.30-amd-amdpal -run-pass=greedy --stress-regalloc=6 --verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s # The spills/copies during RA for scalar register block LiveIns should be inserted at the beginning of the block. # The COPY inserted in bb.9 during liverange split should precede the SPILL that was inserted earlier in the flow. diff --git a/llvm/test/CodeGen/AMDGPU/ran-out-of-registers-error-all-regs-reserved.ll b/llvm/test/CodeGen/AMDGPU/ran-out-of-registers-error-all-regs-reserved.ll index 06c862c7fb481..0825688cb03c0 100644 --- a/llvm/test/CodeGen/AMDGPU/ran-out-of-registers-error-all-regs-reserved.ll +++ b/llvm/test/CodeGen/AMDGPU/ran-out-of-registers-error-all-regs-reserved.ll @@ -1,6 +1,6 @@ -; RUN: not llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -vgpr-regalloc=greedy -filetype=null %s 2>&1 | FileCheck -implicit-check-not=error %s -; RUN: not llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -vgpr-regalloc=basic -filetype=null %s 2>&1 | FileCheck -implicit-check-not=error %s -; RUN: not llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -vgpr-regalloc=fast -filetype=null %s 2>&1 | FileCheck -implicit-check-not=error %s +; RUN: not llc -mtriple=amdgpu9.08-amd-amdhsa -vgpr-regalloc=greedy -filetype=null %s 2>&1 | FileCheck -implicit-check-not=error %s +; RUN: not llc -mtriple=amdgpu9.08-amd-amdhsa -vgpr-regalloc=basic -filetype=null %s 2>&1 | FileCheck -implicit-check-not=error %s +; RUN: not llc -mtriple=amdgpu9.08-amd-amdhsa -vgpr-regalloc=fast -filetype=null %s 2>&1 | FileCheck -implicit-check-not=error %s declare <32 x i32> @llvm.amdgcn.mfma.i32.32x32x4i8(i32, i32, <32 x i32>, i32 immarg, i32 immarg, i32 immarg) diff --git a/llvm/test/CodeGen/AMDGPU/ran-out-of-registers-errors.ll b/llvm/test/CodeGen/AMDGPU/ran-out-of-registers-errors.ll index d27f45f5813db..1d23b1fd5e30f 100644 --- a/llvm/test/CodeGen/AMDGPU/ran-out-of-registers-errors.ll +++ b/llvm/test/CodeGen/AMDGPU/ran-out-of-registers-errors.ll @@ -6,7 +6,7 @@ ; RUN: not llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -stress-regalloc=1 -vgpr-regalloc=basic -filetype=null %t.bc 2>&1 | FileCheck -implicit-check-not=error -check-prefixes=DBGINFO-CHECK,DBGINFO-BASIC %s ; FIXME: Asserts when using -O2 + -vgpr-regalloc=fast -; RUN: not llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -stress-regalloc=1 -O0 -filetype=null %t.bc 2>&1 | FileCheck -implicit-check-not=error -check-prefixes=DBGINFO-CHECK,DBGINFO-FAST %s +; RUN: not llc -mtriple=amdgpu9.08-amd-amdhsa -stress-regalloc=1 -O0 -filetype=null %t.bc 2>&1 | FileCheck -implicit-check-not=error -check-prefixes=DBGINFO-CHECK,DBGINFO-FAST %s ; TODO: Should we fix emitting multiple errors sometimes in basic and fast? diff --git a/llvm/test/CodeGen/AMDGPU/ran-out-of-sgprs-allocation-failure.mir b/llvm/test/CodeGen/AMDGPU/ran-out-of-sgprs-allocation-failure.mir index 273cc7a50085a..7ecbecec82898 100644 --- a/llvm/test/CodeGen/AMDGPU/ran-out-of-sgprs-allocation-failure.mir +++ b/llvm/test/CodeGen/AMDGPU/ran-out-of-sgprs-allocation-failure.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -verify-regalloc -start-before=greedy,0 -stop-after=virtregrewriter,0 -greedy-regclass-priority-trumps-globalness=1 -o - %s | FileCheck %s +# RUN: llc -mtriple=amdgpu9.0a-amd-amdhsa -verify-regalloc -start-before=greedy,0 -stop-after=virtregrewriter,0 -greedy-regclass-priority-trumps-globalness=1 -o - %s | FileCheck %s # The allocation would previously fail due to poor ordering based on # register class. The super wide tuples should be allocated first so diff --git a/llvm/test/CodeGen/AMDGPU/rcp-pattern.ll b/llvm/test/CodeGen/AMDGPU/rcp-pattern.ll index 26f2b3d2af60d..107bff7d452db 100644 --- a/llvm/test/CodeGen/AMDGPU/rcp-pattern.ll +++ b/llvm/test/CodeGen/AMDGPU/rcp-pattern.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 -; RUN: llc -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefixes=GCN,SI %s -; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=GCN,VI %s +; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck -check-prefixes=GCN,SI %s +; RUN: llc -mtriple=amdgpu8.02 < %s | FileCheck -check-prefixes=GCN,VI %s ; RUN: llc -mtriple=r600 -mcpu=cypress < %s | FileCheck -check-prefixes=R600,EG %s ; RUN: llc -mtriple=r600 -mcpu=cayman < %s | FileCheck -check-prefixes=R600,CM %s diff --git a/llvm/test/CodeGen/AMDGPU/read-register-invalid-register.ll b/llvm/test/CodeGen/AMDGPU/read-register-invalid-register.ll index 28f9ca8d6576f..d6069614b9b19 100644 --- a/llvm/test/CodeGen/AMDGPU/read-register-invalid-register.ll +++ b/llvm/test/CodeGen/AMDGPU/read-register-invalid-register.ll @@ -1,5 +1,5 @@ -; RUN: not llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx900 -filetype=null < %s 2>&1 | FileCheck --implicit-check-not=error %s -; RUN: not llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx900 -filetype=null < %s 2>&1 | FileCheck --implicit-check-not=error %s +; RUN: not llc -global-isel=0 -mtriple=amdgpu9.00 -filetype=null < %s 2>&1 | FileCheck --implicit-check-not=error %s +; RUN: not llc -global-isel=1 -mtriple=amdgpu9.00 -filetype=null < %s 2>&1 | FileCheck --implicit-check-not=error %s declare i32 @llvm.read_register.i32(metadata) #0 diff --git a/llvm/test/CodeGen/AMDGPU/read-register-invalid-subtarget.ll b/llvm/test/CodeGen/AMDGPU/read-register-invalid-subtarget.ll index bc26e1c27ce78..5a5a0710d34a1 100644 --- a/llvm/test/CodeGen/AMDGPU/read-register-invalid-subtarget.ll +++ b/llvm/test/CodeGen/AMDGPU/read-register-invalid-subtarget.ll @@ -1,4 +1,4 @@ -; RUN: not llc -mtriple=amdgcn -mcpu=tahiti < %s 2>&1 | FileCheck %s +; RUN: not llc -mtriple=amdgpu6.00 < %s 2>&1 | FileCheck %s ; CHECK: error: invalid register "flat_scratch_lo" for subtarget. diff --git a/llvm/test/CodeGen/AMDGPU/read-write-register-illegal-type.ll b/llvm/test/CodeGen/AMDGPU/read-write-register-illegal-type.ll index 2324f3f16b194..40a258dac3fde 100644 --- a/llvm/test/CodeGen/AMDGPU/read-write-register-illegal-type.ll +++ b/llvm/test/CodeGen/AMDGPU/read-write-register-illegal-type.ll @@ -1,4 +1,4 @@ -; RUN: not llc -mtriple=amdgcn -mcpu=gfx900 -filetype=null %s 2>&1 | FileCheck %s +; RUN: not llc -mtriple=amdgpu9.00 -filetype=null %s 2>&1 | FileCheck %s ; CHECK: error: <unknown>:0:0: cannot use llvm.read_register with illegal type define amdgpu_kernel void @test_read_register_i9(ptr addrspace(1) %out) nounwind { diff --git a/llvm/test/CodeGen/AMDGPU/read_register.ll b/llvm/test/CodeGen/AMDGPU/read_register.ll index f6a5af55840ac..f58aefeffd66d 100644 --- a/llvm/test/CodeGen/AMDGPU/read_register.ll +++ b/llvm/test/CodeGen/AMDGPU/read_register.ll @@ -1,5 +1,5 @@ -; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=bonaire < %s | FileCheck %s -; RUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdhsa -mcpu=bonaire < %s | FileCheck %s +; RUN: llc -global-isel=0 -mtriple=amdgpu7.04-amd-amdhsa < %s | FileCheck %s +; RUN: llc -global-isel=1 -mtriple=amdgpu7.04-amd-amdhsa < %s | FileCheck %s declare i32 @llvm.read_register.i32(metadata) #0 declare i64 @llvm.read_register.i64(metadata) #0 diff --git a/llvm/test/CodeGen/AMDGPU/readcyclecounter.ll b/llvm/test/CodeGen/AMDGPU/readcyclecounter.ll index f67cbe381bfad..2af86f7f01172 100644 --- a/llvm/test/CodeGen/AMDGPU/readcyclecounter.ll +++ b/llvm/test/CodeGen/AMDGPU/readcyclecounter.ll @@ -1,17 +1,17 @@ -; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefix=MEMTIME -check-prefix=SIVI -check-prefix=GCN %s +; RUN: llc -global-isel=0 -mtriple=amdgpu6.00 < %s | FileCheck -check-prefix=MEMTIME -check-prefix=SIVI -check-prefix=GCN %s ; -global-isel=1 SI run line skipped since store not yet implemented. -; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=MEMTIME -check-prefix=SIVI -check-prefix=GCN %s -; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=MEMTIME -check-prefix=SIVI -check-prefix=GCN %s -; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefix=MEMTIME -check-prefix=GCN %s -; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefix=MEMTIME -check-prefix=GCN %s -; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1030 < %s | FileCheck -check-prefixes=MEMTIME -check-prefix=GCN %s -; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1030 < %s | FileCheck -check-prefixes=MEMTIME -check-prefix=GCN %s -; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -amdgpu-enable-vopd=0 < %s | FileCheck -check-prefixes=GETREG,GETREG-SDAG -check-prefix=GCN %s -; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 -amdgpu-enable-vopd=0 < %s | FileCheck -check-prefixes=GETREG,GETREG-GISEL -check-prefix=GCN %s -; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GCN,GFX12 %s -; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GCN,GFX12 %s -; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GCN,GFX1250 %s -; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GCN,GFX1250 %s +; RUN: llc -global-isel=0 -mtriple=amdgpu8.02 < %s | FileCheck -check-prefix=MEMTIME -check-prefix=SIVI -check-prefix=GCN %s +; RUN: llc -global-isel=1 -mtriple=amdgpu8.02 < %s | FileCheck -check-prefix=MEMTIME -check-prefix=SIVI -check-prefix=GCN %s +; RUN: llc -global-isel=0 -mtriple=amdgpu10.10 < %s | FileCheck -check-prefix=MEMTIME -check-prefix=GCN %s +; RUN: llc -global-isel=1 -mtriple=amdgpu10.10 < %s | FileCheck -check-prefix=MEMTIME -check-prefix=GCN %s +; RUN: llc -global-isel=0 -mtriple=amdgpu10.30 < %s | FileCheck -check-prefixes=MEMTIME -check-prefix=GCN %s +; RUN: llc -global-isel=1 -mtriple=amdgpu10.30 < %s | FileCheck -check-prefixes=MEMTIME -check-prefix=GCN %s +; RUN: llc -global-isel=0 -mtriple=amdgpu11.00 -amdgpu-enable-vopd=0 < %s | FileCheck -check-prefixes=GETREG,GETREG-SDAG -check-prefix=GCN %s +; RUN: llc -global-isel=1 -mtriple=amdgpu11.00 -amdgpu-enable-vopd=0 < %s | FileCheck -check-prefixes=GETREG,GETREG-GISEL -check-prefix=GCN %s +; RUN: llc -global-isel=0 -mtriple=amdgpu12.00 < %s | FileCheck -check-prefixes=GCN,GFX12 %s +; RUN: llc -global-isel=1 -mtriple=amdgpu12.00 < %s | FileCheck -check-prefixes=GCN,GFX12 %s +; RUN: llc -global-isel=0 -mtriple=amdgpu12.50 < %s | FileCheck -check-prefixes=GCN,GFX1250 %s +; RUN: llc -global-isel=1 -mtriple=amdgpu12.50 < %s | FileCheck -check-prefixes=GCN,GFX1250 %s declare i64 @llvm.readcyclecounter() #0 diff --git a/llvm/test/CodeGen/AMDGPU/readlane_exec0.mir b/llvm/test/CodeGen/AMDGPU/readlane_exec0.mir index 86685c265dff3..fe0dfd2eba37e 100644 --- a/llvm/test/CodeGen/AMDGPU/readlane_exec0.mir +++ b/llvm/test/CodeGen/AMDGPU/readlane_exec0.mir @@ -1,5 +1,5 @@ -# RUN: llc -o - %s -mtriple=amdgcn -mcpu=fiji -run-pass=si-late-branch-lowering -verify-machineinstrs | FileCheck -check-prefix=GCN %s -# RUN: llc -o - %s -mtriple=amdgcn -mcpu=fiji -passes=si-late-branch-lowering | FileCheck -check-prefix=GCN %s +# RUN: llc -o - %s -mtriple=amdgpu8.03 -run-pass=si-late-branch-lowering -verify-machineinstrs | FileCheck -check-prefix=GCN %s +# RUN: llc -o - %s -mtriple=amdgpu8.03 -passes=si-late-branch-lowering | FileCheck -check-prefix=GCN %s # GCN-LABEL: readlane_exec0 # GCN: bb.0 diff --git a/llvm/test/CodeGen/AMDGPU/readsteadycounter.ll b/llvm/test/CodeGen/AMDGPU/readsteadycounter.ll index ddbae6493aceb..e4d99de1a1391 100644 --- a/llvm/test/CodeGen/AMDGPU/readsteadycounter.ll +++ b/llvm/test/CodeGen/AMDGPU/readsteadycounter.ll @@ -1,8 +1,8 @@ -; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx700 < %s | FileCheck %s -check-prefixes=GCN,GFX700 -; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck %s -check-prefixes=GCN,GFX900 -; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck %s -check-prefixes=GCN,GFX900 -; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck %s -check-prefixes=GCN,GFX1100 -; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck %s -check-prefixes=GCN,GFX1100 +; RUN: llc -global-isel=0 -mtriple=amdgpu7.00 < %s | FileCheck %s -check-prefixes=GCN,GFX700 +; RUN: llc -global-isel=0 -mtriple=amdgpu9.00 < %s | FileCheck %s -check-prefixes=GCN,GFX900 +; RUN: llc -global-isel=1 -mtriple=amdgpu9.00 < %s | FileCheck %s -check-prefixes=GCN,GFX900 +; RUN: llc -global-isel=0 -mtriple=amdgpu11.00 < %s | FileCheck %s -check-prefixes=GCN,GFX1100 +; RUN: llc -global-isel=1 -mtriple=amdgpu11.00 < %s | FileCheck %s -check-prefixes=GCN,GFX1100 declare i64 @llvm.readsteadycounter() #0 diff --git a/llvm/test/CodeGen/AMDGPU/reassoc-mul-add-1-to-mad.ll b/llvm/test/CodeGen/AMDGPU/reassoc-mul-add-1-to-mad.ll index 13d43c2d00835..b6c99d75ee4b3 100644 --- a/llvm/test/CodeGen/AMDGPU/reassoc-mul-add-1-to-mad.ll +++ b/llvm/test/CodeGen/AMDGPU/reassoc-mul-add-1-to-mad.ll @@ -1,14 +1,14 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 -; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx600 < %s | FileCheck -check-prefixes=GFX67,GFX6 %s -; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx700 < %s | FileCheck -check-prefixes=GFX67,GFX7 %s -; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx803 < %s | FileCheck -check-prefixes=GFX8 %s -; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX9,GFX900 %s -; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx90a < %s | FileCheck -check-prefixes=GFX9,GFX90A %s -; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx1030 < %s | FileCheck -check-prefixes=GFX10 %s -; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx1250 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-FAKE16 %s -; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx1250 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-REAL16 %s -; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx1310 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX13,GFX13-FAKE16 %s -; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx1310 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX13,GFX13-REAL16 %s +; RUN: llc -mtriple=amdgpu6.00-amd-amdpal < %s | FileCheck -check-prefixes=GFX67,GFX6 %s +; RUN: llc -mtriple=amdgpu7.00-amd-amdpal < %s | FileCheck -check-prefixes=GFX67,GFX7 %s +; RUN: llc -mtriple=amdgpu8.03-amd-amdpal < %s | FileCheck -check-prefixes=GFX8 %s +; RUN: llc -mtriple=amdgpu9.00-amd-amdpal < %s | FileCheck -check-prefixes=GFX9,GFX900 %s +; RUN: llc -mtriple=amdgpu9.0a-amd-amdpal < %s | FileCheck -check-prefixes=GFX9,GFX90A %s +; RUN: llc -mtriple=amdgpu10.30-amd-amdpal < %s | FileCheck -check-prefixes=GFX10 %s +; RUN: llc -mtriple=amdgpu12.50-amd-amdpal -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-FAKE16 %s +; RUN: llc -mtriple=amdgpu12.50-amd-amdpal -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-REAL16 %s +; RUN: llc -mtriple=amdgpu13.10-amd-amdpal -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX13,GFX13-FAKE16 %s +; RUN: llc -mtriple=amdgpu13.10-amd-amdpal -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX13,GFX13-REAL16 %s ; We want to undo these canonicalizations to enable mad matching: ; (x * y) + x --> x * (y + 1) diff --git a/llvm/test/CodeGen/AMDGPU/reassoc-scalar.ll b/llvm/test/CodeGen/AMDGPU/reassoc-scalar.ll index 8da7c293e4ea2..97c02293f492f 100644 --- a/llvm/test/CodeGen/AMDGPU/reassoc-scalar.ll +++ b/llvm/test/CodeGen/AMDGPU/reassoc-scalar.ll @@ -1,5 +1,5 @@ -; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=GCN,GFX8 %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9 %s +; RUN: llc -mtriple=amdgpu8.02 < %s | FileCheck -check-prefixes=GCN,GFX8 %s +; RUN: llc -mtriple=amdgpu9.00 < %s | FileCheck -check-prefixes=GCN,GFX9 %s ; GCN-LABEL: reassoc_i32: ; GCN: s_add_i32 [[ADD1:s[0-9]+]], s{{[0-9]+}}, s{{[0-9]+}} diff --git a/llvm/test/CodeGen/AMDGPU/recursion.ll b/llvm/test/CodeGen/AMDGPU/recursion.ll index f1ccbe57dd50f..acbe592fd6d29 100644 --- a/llvm/test/CodeGen/AMDGPU/recursion.ll +++ b/llvm/test/CodeGen/AMDGPU/recursion.ll @@ -1,6 +1,6 @@ -; RUN: sed 's/CODE_OBJECT_VERSION/400/g' %s | llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 | FileCheck %s -; RUN: sed 's/CODE_OBJECT_VERSION/500/g' %s | llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 | FileCheck -check-prefixes=V5 %s -; RUN: sed 's/CODE_OBJECT_VERSION/600/g' %s | llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 | FileCheck -check-prefixes=V5 %s +; RUN: sed 's/CODE_OBJECT_VERSION/400/g' %s | llc -mtriple=amdgpu9.00-amd-amdhsa | FileCheck %s +; RUN: sed 's/CODE_OBJECT_VERSION/500/g' %s | llc -mtriple=amdgpu9.00-amd-amdhsa | FileCheck -check-prefixes=V5 %s +; RUN: sed 's/CODE_OBJECT_VERSION/600/g' %s | llc -mtriple=amdgpu9.00-amd-amdhsa | FileCheck -check-prefixes=V5 %s ; CHECK-LABEL: {{^}}recursive: ; CHECK: .set .Lrecursive.private_seg_size, 16+max(16384) diff --git a/llvm/test/CodeGen/AMDGPU/recursive-resource-usage-mcexpr.ll b/llvm/test/CodeGen/AMDGPU/recursive-resource-usage-mcexpr.ll index cd85c836df81b..b26e2784fab17 100644 --- a/llvm/test/CodeGen/AMDGPU/recursive-resource-usage-mcexpr.ll +++ b/llvm/test/CodeGen/AMDGPU/recursive-resource-usage-mcexpr.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a < %s | FileCheck %s +; RUN: llc -mtriple=amdgpu9.0a-amd-amdhsa < %s | FileCheck %s ; Recursion: foo -> bar -> baz -> qux -> foo diff --git a/llvm/test/CodeGen/AMDGPU/recursive_global_initializer.ll b/llvm/test/CodeGen/AMDGPU/recursive_global_initializer.ll index c8b2603b689e3..b6820ea6bca3c 100644 --- a/llvm/test/CodeGen/AMDGPU/recursive_global_initializer.ll +++ b/llvm/test/CodeGen/AMDGPU/recursive_global_initializer.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals --version 2 -; RUN: opt -mtriple=amdgcn-amd-amdhsa -passes=amdgpu-attributor -S %s | FileCheck %s +; RUN: opt -mtriple=amdgpu-amd-amdhsa -passes=amdgpu-attributor -S %s | FileCheck %s %struct.foo = type { %struct.pluto, ptr, i64 } %struct.pluto = type { [512 x i8], ptr } _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
