llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-backend-amdgpu Author: Matt Arsenault (arsenm) <details> <summary>Changes</summary> Mechanically migrate the command-line target spelling on llc/opt RUN lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the redundant -mcpu. Co-Authored-By: Claude <noreply@<!-- -->anthropic.com> (Claude-Opus-4.8) --- Patch is 130.44 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/209734.diff 100 Files Affected: - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir (+14-14) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir (+16-16) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-local.mir (+16-16) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-memory-metadata.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir (+16-16) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-store-s16-true16.mir (+4-4) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-lshr.mir (+5-5) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-merge-values.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-mul.mir (+6-6) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-phi.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ptr-add.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ptrmask.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-rotl-rotr.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sadde.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-saddo.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-saddsat.mir (+5-5) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sbfx.mir (+3-3) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sdiv.mir (+5-5) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-select.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sext-inreg.mir (+5-5) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sext.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-constant-32bit.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-flat.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-global.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-local.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-private.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-s16-true16.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shl.mir (+5-5) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shuffle-vector.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shuffle-vector.s16.mir (+4-4) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sitofp.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smax.mir (+6-6) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smin.mir (+6-6) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smulh.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smulo.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-srem.mir (+5-5) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sshlsat.mir (+5-5) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssube.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssubo.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssubsat.mir (+5-5) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store-global.mir (+9-9) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-strict_fsub.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sub.mir (+5-5) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-trap-gfx11.mir (+3-3) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-trap.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-trunc.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uadde.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uaddo.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uaddsat.mir (+5-5) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ubfx.mir (+3-3) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-udiv.mir (+5-5) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uitofp.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umax.mir (+6-6) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umin.mir (+6-6) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umulh.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umulo.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-urem.mir (+5-5) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ushlsat.mir (+5-5) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-usube.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-usubo.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-usubsat.mir (+5-5) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-vector-args-gfx7.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-vector-args-gfx8-plus.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-xor.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zext.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-constant-32bit.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-flat.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-global.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-local.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-private.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.abs.ll (+5-5) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ballot.i32.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ballot.i64.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.dispatch.ptr.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.fmas.ll (+6-6) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.scale.ll (+4-4) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i32.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i64.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.fdot2.ll (+4-4) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.fmul.legacy.ll (+6-6) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.fract.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.frexp.mant.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.if.break.i32.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.if.break.i64.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.atomic.dim.a16.ll (+4-4) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.atomic.dim.ll (+7-7) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.atomic.dim.mir (+5-5) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.a16.dim.ll (+4-4) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.dim.ll (+4-4) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.o.dim.ll (+3-3) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.getresinfo.a16.ll (+4-4) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.getresinfo.ll (+5-5) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.1d.d16.ll (+6-6) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.1d.ll (+6-6) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.2d.ll (+4-4) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.2darraymsaa.a16.ll (+4-4) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.2darraymsaa.ll (+4-4) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.3d.a16.ll (+4-4) ``````````diff diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir index aad9176c7be8e..8a17decb4e998 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir @@ -1,18 +1,18 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=bonaire -O0 -run-pass=legalizer %s -o - | FileCheck -check-prefix=CI %s -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -O0 -run-pass=legalizer %s -o - | FileCheck -check-prefix=VI %s -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -O0 -run-pass=legalizer %s -o - | FileCheck -check-prefix=GFX9PLUS %s -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -O0 -run-pass=legalizer %s -o - | FileCheck -check-prefix=GFX9PLUS %s -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -O0 -run-pass=legalizer -mattr=+real-true16 %s -o - | FileCheck -check-prefixes=GFX11PLUS,GFX11PLUS-TRUE16 %s -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -O0 -run-pass=legalizer -mattr=-real-true16 %s -o - | FileCheck -check-prefixes=GFX11PLUS,GFX11PLUS-FAKE16 %s -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -O0 -run-pass=legalizer -mattr=+real-true16 %s -o - | FileCheck -check-prefixes=GFX12,GFX12-TRUE16 %s -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -O0 -run-pass=legalizer -mattr=-real-true16 %s -o - | FileCheck -check-prefixes=GFX12,GFX12-FAKE16 %s -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=bonaire -mattr=-unaligned-access-mode -O0 -run-pass=legalizer %s -o - | FileCheck -check-prefixes=CI %s -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -mattr=-unaligned-access-mode -O0 -run-pass=legalizer %s -o - | FileCheck -check-prefixes=VI %s -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=-unaligned-access-mode -O0 -run-pass=legalizer %s -o - | FileCheck -check-prefixes=UNALIGNED_GFX9PLUS %s -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -mattr=-unaligned-access-mode -O0 -run-pass=legalizer %s -o - | FileCheck -check-prefixes=UNALIGNED_GFX9PLUS %s -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=+real-true16 -mattr=-unaligned-access-mode -O0 -run-pass=legalizer %s -o - | FileCheck -check-prefixes=UNALIGNED_GFX11PLUS %s -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -mattr=+real-true16 -mattr=-unaligned-access-mode -O0 -run-pass=legalizer %s -o - | FileCheck -check-prefixes=UNALIGNED_GFX12 %s +# RUN: llc -mtriple=amdgpu7.04-amd-amdhsa -O0 -run-pass=legalizer %s -o - | FileCheck -check-prefix=CI %s +# RUN: llc -mtriple=amdgpu8.03-amd-amdhsa -O0 -run-pass=legalizer %s -o - | FileCheck -check-prefix=VI %s +# RUN: llc -mtriple=amdgpu9.00-amd-amdhsa -O0 -run-pass=legalizer %s -o - | FileCheck -check-prefix=GFX9PLUS %s +# RUN: llc -mtriple=amdgpu10.10-amd-amdhsa -O0 -run-pass=legalizer %s -o - | FileCheck -check-prefix=GFX9PLUS %s +# RUN: llc -mtriple=amdgpu11.00-amd-amdhsa -O0 -run-pass=legalizer -mattr=+real-true16 %s -o - | FileCheck -check-prefixes=GFX11PLUS,GFX11PLUS-TRUE16 %s +# RUN: llc -mtriple=amdgpu11.00-amd-amdhsa -O0 -run-pass=legalizer -mattr=-real-true16 %s -o - | FileCheck -check-prefixes=GFX11PLUS,GFX11PLUS-FAKE16 %s +# RUN: llc -mtriple=amdgpu12.00-amd-amdhsa -O0 -run-pass=legalizer -mattr=+real-true16 %s -o - | FileCheck -check-prefixes=GFX12,GFX12-TRUE16 %s +# RUN: llc -mtriple=amdgpu12.00-amd-amdhsa -O0 -run-pass=legalizer -mattr=-real-true16 %s -o - | FileCheck -check-prefixes=GFX12,GFX12-FAKE16 %s +# RUN: llc -mtriple=amdgpu7.04-amd-amdhsa -mattr=-unaligned-access-mode -O0 -run-pass=legalizer %s -o - | FileCheck -check-prefixes=CI %s +# RUN: llc -mtriple=amdgpu8.03-amd-amdhsa -mattr=-unaligned-access-mode -O0 -run-pass=legalizer %s -o - | FileCheck -check-prefixes=VI %s +# RUN: llc -mtriple=amdgpu9.00-amd-amdhsa -mattr=-unaligned-access-mode -O0 -run-pass=legalizer %s -o - | FileCheck -check-prefixes=UNALIGNED_GFX9PLUS %s +# RUN: llc -mtriple=amdgpu10.10-amd-amdhsa -mattr=-unaligned-access-mode -O0 -run-pass=legalizer %s -o - | FileCheck -check-prefixes=UNALIGNED_GFX9PLUS %s +# RUN: llc -mtriple=amdgpu11.00-amd-amdhsa -mattr=+real-true16 -mattr=-unaligned-access-mode -O0 -run-pass=legalizer %s -o - | FileCheck -check-prefixes=UNALIGNED_GFX11PLUS %s +# RUN: llc -mtriple=amdgpu12.00-amd-amdhsa -mattr=+real-true16 -mattr=-unaligned-access-mode -O0 -run-pass=legalizer %s -o - | FileCheck -check-prefixes=UNALIGNED_GFX12 %s --- name: test_load_flat_s1_align1 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir index 8ca93ff3e809f..9d5ceec33b86f 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir @@ -1,22 +1,22 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -O0 -run-pass=legalizer -global-isel-abort=0 -pass-remarks-missed='gisel.*' %s 2> %t.err -o - | FileCheck -check-prefix=SI %s +# RUN: llc -mtriple=amdgpu6.00-mesa-mesa3d -O0 -run-pass=legalizer -global-isel-abort=0 -pass-remarks-missed='gisel.*' %s 2> %t.err -o - | FileCheck -check-prefix=SI %s # RUN: FileCheck -check-prefix=ERR %s < %t.err -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=bonaire -O0 -run-pass=legalizer -global-isel-abort=0 %s -o - | FileCheck -check-prefix=CI-HSA %s -# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=bonaire -O0 -run-pass=legalizer -global-isel-abort=0 %s -o - | FileCheck -check-prefix=CI-MESA %s -# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer -global-isel-abort=0 %s -o - | FileCheck -check-prefix=VI %s -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -O0 -run-pass=legalizer -global-isel-abort=0 -pass-remarks-missed='gisel.*' 2> %t.err %s -o - | FileCheck -check-prefixes=GFX9-HSA %s +# RUN: llc -mtriple=amdgpu7.04-amd-amdhsa -O0 -run-pass=legalizer -global-isel-abort=0 %s -o - | FileCheck -check-prefix=CI-HSA %s +# RUN: llc -mtriple=amdgpu7.04-mesa-mesa3d -O0 -run-pass=legalizer -global-isel-abort=0 %s -o - | FileCheck -check-prefix=CI-MESA %s +# RUN: llc -mtriple=amdgpu8.03-mesa-mesa3d -O0 -run-pass=legalizer -global-isel-abort=0 %s -o - | FileCheck -check-prefix=VI %s +# RUN: llc -mtriple=amdgpu9.00-amd-amdhsa -O0 -run-pass=legalizer -global-isel-abort=0 -pass-remarks-missed='gisel.*' 2> %t.err %s -o - | FileCheck -check-prefixes=GFX9-HSA %s # RUN: FileCheck -check-prefix=ERR %s < %t.err -# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -O0 -run-pass=legalizer -global-isel-abort=0 %s -o - | FileCheck -check-prefixes=GFX9-MESA %s -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -O0 -run-pass=legalizer -global-isel-abort=0 %s -o - | FileCheck -check-prefixes=GFX9-HSA %s -# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -O0 -run-pass=legalizer -global-isel-abort=0 %s -o - | FileCheck -check-prefixes=GFX9-MESA %s -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -O0 -run-pass=legalizer -global-isel-abort=0 -mattr=+real-true16 %s -o - | FileCheck -check-prefixes=GFX11-HSA,GFX11-HSA-TRUE16 %s -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -O0 -run-pass=legalizer -global-isel-abort=0 -mattr=-real-true16 %s -o - | FileCheck -check-prefixes=GFX11-HSA,GFX11-HSA-FAKE16 %s -# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -O0 -run-pass=legalizer -global-isel-abort=0 -mattr=+real-true16 %s -o - | FileCheck -check-prefixes=GFX11-MESA,GFX11-MESA-TRUE16 %s -# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -O0 -run-pass=legalizer -global-isel-abort=0 -mattr=-real-true16 %s -o - | FileCheck -check-prefixes=GFX11-MESA,GFX11-MESA-FAKE16 %s -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -O0 -run-pass=legalizer -global-isel-abort=0 -mattr=+real-true16 %s -o - | FileCheck -check-prefixes=GFX12-HSA,GFX12-HSA-TRUE16 %s -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -O0 -run-pass=legalizer -global-isel-abort=0 -mattr=-real-true16 %s -o - | FileCheck -check-prefixes=GFX12-HSA,GFX12-HSA-FAKE16 %s -# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1200 -O0 -run-pass=legalizer -global-isel-abort=0 -mattr=+real-true16 %s -o - | FileCheck -check-prefixes=GFX12-MESA,GFX12-MESA-TRUE16 %s -# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1200 -O0 -run-pass=legalizer -global-isel-abort=0 -mattr=-real-true16 %s -o - | FileCheck -check-prefixes=GFX12-MESA,GFX12-MESA-FAKE16 %s +# RUN: llc -mtriple=amdgpu9.00-mesa-mesa3d -O0 -run-pass=legalizer -global-isel-abort=0 %s -o - | FileCheck -check-prefixes=GFX9-MESA %s +# RUN: llc -mtriple=amdgpu10.10-amd-amdhsa -O0 -run-pass=legalizer -global-isel-abort=0 %s -o - | FileCheck -check-prefixes=GFX9-HSA %s +# RUN: llc -mtriple=amdgpu10.10-mesa-mesa3d -O0 -run-pass=legalizer -global-isel-abort=0 %s -o - | FileCheck -check-prefixes=GFX9-MESA %s +# RUN: llc -mtriple=amdgpu11.00-amd-amdhsa -O0 -run-pass=legalizer -global-isel-abort=0 -mattr=+real-true16 %s -o - | FileCheck -check-prefixes=GFX11-HSA,GFX11-HSA-TRUE16 %s +# RUN: llc -mtriple=amdgpu11.00-amd-amdhsa -O0 -run-pass=legalizer -global-isel-abort=0 -mattr=-real-true16 %s -o - | FileCheck -check-prefixes=GFX11-HSA,GFX11-HSA-FAKE16 %s +# RUN: llc -mtriple=amdgpu11.00-mesa-mesa3d -O0 -run-pass=legalizer -global-isel-abort=0 -mattr=+real-true16 %s -o - | FileCheck -check-prefixes=GFX11-MESA,GFX11-MESA-TRUE16 %s +# RUN: llc -mtriple=amdgpu11.00-mesa-mesa3d -O0 -run-pass=legalizer -global-isel-abort=0 -mattr=-real-true16 %s -o - | FileCheck -check-prefixes=GFX11-MESA,GFX11-MESA-FAKE16 %s +# RUN: llc -mtriple=amdgpu12.00-amd-amdhsa -O0 -run-pass=legalizer -global-isel-abort=0 -mattr=+real-true16 %s -o - | FileCheck -check-prefixes=GFX12-HSA,GFX12-HSA-TRUE16 %s +# RUN: llc -mtriple=amdgpu12.00-amd-amdhsa -O0 -run-pass=legalizer -global-isel-abort=0 -mattr=-real-true16 %s -o - | FileCheck -check-prefixes=GFX12-HSA,GFX12-HSA-FAKE16 %s +# RUN: llc -mtriple=amdgpu12.00-mesa-mesa3d -O0 -run-pass=legalizer -global-isel-abort=0 -mattr=+real-true16 %s -o - | FileCheck -check-prefixes=GFX12-MESA,GFX12-MESA-TRUE16 %s +# RUN: llc -mtriple=amdgpu12.00-mesa-mesa3d -O0 -run-pass=legalizer -global-isel-abort=0 -mattr=-real-true16 %s -o - | FileCheck -check-prefixes=GFX12-MESA,GFX12-MESA-FAKE16 %s # ERR-NOT: remark # ERR: remark: <unknown>:0:0: unable to legalize instruction: %{{[0-9]+}}:_(<2 x s32>) = G_LOAD %{{[0-9]+}}:_(p1) :: (load (<2 x s16>), align 1, addrspace 1) (in function: test_extload_global_v2s32_from_v2s16_align1) diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-local.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-local.mir index e1df4a5f9b1ff..3cfd6a321f4f2 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-local.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-local.mir @@ -1,20 +1,20 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -O0 -run-pass=legalizer -global-isel-abort=0 %s -o - | FileCheck -check-prefix=SI %s -# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=bonaire -mattr=-enable-ds128 -O0 -run-pass=legalizer -global-isel-abort=0 %s -o - | FileCheck -check-prefix=CI %s -# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=bonaire -mattr=+enable-ds128 -O0 -run-pass=legalizer -global-isel-abort=0 %s -o - | FileCheck -check-prefix=CI-DS128 %s -# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer -global-isel-abort=0 %s -o - | FileCheck -check-prefix=VI %s -# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -O0 -run-pass=legalizer -mattr=-unaligned-access-mode -global-isel-abort=0 %s -o - | FileCheck -check-prefix=GFX9 %s -# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -O0 -run-pass=legalizer -mattr=+unaligned-access-mode -global-isel-abort=0 %s -o - | FileCheck -check-prefix=GFX9-UNALIGNED %s -# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -O0 -run-pass=legalizer -mattr=-unaligned-access-mode -global-isel-abort=0 %s -o - | FileCheck -check-prefix=GFX10 %s -# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -O0 -run-pass=legalizer -mattr=+unaligned-access-mode -global-isel-abort=0 %s -o - | FileCheck -check-prefix=GFX10-UNALIGNED %s -# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -O0 -run-pass=legalizer -mattr=-unaligned-access-mode,+real-true16 -global-isel-abort=0 %s -o - | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s -# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -O0 -run-pass=legalizer -mattr=-unaligned-access-mode,-real-true16 -global-isel-abort=0 %s -o - | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s -# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -O0 -run-pass=legalizer -mattr=+unaligned-access-mode,+real-true16 -global-isel-abort=0 %s -o - | FileCheck -check-prefixes=GFX11-UNALIGNED,GFX11-UNALIGNED-TRUE16 %s -# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -O0 -run-pass=legalizer -mattr=+unaligned-access-mode,-real-true16 -global-isel-abort=0 %s -o - | FileCheck -check-prefixes=GFX11-UNALIGNED,GFX11-UNALIGNED-FAKE16 %s -# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1200 -O0 -run-pass=legalizer -mattr=-unaligned-access-mode,+real-true16 -global-isel-abort=0 %s -o - | FileCheck -check-prefixes=GFX12,GFX12-TRUE16 %s -# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1200 -O0 -run-pass=legalizer -mattr=-unaligned-access-mode,-real-true16 -global-isel-abort=0 %s -o - | FileCheck -check-prefixes=GFX12,GFX12-FAKE16 %s -# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1200 -O0 -run-pass=legalizer -mattr=+unaligned-access-mode,+real-true16 -global-isel-abort=0 %s -o - | FileCheck -check-prefixes=GFX12-UNALIGNED,GFX12-UNALIGNED-TRUE16 %s -# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1200 -O0 -run-pass=legalizer -mattr=+unaligned-access-mode,-real-true16 -global-isel-abort=0 %s -o - | FileCheck -check-prefixes=GFX12-UNALIGNED,GFX12-UNALIGNED-FAKE16 %s +# RUN: llc -mtriple=amdgpu6.00-mesa-mesa3d -O0 -run-pass=legalizer -global-isel-abort=0 %s -o - | FileCheck -check-prefix=SI %s +# RUN: llc -mtriple=amdgpu7.04-mesa-mesa3d -mattr=-enable-ds128 -O0 -run-pass=legalizer -global-isel-abort=0 %s -o - | FileCheck -check-prefix=CI %s +# RUN: llc -mtriple=amdgpu7.04-mesa-mesa3d -mattr=+enable-ds128 -O0 -run-pass=legalizer -global-isel-abort=0 %s -o - | FileCheck -check-prefix=CI-DS128 %s +# RUN: llc -mtriple=amdgpu8.03-mesa-mesa3d -O0 -run-pass=legalizer -global-isel-abort=0 %s -o - | FileCheck -check-prefix=VI %s +# RUN: llc -mtriple=amdgpu9.00-mesa-mesa3d -O0 -run-pass=legalizer -mattr=-unaligned-access-mode -global-isel-abort=0 %s -o - | FileCheck -check-prefix=GFX9 %s +# RUN: llc -mtriple=amdgpu9.00-mesa-mesa3d -O0 -run-pass=legalizer -mattr=+unaligned-access-mode -global-isel-abort=0 %s -o - | FileCheck -check-prefix=GFX9-UNALIGNED %s +# RUN: llc -mtriple=amdgpu10.10-mesa-mesa3d -O0 -run-pass=legalizer -mattr=-unaligned-access-mode -global-isel-abort=0 %s -o - | FileCheck -check-prefix=GFX10 %s +# RUN: llc -mtriple=amdgpu10.10-mesa-mesa3d -O0 -run-pass=legalizer -mattr=+unaligned-access-mode -global-isel-abort=0 %s -o - | FileCheck -check-prefix=GFX10-UNALIGNED %s +# RUN: llc -mtriple=amdgpu11.00-mesa-mesa3d -O0 -run-pass=legalizer -mattr=-unaligned-access-mode,+real-true16 -global-isel-abort=0 %s -o - | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s +# RUN: llc -mtriple=amdgpu11.00-mesa-mesa3d -O0 -run-pass=legalizer -mattr=-unaligned-access-mode,-real-true16 -global-isel-abort=0 %s -o - | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s +# RUN: llc -mtriple=amdgpu11.00-mesa-mesa3d -O0 -run-pass=legalizer -mattr=+unaligned-access-mode,+real-true16 -global-isel-abort=0 %s -o - | FileCheck -check-prefixes=GFX11-UNALIGNED,GFX11-UNALIGNED-TRUE16 %s +# RUN: llc -mtriple=amdgpu11.00-mesa-mesa3d -O0 -run-pass=legalizer -mattr=+unaligned-access-mode,-real-true16 -global-isel-abort=0 %s -o - | FileCheck -check-prefixes=GFX11-UNALIGNED,GFX11-UNALIGNED-FAKE16 %s +# RUN: llc -mtriple=amdgpu12.00-mesa-mesa3d -O0 -run-pass=legalizer -mattr=-unaligned-access-mode,+real-true16 -global-isel-abort=0 %s -o - | FileCheck -check-prefixes=GFX12,GFX12-TRUE16 %s +# RUN: llc -mtriple=amdgpu12.00-mesa-mesa3d -O0 -run-pass=legalizer -mattr=-unaligned-access-mode,-real-true16 -global-isel-abort=0 %s -o - | FileCheck -check-prefixes=GFX12,GFX12-FAKE16 %s +# RUN: llc -mtriple=amdgpu12.00-mesa-mesa3d -O0 -run-pass=legalizer -mattr=+unaligned-access-mode,+real-true16 -global-isel-abort=0 %s -o - | FileCheck -check-prefixes=GFX12-UNALIGNED,GFX12-UNALIGNED-TRUE16 %s +# RUN: llc -mtriple=amdgpu12.00-mesa-mesa3d -O0 -run-pass=legalizer -mattr=+unaligned-access-mode,-real-true16 -global-isel-abort=0 %s -o - | FileCheck -check-prefixes=GFX12-UNALIGNED,GFX12-UNALIGNED-FAKE16 %s --- name: test_load_local_s1_align1 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-memory-metadata.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-memory-metadata.mir index da88d5f13c1eb..4b52e96f5a5ef 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-memory-metadata.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-memory-metadata.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer %s -o - | FileCheck -check-prefix=SI %s +# RUN: llc -mtriple=amdgpu6.00-mesa-mesa3d -run-pass=legalizer %s -o - | FileCheck -check-prefix=SI %s --- | diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir index 4f123b4aa9004..72615bb1b7cda 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir @@ -1,20 +1,20 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=tahiti -O0 -run-pass=legalizer -global-isel-abort=0 %s -o - | FileCheck -check-prefix=SI %s -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=bonaire -O0 -run-pass=legalizer -global-isel-abort=0 %s -o - | FileCheck -check-prefix=CI %s -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -O0 -run-pass=legalizer -global-isel-abort=0 %s -o - | FileCheck -check-prefix=VI %s -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -O0 -run-pass=legalizer -global-isel-abort=0 %s -o - | FileCheck -check-prefix=GFX9 %s -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -O0 -run-pass=legalizer -global-isel-abort=0 %s -o - | FileCheck -check-prefix=GFX10 %s -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -O0 -run-pass=legalizer -global-isel-abort=0 -mattr=+real-true16 %s -o - | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -O0 -run-pass=legalizer -global-isel-abort=0 -mattr=-real-true16 %s -o - | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -O0 -run-pass=legalizer -global-isel-abort=0 -mattr=+real-true16 %s -o - | FileCheck -check-prefixes=GFX12,GFX12-TRUE16 %s -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -O0 -run-pass=legalizer -global-isel-abort=0 -mattr=-real-true16 %s -o - | FileCheck -check-prefixes=GFX12,GFX12-FAKE16 %s -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=tahiti -mattr=-unaligned-access-mode -O0 -run-pass=legalizer -global-isel-abort=0 %s -o - | FileCheck -check-prefixes=SI %s -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=bonaire -mattr=-unaligned-access-mode -O0 -run-pass=legalizer -global-isel-abort=0 %s -o - | FileCheck -check-prefixes=CI %s -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -mattr=-unaligned-access-mode -O0 -run-pass=legalizer -global-isel-abort=0 %s -o - | FileCheck -check-prefixes=VI %s -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=-unaligned-access-mode -O0 -run-pass=legalizer -global-isel-abort=0 %s -o - | FileCheck -check-prefixes=UNALIGNED_GFX9 %s -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -mattr=-unaligned-access-mode -O0 -run-pass=legalizer -global-isel-abort=0 %s -o - | FileCheck -check-prefixes=UNALIGNED_GFX10 %s -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=+real-true16 -mattr=-unaligned-access-mode -O0 -run-pass=legalizer -global-isel-abort=0 %s -o - | FileCheck -check-prefixes=UNALIGNED_GFX11 %s -# RUN: llc -mtriple=amdgcn-am... [truncated] `````````` </details> https://github.com/llvm/llvm-project/pull/209734 _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
