github-actions[bot] wrote:
<!--LLVM CODE FORMAT COMMENT: {clang-format}-->
:warning: C/C++ code formatter, clang-format found issues in your code.
:warning:
<details>
<summary>
You can test this locally with the following command:
</summary>
``````````bash
git-clang-format --diff origin/main HEAD --extensions cl,c,h,cpp --
clang/lib/Basic/Targets/AMDGPU.cpp clang/test/CodeGen/target-data.c
clang/test/CodeGenOpenCL/amdgpu-env-amdgcn.cl
clang/test/CodeGenOpenCL/builtins-amdgcn-gfx12.cl
clang/test/CodeGenOpenCL/builtins-amdgcn-gfx1250.cl
llvm/include/llvm/Support/AMDGPUAddrSpace.h llvm/lib/Target/AMDGPU/AMDGPU.h
llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
llvm/lib/Target/AMDGPU/AMDGPULowerExecSync.cpp
llvm/lib/Target/AMDGPU/AMDGPULowerModuleLDSPass.cpp
llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp
llvm/lib/Target/AMDGPU/AMDGPUMachineFunctionInfo.cpp
llvm/lib/Target/AMDGPU/AMDGPUMachineFunctionInfo.h
llvm/lib/Target/AMDGPU/AMDGPUMemoryUtils.cpp llvm/lib/Target/AMDGPU/SIDefines.h
llvm/lib/Target/AMDGPU/SIISelLowering.cpp
llvm/lib/TargetParser/TargetDataLayout.cpp
mlir/lib/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.cpp
mlir/lib/Conversion/GPUToROCDL/LowerGpuOpsToROCDLOps.cpp
--diff_from_common_commit
``````````
:warning:
The reproduction instructions above might return results for more than one PR
in a stack if you are using a stacked PR workflow. You can limit the results by
changing `origin/main` to the base branch/commit you want to compare against.
:warning:
</details>
<details>
<summary>
View the diff from clang-format here.
</summary>
``````````diff
diff --git a/clang/lib/Basic/Targets/AMDGPU.cpp
b/clang/lib/Basic/Targets/AMDGPU.cpp
index e544325af..a2330dd1d 100644
--- a/clang/lib/Basic/Targets/AMDGPU.cpp
+++ b/clang/lib/Basic/Targets/AMDGPU.cpp
@@ -57,7 +57,7 @@ const LangASMap AMDGPUTargetInfo::AMDGPUAddrSpaceMap = {
llvm::AMDGPUAS::PRIVATE_ADDRESS, // hlsl_output
llvm::AMDGPUAS::GLOBAL_ADDRESS, // hlsl_push_constant
llvm::AMDGPUAS::FLAT_ADDRESS, // wasm_funcref
- llvm::AMDGPUAS::BARRIER, // amdgpu_barrier
+ llvm::AMDGPUAS::BARRIER, // amdgpu_barrier
};
} // namespace targets
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index e6b116111..7221cdd94 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -12078,11 +12078,8 @@ SDValue
SITargetLowering::LowerINTRINSIC_W_CHAIN(SDValue Op,
} else {
Opc = AMDGPU::S_GET_BARRIER_STATE_M0;
if (IntrID == Intrinsic::amdgcn_s_get_named_barrier_state) {
- SDValue M0Val =
- DAG.getNode(
- ISD::AND, DL, MVT::i32, Op->getOperand(2),
- DAG.getConstant(0x3F, DL, MVT::i32))
- ;
+ SDValue M0Val = DAG.getNode(ISD::AND, DL, MVT::i32, Op->getOperand(2),
+ DAG.getConstant(0x3F, DL, MVT::i32));
Ops.push_back(copyToM0(DAG, Chain, DL, M0Val).getValue(0));
} else
Ops.push_back(copyToM0(DAG, Chain, DL, Op->getOperand(2)).getValue(0));
@@ -12717,7 +12714,7 @@ SDValue SITargetLowering::LowerINTRINSIC_VOID(SDValue
Op,
: AMDGPU::S_BARRIER_SIGNAL_M0;
// extract the BarrierID from bits 0-5 of BarOp
SDValue BarID = DAG.getNode(ISD::AND, DL, MVT::i32, BarOp,
- DAG.getConstant(0x3F, DL, MVT::i32));
+ DAG.getConstant(0x3F, DL, MVT::i32));
// Member count should be put into M0[ShAmt:+6]
// Barrier ID should be put into M0[5:0]
SDValue MemberCnt = DAG.getNode(ISD::AND, DL, MVT::i32, CntOp,
@@ -12775,7 +12772,7 @@ SDValue SITargetLowering::LowerINTRINSIC_VOID(SDValue
Op,
}
// extract the BarrierID from bits 0-5 of BarOp, copy to M0[5:0]
SDValue M0Val = DAG.getNode(ISD::AND, DL, MVT::i32, BarOp,
- DAG.getConstant(0x3F, DL, MVT::i32));
+ DAG.getConstant(0x3F, DL, MVT::i32));
Ops.push_back(copyToM0(DAG, Chain, DL, M0Val).getValue(0));
}
``````````
</details>
https://github.com/llvm/llvm-project/pull/209746
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