https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/209776
Fold the explicit -mcpu subtarget into the amdgpu subarch triple on llc/opt RUN lines (e.g. -mtriple=amdgcn -mcpu=gfx600 -> -mtriple=amdgpu6.00), now that these tests carry an explicit -mcpu following the default-subtarget pinning. Codegen output is unchanged. Co-Authored-By: Claude <[email protected]> (Claude-Opus-4.8) >From 7eccd5dddf28079da240c957d0e9d4e6cfce3629 Mon Sep 17 00:00:00 2001 From: Matt Arsenault <[email protected]> Date: Fri, 26 Jun 2026 07:46:58 +0200 Subject: [PATCH] AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (50) Fold the explicit -mcpu subtarget into the amdgpu subarch triple on llc/opt RUN lines (e.g. -mtriple=amdgcn -mcpu=gfx600 -> -mtriple=amdgpu6.00), now that these tests carry an explicit -mcpu following the default-subtarget pinning. Codegen output is unchanged. Co-Authored-By: Claude <[email protected]> (Claude-Opus-4.8) --- llvm/test/CodeGen/AMDGPU/InlineAsmCrash.ll | 2 +- llvm/test/CodeGen/AMDGPU/add_i128.ll | 2 +- llvm/test/CodeGen/AMDGPU/add_i64.ll | 2 +- .../AMDGPU/addrspacecast-initializer-unsupported.ll | 2 +- llvm/test/CodeGen/AMDGPU/addrspacecast-initializer.ll | 2 +- llvm/test/CodeGen/AMDGPU/alignbit-pat.ll | 2 +- llvm/test/CodeGen/AMDGPU/allow-check.ll | 6 +++--- llvm/test/CodeGen/AMDGPU/amdgpu-function-calls-option.ll | 6 +++--- llvm/test/CodeGen/AMDGPU/array-ptr-calc-i64.ll | 2 +- llvm/test/CodeGen/AMDGPU/barrier-elimination.ll | 4 ++-- llvm/test/CodeGen/AMDGPU/bfi_nested.ll | 2 +- llvm/test/CodeGen/AMDGPU/branch-relax-indirect-branch.mir | 2 +- llvm/test/CodeGen/AMDGPU/branch-uniformity.ll | 2 +- llvm/test/CodeGen/AMDGPU/call-constant.ll | 4 ++-- llvm/test/CodeGen/AMDGPU/call-constexpr.ll | 4 ++-- llvm/test/CodeGen/AMDGPU/cf-loop-on-constant.ll | 4 ++-- llvm/test/CodeGen/AMDGPU/clamp-omod-special-case.mir | 2 +- llvm/test/CodeGen/AMDGPU/cndmask-no-def-vcc.ll | 2 +- .../CodeGen/AMDGPU/coalescer-early-clobber-subreg.mir | 2 +- .../CodeGen/AMDGPU/coalescer-identical-values-undef.mir | 2 +- llvm/test/CodeGen/AMDGPU/coalescer-subreg-join.mir | 2 +- llvm/test/CodeGen/AMDGPU/coalescer_remat.ll | 2 +- llvm/test/CodeGen/AMDGPU/collapse-endcf-broken.mir | 4 ++-- llvm/test/CodeGen/AMDGPU/collapse-endcf.mir | 4 ++-- llvm/test/CodeGen/AMDGPU/collapse-endcf2.mir | 2 +- llvm/test/CodeGen/AMDGPU/combine-and-sext-bool.ll | 2 +- llvm/test/CodeGen/AMDGPU/combine-reg-or-const.ll | 2 +- llvm/test/CodeGen/AMDGPU/combine-sreg64-inits.mir | 4 ++-- llvm/test/CodeGen/AMDGPU/commute-compares.ll | 2 +- llvm/test/CodeGen/AMDGPU/commute_modifiers.ll | 2 +- llvm/test/CodeGen/AMDGPU/control-flow-fastregalloc.ll | 4 ++-- llvm/test/CodeGen/AMDGPU/control-flow-optnone.ll | 2 +- llvm/test/CodeGen/AMDGPU/convergent-inlineasm.ll | 2 +- .../CodeGen/AMDGPU/copyprop_regsequence_with_undef.mir | 4 ++-- llvm/test/CodeGen/AMDGPU/cttz-elts.ll | 2 +- .../test/CodeGen/AMDGPU/dagcomb-shuffle-vecextend-non2.ll | 2 +- llvm/test/CodeGen/AMDGPU/dagcombine-lshr-and-cmp.ll | 2 +- llvm/test/CodeGen/AMDGPU/dagcombine-reassociate-bug.ll | 2 +- llvm/test/CodeGen/AMDGPU/dce-disjoint-intervals.mir | 2 +- llvm/test/CodeGen/AMDGPU/debug-value2.ll | 2 +- llvm/test/CodeGen/AMDGPU/debug_frame.ll | 8 ++++---- .../CodeGen/AMDGPU/default_amdhsa_code_object_version.ll | 2 +- llvm/test/CodeGen/AMDGPU/detect-dead-lanes.mir | 4 ++-- llvm/test/CodeGen/AMDGPU/div_v2i128.ll | 4 ++-- llvm/test/CodeGen/AMDGPU/divergence-driven-bfe-isel.ll | 2 +- llvm/test/CodeGen/AMDGPU/divergence-driven-bitreverse.ll | 4 ++-- llvm/test/CodeGen/AMDGPU/divergence-driven-ctlz-cttz.ll | 4 ++-- llvm/test/CodeGen/AMDGPU/divergence-driven-ctpop.ll | 4 ++-- llvm/test/CodeGen/AMDGPU/divergence-driven-min-max.ll | 4 ++-- llvm/test/CodeGen/AMDGPU/divergence-driven-not-isel.ll | 4 ++-- llvm/test/CodeGen/AMDGPU/divergence-driven-sext-inreg.ll | 2 +- llvm/test/CodeGen/AMDGPU/divergence-driven-trunc-to-i1.ll | 2 +- .../test/CodeGen/AMDGPU/enable-no-signed-zeros-fp-math.ll | 2 +- llvm/test/CodeGen/AMDGPU/endcf-loop-header.ll | 2 +- llvm/test/CodeGen/AMDGPU/endpgm-dce.mir | 2 +- llvm/test/CodeGen/AMDGPU/extload-align.ll | 2 +- llvm/test/CodeGen/AMDGPU/extract-load-i1.ll | 2 +- .../test/CodeGen/AMDGPU/extract-subvector-equal-length.ll | 2 +- llvm/test/CodeGen/AMDGPU/extract-subvector.ll | 2 +- .../AMDGPU/extract-vector-elt-build-vector-combine.ll | 2 +- llvm/test/CodeGen/AMDGPU/extractelt-to-trunc.ll | 2 +- llvm/test/CodeGen/AMDGPU/fabs.f64.ll | 2 +- llvm/test/CodeGen/AMDGPU/fadd-fma-fmul-combine.ll | 8 ++++---- llvm/test/CodeGen/AMDGPU/fix-sgpr-copies.mir | 2 +- llvm/test/CodeGen/AMDGPU/fix-vgpr-copies.mir | 4 ++-- llvm/test/CodeGen/AMDGPU/fold-cndmask.mir | 2 +- llvm/test/CodeGen/AMDGPU/fold-fi-mubuf.mir | 2 +- llvm/test/CodeGen/AMDGPU/fold-fi-operand-shrink.mir | 2 +- llvm/test/CodeGen/AMDGPU/fold-fmul-to-neg-abs.ll | 2 +- llvm/test/CodeGen/AMDGPU/fold-imm-copy.mir | 2 +- .../AMDGPU/fold-immediate-operand-shrink-with-carry.mir | 2 +- .../test/CodeGen/AMDGPU/fold-immediate-operand-shrink.mir | 2 +- llvm/test/CodeGen/AMDGPU/fold-immediate-output-mods.mir | 4 ++-- llvm/test/CodeGen/AMDGPU/fold-implicit-operand.mir | 2 +- llvm/test/CodeGen/AMDGPU/fold-over-exec.mir | 2 +- llvm/test/CodeGen/AMDGPU/fold-readlane.mir | 2 +- .../force-alwaysinline-lds-global-address-codegen.ll | 6 +++--- llvm/test/CodeGen/AMDGPU/fp-to-int-to-fp.ll | 2 +- .../CodeGen/AMDGPU/frame-lowering-entry-all-sgpr-used.mir | 2 +- .../test/CodeGen/AMDGPU/freeze-other-uses-issue-198094.ll | 2 +- llvm/test/CodeGen/AMDGPU/global-alias.ll | 2 +- llvm/test/CodeGen/AMDGPU/hoist-cond.ll | 2 +- llvm/test/CodeGen/AMDGPU/hsa-metadata-deduced-arg-attr.ll | 2 +- .../CodeGen/AMDGPU/hsa-metadata-invalid-ocl-version-1.ll | 2 +- .../CodeGen/AMDGPU/hsa-metadata-invalid-ocl-version-3.ll | 2 +- llvm/test/CodeGen/AMDGPU/huge-number-operand-folds.mir | 2 +- llvm/test/CodeGen/AMDGPU/i1-copies-rpo.mir | 2 +- llvm/test/CodeGen/AMDGPU/i1-copy-from-loop.ll | 2 +- llvm/test/CodeGen/AMDGPU/i1-copy-phi-uniform-branch.ll | 2 +- llvm/test/CodeGen/AMDGPU/implicit-def-muse.ll | 4 ++-- llvm/test/CodeGen/AMDGPU/indirect-call.ll | 4 ++-- llvm/test/CodeGen/AMDGPU/insert-waitcnts-exp.mir | 2 +- llvm/test/CodeGen/AMDGPU/invalid-addrspacecast.ll | 4 ++-- .../CodeGen/AMDGPU/invalid-inline-asm-constraint-crash.ll | 2 +- llvm/test/CodeGen/AMDGPU/invariant-load-no-alias-store.ll | 2 +- llvm/test/CodeGen/AMDGPU/invert-br-undef-vcc.mir | 2 +- llvm/test/CodeGen/AMDGPU/ipra-regmask.ll | 8 ++++---- .../CodeGen/AMDGPU/ipra-return-address-save-restore.ll | 4 ++-- llvm/test/CodeGen/AMDGPU/kernarg-stack-alignment.ll | 2 +- 99 files changed, 136 insertions(+), 136 deletions(-) diff --git a/llvm/test/CodeGen/AMDGPU/InlineAsmCrash.ll b/llvm/test/CodeGen/AMDGPU/InlineAsmCrash.ll index 974b16188b1ed..a4bb74b7c26d2 100644 --- a/llvm/test/CodeGen/AMDGPU/InlineAsmCrash.ll +++ b/llvm/test/CodeGen/AMDGPU/InlineAsmCrash.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck %s +; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck %s ; CHECK: ;;#ASMSTART ; CHECK-NEXT: s_nop 0 diff --git a/llvm/test/CodeGen/AMDGPU/add_i128.ll b/llvm/test/CodeGen/AMDGPU/add_i128.ll index 19b05357c1f5e..5342ec89b0d69 100644 --- a/llvm/test/CodeGen/AMDGPU/add_i128.ll +++ b/llvm/test/CodeGen/AMDGPU/add_i128.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck -check-prefix=GCN %s define amdgpu_kernel void @test_i128_vreg(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %inA, ptr addrspace(1) noalias %inB) { ; GCN-LABEL: test_i128_vreg: diff --git a/llvm/test/CodeGen/AMDGPU/add_i64.ll b/llvm/test/CodeGen/AMDGPU/add_i64.ll index b4ac465f5fa0a..e14185405b610 100644 --- a/llvm/test/CodeGen/AMDGPU/add_i64.ll +++ b/llvm/test/CodeGen/AMDGPU/add_i64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -check-prefix=SI %s +; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck -check-prefix=SI %s define amdgpu_kernel void @test_i64_vreg(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %inA, ptr addrspace(1) noalias %inB) { ; SI-LABEL: test_i64_vreg: diff --git a/llvm/test/CodeGen/AMDGPU/addrspacecast-initializer-unsupported.ll b/llvm/test/CodeGen/AMDGPU/addrspacecast-initializer-unsupported.ll index 38161b66fea7d..30279992a87ef 100644 --- a/llvm/test/CodeGen/AMDGPU/addrspacecast-initializer-unsupported.ll +++ b/llvm/test/CodeGen/AMDGPU/addrspacecast-initializer-unsupported.ll @@ -1,4 +1,4 @@ -; RUN: not llc -mtriple=amdgcn -mcpu=gfx600 -amdgpu-enable-lower-module-lds=false < %s 2> %t.err | FileCheck %s +; RUN: not llc -mtriple=amdgpu6.00 -amdgpu-enable-lower-module-lds=false < %s 2> %t.err | FileCheck %s ; RUN: FileCheck -check-prefix=ERROR %s < %t.err ; ERROR: error: unsupported expression in static initializer: addrspacecast (ptr addrspace(3) @lds.arr to ptr addrspace(4)) diff --git a/llvm/test/CodeGen/AMDGPU/addrspacecast-initializer.ll b/llvm/test/CodeGen/AMDGPU/addrspacecast-initializer.ll index 7f892e747e245..7b54067f6db1c 100644 --- a/llvm/test/CodeGen/AMDGPU/addrspacecast-initializer.ll +++ b/llvm/test/CodeGen/AMDGPU/addrspacecast-initializer.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck %s +; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck %s ; CHECK: global.arr: ; CHECK: .zero 1024 diff --git a/llvm/test/CodeGen/AMDGPU/alignbit-pat.ll b/llvm/test/CodeGen/AMDGPU/alignbit-pat.ll index c21ee9842fdda..77d31967defb3 100644 --- a/llvm/test/CodeGen/AMDGPU/alignbit-pat.ll +++ b/llvm/test/CodeGen/AMDGPU/alignbit-pat.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 -; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgpu6.00 < %s | FileCheck -check-prefix=GCN %s define amdgpu_kernel void @alignbit_shr_pat(ptr addrspace(1) nocapture readonly %arg, ptr addrspace(1) nocapture %arg1, i32 %arg2) { ; GCN-LABEL: alignbit_shr_pat: diff --git a/llvm/test/CodeGen/AMDGPU/allow-check.ll b/llvm/test/CodeGen/AMDGPU/allow-check.ll index 430a8a9fb26c7..4cb6439c187ad 100644 --- a/llvm/test/CodeGen/AMDGPU/allow-check.ll +++ b/llvm/test/CodeGen/AMDGPU/allow-check.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 -; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx600 -global-isel=0 -fast-isel=0 | FileCheck %s -; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx600 -global-isel=1 -fast-isel=0 | FileCheck %s -; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx600 -global-isel=0 -fast-isel=1 | FileCheck %s +; RUN: llc < %s -mtriple=amdgpu6.00-amd-mesa3d -global-isel=0 -fast-isel=0 | FileCheck %s +; RUN: llc < %s -mtriple=amdgpu6.00-amd-mesa3d -global-isel=1 -fast-isel=0 | FileCheck %s +; RUN: llc < %s -mtriple=amdgpu6.00-amd-mesa3d -global-isel=0 -fast-isel=1 | FileCheck %s define i1 @test_runtime() local_unnamed_addr { ; CHECK-LABEL: test_runtime: diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-function-calls-option.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-function-calls-option.ll index 3394a287b828f..9e7a50d4d826a 100644 --- a/llvm/test/CodeGen/AMDGPU/amdgpu-function-calls-option.ll +++ b/llvm/test/CodeGen/AMDGPU/amdgpu-function-calls-option.ll @@ -1,6 +1,6 @@ -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -amdgpu-function-calls < %s | FileCheck -check-prefix=CALLS %s -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 < %s | FileCheck -check-prefix=CALLS %s -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -amdgpu-function-calls=0 < %s | FileCheck -check-prefix=NOCALLS %s +; RUN: llc -mtriple=amdgpu7.00-amd-amdhsa -amdgpu-function-calls < %s | FileCheck -check-prefix=CALLS %s +; RUN: llc -mtriple=amdgpu7.00-amd-amdhsa < %s | FileCheck -check-prefix=CALLS %s +; RUN: llc -mtriple=amdgpu7.00-amd-amdhsa -amdgpu-function-calls=0 < %s | FileCheck -check-prefix=NOCALLS %s ; RUN: llc -mtriple=r600-mesa-mesa3d < %s | FileCheck -check-prefix=NOCALLS %s ; RUN: llc -mtriple=r600-mesa-mesa3d -amdgpu-function-calls=0 < %s | FileCheck -check-prefix=NOCALLS %s diff --git a/llvm/test/CodeGen/AMDGPU/array-ptr-calc-i64.ll b/llvm/test/CodeGen/AMDGPU/array-ptr-calc-i64.ll index 22b5838d36c45..c1f2dd7daa984 100644 --- a/llvm/test/CodeGen/AMDGPU/array-ptr-calc-i64.ll +++ b/llvm/test/CodeGen/AMDGPU/array-ptr-calc-i64.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -check-prefix=SI %s +; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck -check-prefix=SI %s declare i32 @llvm.amdgcn.mbcnt.lo(i32, i32) #0 declare i32 @llvm.amdgcn.mbcnt.hi(i32, i32) #0 diff --git a/llvm/test/CodeGen/AMDGPU/barrier-elimination.ll b/llvm/test/CodeGen/AMDGPU/barrier-elimination.ll index 257a51c85e6a0..6631155375172 100644 --- a/llvm/test/CodeGen/AMDGPU/barrier-elimination.ll +++ b/llvm/test/CodeGen/AMDGPU/barrier-elimination.ll @@ -1,5 +1,5 @@ -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s -global-isel | FileCheck %s +; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck %s +; RUN: llc -mtriple=amdgpu6.00 < %s -global-isel | FileCheck %s ; CHECK-LABEL: {{^}}unknown_wgs: ; CHECK: s_barrier diff --git a/llvm/test/CodeGen/AMDGPU/bfi_nested.ll b/llvm/test/CodeGen/AMDGPU/bfi_nested.ll index 5461155d875a2..6243f9ba0741c 100644 --- a/llvm/test/CodeGen/AMDGPU/bfi_nested.ll +++ b/llvm/test/CodeGen/AMDGPU/bfi_nested.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -enable-var-scope -check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck -enable-var-scope -check-prefix=GCN %s define float @v_bfi_single_nesting_level(float %x, float %y, float %z) { ; GCN-LABEL: v_bfi_single_nesting_level: diff --git a/llvm/test/CodeGen/AMDGPU/branch-relax-indirect-branch.mir b/llvm/test/CodeGen/AMDGPU/branch-relax-indirect-branch.mir index 62c06ac31d474..3fdcb314366ca 100644 --- a/llvm/test/CodeGen/AMDGPU/branch-relax-indirect-branch.mir +++ b/llvm/test/CodeGen/AMDGPU/branch-relax-indirect-branch.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -verify-machineinstrs -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 --amdgpu-s-branch-bits=5 -run-pass branch-relaxation %s -o - | FileCheck %s +# RUN: llc -verify-machineinstrs -mtriple=amdgpu7.00-amd-amdhsa --amdgpu-s-branch-bits=5 -run-pass branch-relaxation %s -o - | FileCheck %s --- name: branch_no_terminators diff --git a/llvm/test/CodeGen/AMDGPU/branch-uniformity.ll b/llvm/test/CodeGen/AMDGPU/branch-uniformity.ll index 9ee3e822cea59..a02e690b81152 100644 --- a/llvm/test/CodeGen/AMDGPU/branch-uniformity.ll +++ b/llvm/test/CodeGen/AMDGPU/branch-uniformity.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck %s +; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck %s ; The branch instruction in LOOP49 has a uniform condition, but PHI instructions ; introduced by the structurizecfg pass previously caused a false divergence diff --git a/llvm/test/CodeGen/AMDGPU/call-constant.ll b/llvm/test/CodeGen/AMDGPU/call-constant.ll index d09e0b1723831..8757089cf5dad 100644 --- a/llvm/test/CodeGen/AMDGPU/call-constant.ll +++ b/llvm/test/CodeGen/AMDGPU/call-constant.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 -; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 < %s | FileCheck -check-prefixes=GCN,SDAG %s -; RUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 < %s | FileCheck -check-prefixes=GCN,GISEL %s +; RUN: llc -global-isel=0 -mtriple=amdgpu7.00-amd-amdhsa < %s | FileCheck -check-prefixes=GCN,SDAG %s +; RUN: llc -global-isel=1 -mtriple=amdgpu7.00-amd-amdhsa < %s | FileCheck -check-prefixes=GCN,GISEL %s define amdgpu_kernel void @test_call_undef() #0 { ; SDAG-LABEL: test_call_undef: diff --git a/llvm/test/CodeGen/AMDGPU/call-constexpr.ll b/llvm/test/CodeGen/AMDGPU/call-constexpr.ll index 2799efe3f16d2..53867b9031f6b 100644 --- a/llvm/test/CodeGen/AMDGPU/call-constexpr.ll +++ b/llvm/test/CodeGen/AMDGPU/call-constexpr.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 -; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 < %s | FileCheck -check-prefixes=GCN,SDAG %s -; RUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 < %s | FileCheck -check-prefixes=GCN,GISEL %s +; RUN: llc -global-isel=0 -mtriple=amdgpu7.00-amd-amdhsa < %s | FileCheck -check-prefixes=GCN,SDAG %s +; RUN: llc -global-isel=1 -mtriple=amdgpu7.00-amd-amdhsa < %s | FileCheck -check-prefixes=GCN,GISEL %s define amdgpu_kernel void @test_bitcast_return_type_noinline() #0 { ; SDAG-LABEL: test_bitcast_return_type_noinline: diff --git a/llvm/test/CodeGen/AMDGPU/cf-loop-on-constant.ll b/llvm/test/CodeGen/AMDGPU/cf-loop-on-constant.ll index 637b5f95a7b62..a640ae1635d07 100644 --- a/llvm/test/CodeGen/AMDGPU/cf-loop-on-constant.ll +++ b/llvm/test/CodeGen/AMDGPU/cf-loop-on-constant.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -check-prefix=GCN %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 -O0 < %s | FileCheck -check-prefix=GCN_DBG %s +; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu6.00 -O0 < %s | FileCheck -check-prefix=GCN_DBG %s define amdgpu_kernel void @test_loop(ptr addrspace(3) %ptr, i32 %n) nounwind { ; GCN-LABEL: test_loop: diff --git a/llvm/test/CodeGen/AMDGPU/clamp-omod-special-case.mir b/llvm/test/CodeGen/AMDGPU/clamp-omod-special-case.mir index 020b392fe1348..9aa7bea2c4825 100644 --- a/llvm/test/CodeGen/AMDGPU/clamp-omod-special-case.mir +++ b/llvm/test/CodeGen/AMDGPU/clamp-omod-special-case.mir @@ -1,4 +1,4 @@ -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -verify-machineinstrs -run-pass si-fold-operands %s -o - | FileCheck -check-prefix=GCN %s +# RUN: llc -mtriple=amdgpu6.00 -verify-machineinstrs -run-pass si-fold-operands %s -o - | FileCheck -check-prefix=GCN %s --- # GCN-LABEL: name: v_max_self_clamp_not_set_f32 # GCN: %20:vgpr_32 = V_ADD_F32_e64 0, killed %17, 0, 1065353216, 0, 0, implicit $mode, implicit $exec diff --git a/llvm/test/CodeGen/AMDGPU/cndmask-no-def-vcc.ll b/llvm/test/CodeGen/AMDGPU/cndmask-no-def-vcc.ll index 44619c5516a8c..85dbfe0effd15 100644 --- a/llvm/test/CodeGen/AMDGPU/cndmask-no-def-vcc.ll +++ b/llvm/test/CodeGen/AMDGPU/cndmask-no-def-vcc.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck -check-prefix=GCN %s declare i1 @llvm.amdgcn.class.f32(float, i32) diff --git a/llvm/test/CodeGen/AMDGPU/coalescer-early-clobber-subreg.mir b/llvm/test/CodeGen/AMDGPU/coalescer-early-clobber-subreg.mir index 8c8c8284791c2..6b27581e317c1 100644 --- a/llvm/test/CodeGen/AMDGPU/coalescer-early-clobber-subreg.mir +++ b/llvm/test/CodeGen/AMDGPU/coalescer-early-clobber-subreg.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -verify-machineinstrs -run-pass=register-coalescer -o - %s | FileCheck %s +# RUN: llc -mtriple=amdgpu6.00 -verify-machineinstrs -run-pass=register-coalescer -o - %s | FileCheck %s # Test used to crash with message: # JoinVals::computeAssignment(unsigned int, (anonymous namespace)::JoinVals &): Assertion `Assignments[ValNo] != -1 && "Bad recursion?"' failed. diff --git a/llvm/test/CodeGen/AMDGPU/coalescer-identical-values-undef.mir b/llvm/test/CodeGen/AMDGPU/coalescer-identical-values-undef.mir index 57189d3174c3b..6e74e5b0fa0e0 100644 --- a/llvm/test/CodeGen/AMDGPU/coalescer-identical-values-undef.mir +++ b/llvm/test/CodeGen/AMDGPU/coalescer-identical-values-undef.mir @@ -1,4 +1,4 @@ -# RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx600 -run-pass=register-coalescer -o - %s | FileCheck %s +# RUN: llc -mtriple=amdgpu6.00--amdpal -run-pass=register-coalescer -o - %s | FileCheck %s # Check that this doesn't crash. Check for some legitimate output. # CHECK: S_CBRANCH_SCC1 diff --git a/llvm/test/CodeGen/AMDGPU/coalescer-subreg-join.mir b/llvm/test/CodeGen/AMDGPU/coalescer-subreg-join.mir index 59280c9070cfc..c661ed5266e7c 100644 --- a/llvm/test/CodeGen/AMDGPU/coalescer-subreg-join.mir +++ b/llvm/test/CodeGen/AMDGPU/coalescer-subreg-join.mir @@ -1,4 +1,4 @@ -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -run-pass register-coalescer -o - %s | FileCheck %s +# RUN: llc -mtriple=amdgpu6.00 -run-pass register-coalescer -o - %s | FileCheck %s # Check that %11 and %20 have been coalesced. # CHECK: IMAGE_SAMPLE_C_D_O_V1_V11 %[[REG:[0-9]+]] # CHECK: IMAGE_SAMPLE_C_D_O_V1_V11 %[[REG]] diff --git a/llvm/test/CodeGen/AMDGPU/coalescer_remat.ll b/llvm/test/CodeGen/AMDGPU/coalescer_remat.ll index 8690f28555913..33f901b7c70cd 100644 --- a/llvm/test/CodeGen/AMDGPU/coalescer_remat.ll +++ b/llvm/test/CodeGen/AMDGPU/coalescer_remat.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn-- -mcpu=gfx600 -o - %s | FileCheck %s +; RUN: llc -mtriple=amdgpu6.00-- -o - %s | FileCheck %s declare float @llvm.fma.f32(float, float, float) diff --git a/llvm/test/CodeGen/AMDGPU/collapse-endcf-broken.mir b/llvm/test/CodeGen/AMDGPU/collapse-endcf-broken.mir index 1da5a0fbb0ab8..b7f36c5dcd542 100644 --- a/llvm/test/CodeGen/AMDGPU/collapse-endcf-broken.mir +++ b/llvm/test/CodeGen/AMDGPU/collapse-endcf-broken.mir @@ -1,6 +1,6 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -verify-machineinstrs -run-pass=si-optimize-exec-masking-pre-ra %s -o - | FileCheck -check-prefix=GXN %s -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -verify-machineinstrs -passes=si-optimize-exec-masking-pre-ra %s -o - | FileCheck -check-prefix=GXN %s +# RUN: llc -mtriple=amdgpu6.00 -verify-machineinstrs -run-pass=si-optimize-exec-masking-pre-ra %s -o - | FileCheck -check-prefix=GXN %s +# RUN: llc -mtriple=amdgpu6.00 -verify-machineinstrs -passes=si-optimize-exec-masking-pre-ra %s -o - | FileCheck -check-prefix=GXN %s # FIXME: This is a miscompile, and the s_or_b64s need to be preserved. diff --git a/llvm/test/CodeGen/AMDGPU/collapse-endcf.mir b/llvm/test/CodeGen/AMDGPU/collapse-endcf.mir index dc22ca2859e0d..c434737e6dc28 100644 --- a/llvm/test/CodeGen/AMDGPU/collapse-endcf.mir +++ b/llvm/test/CodeGen/AMDGPU/collapse-endcf.mir @@ -1,6 +1,6 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -verify-machineinstrs -run-pass=si-lower-control-flow -amdgpu-remove-redundant-endcf %s -o - | FileCheck -check-prefix=GCN %s -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -passes=si-lower-control-flow -amdgpu-remove-redundant-endcf %s -o - | FileCheck -check-prefix=GCN %s +# RUN: llc -mtriple=amdgpu6.00 -verify-machineinstrs -run-pass=si-lower-control-flow -amdgpu-remove-redundant-endcf %s -o - | FileCheck -check-prefix=GCN %s +# RUN: llc -mtriple=amdgpu6.00 -passes=si-lower-control-flow -amdgpu-remove-redundant-endcf %s -o - | FileCheck -check-prefix=GCN %s # Make sure dbg_value doesn't change codeegn when collapsing end_cf --- diff --git a/llvm/test/CodeGen/AMDGPU/collapse-endcf2.mir b/llvm/test/CodeGen/AMDGPU/collapse-endcf2.mir index 173098708e009..afa46f7877892 100644 --- a/llvm/test/CodeGen/AMDGPU/collapse-endcf2.mir +++ b/llvm/test/CodeGen/AMDGPU/collapse-endcf2.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -verify-machineinstrs -run-pass=si-optimize-exec-masking-pre-ra %s -o - | FileCheck -check-prefix=GCN %s +# RUN: llc -mtriple=amdgpu6.00 -verify-machineinstrs -run-pass=si-optimize-exec-masking-pre-ra %s -o - | FileCheck -check-prefix=GCN %s --- | define amdgpu_kernel void @call_no_explicit_exec_dependency () { diff --git a/llvm/test/CodeGen/AMDGPU/combine-and-sext-bool.ll b/llvm/test/CodeGen/AMDGPU/combine-and-sext-bool.ll index 4452366c8a5fa..c18d2234470ae 100644 --- a/llvm/test/CodeGen/AMDGPU/combine-and-sext-bool.ll +++ b/llvm/test/CodeGen/AMDGPU/combine-and-sext-bool.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck -check-prefix=GCN %s define amdgpu_kernel void @and_i1_sext_bool(ptr addrspace(1) nocapture %arg) { ; GCN-LABEL: and_i1_sext_bool: diff --git a/llvm/test/CodeGen/AMDGPU/combine-reg-or-const.ll b/llvm/test/CodeGen/AMDGPU/combine-reg-or-const.ll index 2783f31c0ec1d..e0bd039db2a87 100644 --- a/llvm/test/CodeGen/AMDGPU/combine-reg-or-const.ll +++ b/llvm/test/CodeGen/AMDGPU/combine-reg-or-const.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -o - %s | FileCheck %s +; RUN: llc -mtriple=amdgpu7.00-amd-amdhsa -o - %s | FileCheck %s ; The OR instruction should not be eliminated by the "OR Combine" DAG optimization. define protected amdgpu_kernel void @_Z11test_kernelPii(ptr addrspace(1) nocapture %Ad.coerce, i32 %s) local_unnamed_addr #5 { diff --git a/llvm/test/CodeGen/AMDGPU/combine-sreg64-inits.mir b/llvm/test/CodeGen/AMDGPU/combine-sreg64-inits.mir index 2c24b863b154e..f20e3c9ed398b 100644 --- a/llvm/test/CodeGen/AMDGPU/combine-sreg64-inits.mir +++ b/llvm/test/CodeGen/AMDGPU/combine-sreg64-inits.mir @@ -1,6 +1,6 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -verify-machineinstrs -run-pass=amdgpu-pre-ra-optimizations %s -o - | FileCheck -check-prefix=GCN %s -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -passes="amdgpu-pre-ra-optimizations" %s -o - | FileCheck -check-prefix=GCN %s +# RUN: llc -mtriple=amdgpu6.00 -verify-machineinstrs -run-pass=amdgpu-pre-ra-optimizations %s -o - | FileCheck -check-prefix=GCN %s +# RUN: llc -mtriple=amdgpu6.00 -passes="amdgpu-pre-ra-optimizations" %s -o - | FileCheck -check-prefix=GCN %s --- name: combine_sreg64_inits diff --git a/llvm/test/CodeGen/AMDGPU/commute-compares.ll b/llvm/test/CodeGen/AMDGPU/commute-compares.ll index 75b634fbb6190..e191fbd75e280 100644 --- a/llvm/test/CodeGen/AMDGPU/commute-compares.ll +++ b/llvm/test/CodeGen/AMDGPU/commute-compares.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 -amdgpu-sdwa-peephole=0 < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu6.00 -amdgpu-sdwa-peephole=0 < %s | FileCheck -check-prefix=GCN %s declare i32 @llvm.amdgcn.workitem.id.x() #0 diff --git a/llvm/test/CodeGen/AMDGPU/commute_modifiers.ll b/llvm/test/CodeGen/AMDGPU/commute_modifiers.ll index 59f528ca1a029..9755eb272a9d5 100644 --- a/llvm/test/CodeGen/AMDGPU/commute_modifiers.ll +++ b/llvm/test/CodeGen/AMDGPU/commute_modifiers.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s +; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s declare i32 @llvm.amdgcn.workitem.id.x() #1 declare float @llvm.fabs.f32(float) #1 diff --git a/llvm/test/CodeGen/AMDGPU/control-flow-fastregalloc.ll b/llvm/test/CodeGen/AMDGPU/control-flow-fastregalloc.ll index ae5fd2c7fdec3..dcc3fa5bf13c8 100644 --- a/llvm/test/CodeGen/AMDGPU/control-flow-fastregalloc.ll +++ b/llvm/test/CodeGen/AMDGPU/control-flow-fastregalloc.ll @@ -1,5 +1,5 @@ -; RUN: llc -O0 -mtriple=amdgcn--amdhsa -mcpu=gfx700 -amdgpu-spill-sgpr-to-vgpr=0 < %s | FileCheck -enable-var-scope -check-prefix=VMEM -check-prefix=GCN %s -; RUN: llc -O0 -mtriple=amdgcn--amdhsa -mcpu=gfx700 -amdgpu-spill-sgpr-to-vgpr=1 < %s | FileCheck -enable-var-scope -check-prefix=VGPR -check-prefix=GCN %s +; RUN: llc -O0 -mtriple=amdgpu7.00--amdhsa -amdgpu-spill-sgpr-to-vgpr=0 < %s | FileCheck -enable-var-scope -check-prefix=VMEM -check-prefix=GCN %s +; RUN: llc -O0 -mtriple=amdgpu7.00--amdhsa -amdgpu-spill-sgpr-to-vgpr=1 < %s | FileCheck -enable-var-scope -check-prefix=VGPR -check-prefix=GCN %s ; Verify registers used for tracking exec mask changes when all ; registers are spilled at the end of the block. The SGPR spill diff --git a/llvm/test/CodeGen/AMDGPU/control-flow-optnone.ll b/llvm/test/CodeGen/AMDGPU/control-flow-optnone.ll index c0eccd0425c7d..94c0b9620aae5 100644 --- a/llvm/test/CodeGen/AMDGPU/control-flow-optnone.ll +++ b/llvm/test/CodeGen/AMDGPU/control-flow-optnone.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu7.00-amd-amdhsa < %s | FileCheck -check-prefix=GCN %s ; optnone disables AMDGPUAnnotateUniformValues, so no branch is known ; to be uniform during instruction selection. The custom selection for diff --git a/llvm/test/CodeGen/AMDGPU/convergent-inlineasm.ll b/llvm/test/CodeGen/AMDGPU/convergent-inlineasm.ll index c2118a8084b38..eaca8f6dc029c 100644 --- a/llvm/test/CodeGen/AMDGPU/convergent-inlineasm.ll +++ b/llvm/test/CodeGen/AMDGPU/convergent-inlineasm.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx700 < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu7.00--amdhsa < %s | FileCheck -check-prefix=GCN %s declare i32 @llvm.amdgcn.workitem.id.x() #0 ; GCN-LABEL: {{^}}convergent_inlineasm: diff --git a/llvm/test/CodeGen/AMDGPU/copyprop_regsequence_with_undef.mir b/llvm/test/CodeGen/AMDGPU/copyprop_regsequence_with_undef.mir index b982929a94515..81919544582b3 100644 --- a/llvm/test/CodeGen/AMDGPU/copyprop_regsequence_with_undef.mir +++ b/llvm/test/CodeGen/AMDGPU/copyprop_regsequence_with_undef.mir @@ -1,6 +1,6 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -run-pass=machine-cse -verify-machineinstrs -o - %s | FileCheck %s -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -passes=machine-cse -o - %s | FileCheck %s +# RUN: llc -mtriple=amdgpu6.00 -run-pass=machine-cse -verify-machineinstrs -o - %s | FileCheck %s +# RUN: llc -mtriple=amdgpu6.00 -passes=machine-cse -o - %s | FileCheck %s # Test to ensure that this does not crash on undefs --- diff --git a/llvm/test/CodeGen/AMDGPU/cttz-elts.ll b/llvm/test/CodeGen/AMDGPU/cttz-elts.ll index a34a246cbce3b..6e4703810b6fd 100644 --- a/llvm/test/CodeGen/AMDGPU/cttz-elts.ll +++ b/llvm/test/CodeGen/AMDGPU/cttz-elts.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck %s +; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck %s define i32 @v1i1(<1 x i1> %x) { ; CHECK-LABEL: v1i1: diff --git a/llvm/test/CodeGen/AMDGPU/dagcomb-shuffle-vecextend-non2.ll b/llvm/test/CodeGen/AMDGPU/dagcomb-shuffle-vecextend-non2.ll index ebb17c0fd16ae..920cd1120bd58 100644 --- a/llvm/test/CodeGen/AMDGPU/dagcomb-shuffle-vecextend-non2.ll +++ b/llvm/test/CodeGen/AMDGPU/dagcomb-shuffle-vecextend-non2.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck -check-prefix=GCN %s ; We are only checking that instruction selection can succeed in this case. This ; cut down test results in no instructions, but that's fine. diff --git a/llvm/test/CodeGen/AMDGPU/dagcombine-lshr-and-cmp.ll b/llvm/test/CodeGen/AMDGPU/dagcombine-lshr-and-cmp.ll index 0dd3a223502c6..1d238989f6aff 100644 --- a/llvm/test/CodeGen/AMDGPU/dagcombine-lshr-and-cmp.ll +++ b/llvm/test/CodeGen/AMDGPU/dagcombine-lshr-and-cmp.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -; RUN: llc -mtriple=amdgcn-- -mcpu=gfx600 -stop-after=amdgpu-isel -O0 < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu6.00-- -stop-after=amdgpu-isel -O0 < %s | FileCheck -check-prefix=GCN %s define i32 @divergent_lshr_and_cmp(i32 %x) { ; GCN-LABEL: name: divergent_lshr_and_cmp diff --git a/llvm/test/CodeGen/AMDGPU/dagcombine-reassociate-bug.ll b/llvm/test/CodeGen/AMDGPU/dagcombine-reassociate-bug.ll index 48afbf8ef5af4..f7689b55d157a 100644 --- a/llvm/test/CodeGen/AMDGPU/dagcombine-reassociate-bug.ll +++ b/llvm/test/CodeGen/AMDGPU/dagcombine-reassociate-bug.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 -amdgpu-scalar-ir-passes=false < %s | FileCheck %s +; RUN: llc -mtriple=amdgpu6.00 -amdgpu-scalar-ir-passes=false < %s | FileCheck %s ; Test for a bug where DAGCombiner::ReassociateOps() was creating adds ; with offset in the first operand and base pointers in the second. diff --git a/llvm/test/CodeGen/AMDGPU/dce-disjoint-intervals.mir b/llvm/test/CodeGen/AMDGPU/dce-disjoint-intervals.mir index cb9008dabbae5..f393c59ab3f11 100644 --- a/llvm/test/CodeGen/AMDGPU/dce-disjoint-intervals.mir +++ b/llvm/test/CodeGen/AMDGPU/dce-disjoint-intervals.mir @@ -1,4 +1,4 @@ -# RUN: llc -mtriple=amdgcn-- -mcpu=gfx600 -run-pass=liveintervals,dead-mi-elimination,register-coalescer -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s +# RUN: llc -mtriple=amdgpu6.00-- -run-pass=liveintervals,dead-mi-elimination,register-coalescer -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s # This is used to fail verififcation if MachineDCE tracks LIS. diff --git a/llvm/test/CodeGen/AMDGPU/debug-value2.ll b/llvm/test/CodeGen/AMDGPU/debug-value2.ll index 35540ca38fa31..eaa0627a5030a 100644 --- a/llvm/test/CodeGen/AMDGPU/debug-value2.ll +++ b/llvm/test/CodeGen/AMDGPU/debug-value2.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 < %s | FileCheck %s +; RUN: llc -mtriple=amdgpu7.00-amd-amdhsa < %s | FileCheck %s %struct.ShapeData = type { <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, i32, i32, i64, <4 x float>, i32, i8, i8, i16, i32, i32 } diff --git a/llvm/test/CodeGen/AMDGPU/debug_frame.ll b/llvm/test/CodeGen/AMDGPU/debug_frame.ll index 2c8a97f473814..29f48b628c051 100644 --- a/llvm/test/CodeGen/AMDGPU/debug_frame.ll +++ b/llvm/test/CodeGen/AMDGPU/debug_frame.ll @@ -1,7 +1,7 @@ -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -o - < %s | FileCheck %s -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 --force-dwarf-frame-section -o - < %s | FileCheck %s -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 --exception-model=dwarf -o - < %s | FileCheck %s -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 --force-dwarf-frame-section --exception-model=dwarf -o - < %s | FileCheck %s +; RUN: llc -mtriple=amdgpu7.00-amd-amdhsa -o - < %s | FileCheck %s +; RUN: llc -mtriple=amdgpu7.00-amd-amdhsa --force-dwarf-frame-section -o - < %s | FileCheck %s +; RUN: llc -mtriple=amdgpu7.00-amd-amdhsa --exception-model=dwarf -o - < %s | FileCheck %s +; RUN: llc -mtriple=amdgpu7.00-amd-amdhsa --force-dwarf-frame-section --exception-model=dwarf -o - < %s | FileCheck %s ; CHECK: .cfi_sections .debug_frame diff --git a/llvm/test/CodeGen/AMDGPU/default_amdhsa_code_object_version.ll b/llvm/test/CodeGen/AMDGPU/default_amdhsa_code_object_version.ll index 6075a8c6032d0..5613aef35447a 100644 --- a/llvm/test/CodeGen/AMDGPU/default_amdhsa_code_object_version.ll +++ b/llvm/test/CodeGen/AMDGPU/default_amdhsa_code_object_version.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 %s -o - | FileCheck %s +; RUN: llc -mtriple=amdgpu7.00-amd-amdhsa %s -o - | FileCheck %s ; CHECK: .amdhsa_code_object_version 6 diff --git a/llvm/test/CodeGen/AMDGPU/detect-dead-lanes.mir b/llvm/test/CodeGen/AMDGPU/detect-dead-lanes.mir index f276c40df7d99..0d467bb3cad43 100644 --- a/llvm/test/CodeGen/AMDGPU/detect-dead-lanes.mir +++ b/llvm/test/CodeGen/AMDGPU/detect-dead-lanes.mir @@ -1,5 +1,5 @@ -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -run-pass detect-dead-lanes -o - %s | FileCheck %s -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -passes detect-dead-lanes -o - %s | FileCheck %s +# RUN: llc -mtriple=amdgpu6.00 -run-pass detect-dead-lanes -o - %s | FileCheck %s +# RUN: llc -mtriple=amdgpu6.00 -passes detect-dead-lanes -o - %s | FileCheck %s ... --- # Combined use/def transfer check, the basics. diff --git a/llvm/test/CodeGen/AMDGPU/div_v2i128.ll b/llvm/test/CodeGen/AMDGPU/div_v2i128.ll index db6dc08e185fc..df15c2d9e0601 100644 --- a/llvm/test/CodeGen/AMDGPU/div_v2i128.ll +++ b/llvm/test/CodeGen/AMDGPU/div_v2i128.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 -; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -o - %s | FileCheck -check-prefix=SDAG %s -; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -o - %s | FileCheck -check-prefix=GISEL %s +; RUN: llc -global-isel=0 -mtriple=amdgpu7.00-amd-amdhsa -o - %s | FileCheck -check-prefix=SDAG %s +; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgpu7.00-amd-amdhsa -o - %s | FileCheck -check-prefix=GISEL %s define <2 x i128> @v_sdiv_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) { ; SDAG-LABEL: v_sdiv_v2i128_vv: diff --git a/llvm/test/CodeGen/AMDGPU/divergence-driven-bfe-isel.ll b/llvm/test/CodeGen/AMDGPU/divergence-driven-bfe-isel.ll index e01e227182347..6065d552b4200 100644 --- a/llvm/test/CodeGen/AMDGPU/divergence-driven-bfe-isel.ll +++ b/llvm/test/CodeGen/AMDGPU/divergence-driven-bfe-isel.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck -check-prefix=GCN %s ; GCN-LABEL: @bfe_uniform ; GCN: s_bfe_u32 s{{[0-9]+}}, s{{[0-9]+}}, 0x40010 diff --git a/llvm/test/CodeGen/AMDGPU/divergence-driven-bitreverse.ll b/llvm/test/CodeGen/AMDGPU/divergence-driven-bitreverse.ll index 8133ac50d2c27..0258380dfab91 100644 --- a/llvm/test/CodeGen/AMDGPU/divergence-driven-bitreverse.ll +++ b/llvm/test/CodeGen/AMDGPU/divergence-driven-bitreverse.ll @@ -1,5 +1,5 @@ -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GCN %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 -enable-new-pm -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu6.00 -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu6.00 -enable-new-pm -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GCN %s ; GCN-LABEL: name: uniform_bitreverse_i32 ; GCN: S_BREV_B32 diff --git a/llvm/test/CodeGen/AMDGPU/divergence-driven-ctlz-cttz.ll b/llvm/test/CodeGen/AMDGPU/divergence-driven-ctlz-cttz.ll index 39654149ad7bd..8ff6049e8291c 100644 --- a/llvm/test/CodeGen/AMDGPU/divergence-driven-ctlz-cttz.ll +++ b/llvm/test/CodeGen/AMDGPU/divergence-driven-ctlz-cttz.ll @@ -1,5 +1,5 @@ -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GCN %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 -enable-new-pm -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu6.00 -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu6.00 -enable-new-pm -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GCN %s ; GCN-LABEL: name: s_ctlz_i32 ; GCN: S_FLBIT_I32_B32 diff --git a/llvm/test/CodeGen/AMDGPU/divergence-driven-ctpop.ll b/llvm/test/CodeGen/AMDGPU/divergence-driven-ctpop.ll index 203341359381a..6b675554de346 100644 --- a/llvm/test/CodeGen/AMDGPU/divergence-driven-ctpop.ll +++ b/llvm/test/CodeGen/AMDGPU/divergence-driven-ctpop.ll @@ -1,5 +1,5 @@ -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GCN %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 -enable-new-pm -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu6.00 -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu6.00 -enable-new-pm -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GCN %s ; GCN-LABEL: name: s_ctpop_i32 ; GCN: S_BCNT1_I32_B32 diff --git a/llvm/test/CodeGen/AMDGPU/divergence-driven-min-max.ll b/llvm/test/CodeGen/AMDGPU/divergence-driven-min-max.ll index 0036b0e17af76..dd8182e2005ef 100644 --- a/llvm/test/CodeGen/AMDGPU/divergence-driven-min-max.ll +++ b/llvm/test/CodeGen/AMDGPU/divergence-driven-min-max.ll @@ -1,5 +1,5 @@ -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GCN %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 -enable-new-pm -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu6.00 -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu6.00 -enable-new-pm -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GCN %s ; GCN-LABEL: name: uniform_imin ; GCN: S_MIN_I32 diff --git a/llvm/test/CodeGen/AMDGPU/divergence-driven-not-isel.ll b/llvm/test/CodeGen/AMDGPU/divergence-driven-not-isel.ll index b7caadab4b223..972a8f2be8116 100644 --- a/llvm/test/CodeGen/AMDGPU/divergence-driven-not-isel.ll +++ b/llvm/test/CodeGen/AMDGPU/divergence-driven-not-isel.ll @@ -1,5 +1,5 @@ -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GCN %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 -enable-new-pm -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu6.00 -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu6.00 -enable-new-pm -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GCN %s ; GCN-LABEL: name: scalar_not_i32 ; GCN: S_NOT_B32 diff --git a/llvm/test/CodeGen/AMDGPU/divergence-driven-sext-inreg.ll b/llvm/test/CodeGen/AMDGPU/divergence-driven-sext-inreg.ll index 70174a1d4fd10..11237953a07bc 100644 --- a/llvm/test/CodeGen/AMDGPU/divergence-driven-sext-inreg.ll +++ b/llvm/test/CodeGen/AMDGPU/divergence-driven-sext-inreg.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -enable-var-scope --check-prefixes=GCN %s +; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck -enable-var-scope --check-prefixes=GCN %s define amdgpu_kernel void @uniform_sext_in_reg_i8_to_i32(ptr addrspace(1) %out, i32 %a, i32 %b) #0 { ; GCN-LABEL: uniform_sext_in_reg_i8_to_i32: diff --git a/llvm/test/CodeGen/AMDGPU/divergence-driven-trunc-to-i1.ll b/llvm/test/CodeGen/AMDGPU/divergence-driven-trunc-to-i1.ll index 5e0947b2c95c5..3d88221af213b 100644 --- a/llvm/test/CodeGen/AMDGPU/divergence-driven-trunc-to-i1.ll +++ b/llvm/test/CodeGen/AMDGPU/divergence-driven-trunc-to-i1.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu6.00 -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GCN %s define amdgpu_kernel void @uniform_trunc_i16_to_i1(ptr addrspace(1) %out, i16 %x, i1 %z) { ; GCN-LABEL: name: uniform_trunc_i16_to_i1 diff --git a/llvm/test/CodeGen/AMDGPU/enable-no-signed-zeros-fp-math.ll b/llvm/test/CodeGen/AMDGPU/enable-no-signed-zeros-fp-math.ll index 3ae8644e1b8c1..aced4bfc0f98a 100644 --- a/llvm/test/CodeGen/AMDGPU/enable-no-signed-zeros-fp-math.ll +++ b/llvm/test/CodeGen/AMDGPU/enable-no-signed-zeros-fp-math.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck --check-prefixes=GCN,GCN-FMF,GCN-SAFE %s +; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck --check-prefixes=GCN,GCN-FMF,GCN-SAFE %s declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone diff --git a/llvm/test/CodeGen/AMDGPU/endcf-loop-header.ll b/llvm/test/CodeGen/AMDGPU/endcf-loop-header.ll index 877f07a50f052..4267111b4072d 100644 --- a/llvm/test/CodeGen/AMDGPU/endcf-loop-header.ll +++ b/llvm/test/CodeGen/AMDGPU/endcf-loop-header.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx600 | FileCheck %s +; RUN: llc < %s -mtriple=amdgpu6.00 | FileCheck %s ; This tests that the llvm.SI.end.cf intrinsic is not inserted into the ; loop block. This intrinsic will be lowered to s_or_b64 by the code diff --git a/llvm/test/CodeGen/AMDGPU/endpgm-dce.mir b/llvm/test/CodeGen/AMDGPU/endpgm-dce.mir index 2f0a3c693cf47..975ab1944aeee 100644 --- a/llvm/test/CodeGen/AMDGPU/endpgm-dce.mir +++ b/llvm/test/CodeGen/AMDGPU/endpgm-dce.mir @@ -1,4 +1,4 @@ -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -verify-machineinstrs -run-pass si-optimize-exec-masking-pre-ra %s -o - | FileCheck -check-prefix=GCN %s +# RUN: llc -mtriple=amdgpu6.00 -verify-machineinstrs -run-pass si-optimize-exec-masking-pre-ra %s -o - | FileCheck -check-prefix=GCN %s # GCN-LABEL: name: kill_all # GCN: bb.0: diff --git a/llvm/test/CodeGen/AMDGPU/extload-align.ll b/llvm/test/CodeGen/AMDGPU/extload-align.ll index a1c4843ce0b3c..023a8679a5a42 100644 --- a/llvm/test/CodeGen/AMDGPU/extload-align.ll +++ b/llvm/test/CodeGen/AMDGPU/extload-align.ll @@ -1,4 +1,4 @@ -; RUN: llc -debug-only=machine-scheduler -mtriple=amdgcn-- -mcpu=gfx600 %s -o - 2>&1| FileCheck -check-prefix=DEBUG %s +; RUN: llc -debug-only=machine-scheduler -mtriple=amdgpu6.00-- %s -o - 2>&1| FileCheck -check-prefix=DEBUG %s ; REQUIRES: asserts ; Verify that the extload generated from %eval has the default diff --git a/llvm/test/CodeGen/AMDGPU/extract-load-i1.ll b/llvm/test/CodeGen/AMDGPU/extract-load-i1.ll index 634ab8b8bdb07..39025365a6e58 100644 --- a/llvm/test/CodeGen/AMDGPU/extract-load-i1.ll +++ b/llvm/test/CodeGen/AMDGPU/extract-load-i1.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 < %s | FileCheck %s +; RUN: llc -mtriple=amdgpu7.00-amd-amdhsa < %s | FileCheck %s ; FIXME: Inefficient codegen which skips an optimization of load + ; extractelement when the vector element type is not byte-sized. diff --git a/llvm/test/CodeGen/AMDGPU/extract-subvector-equal-length.ll b/llvm/test/CodeGen/AMDGPU/extract-subvector-equal-length.ll index 3d4dc0fe824d0..38f9c33e05aa0 100644 --- a/llvm/test/CodeGen/AMDGPU/extract-subvector-equal-length.ll +++ b/llvm/test/CodeGen/AMDGPU/extract-subvector-equal-length.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=amdgcn-- -mcpu=gfx600 < %s | FileCheck %s +; RUN: llc -mtriple=amdgpu6.00-- < %s | FileCheck %s ; Test for ICE in SelectionDAG::computeKnownBits when visiting EXTRACT_SUBVECTOR ; with DemandedElts already as wide as the source vector. diff --git a/llvm/test/CodeGen/AMDGPU/extract-subvector.ll b/llvm/test/CodeGen/AMDGPU/extract-subvector.ll index 130c8563c9a4c..cd58a256b5101 100644 --- a/llvm/test/CodeGen/AMDGPU/extract-subvector.ll +++ b/llvm/test/CodeGen/AMDGPU/extract-subvector.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 -; RUN: llc -mtriple=amdgcn-- -mcpu=gfx600 -o - %s | FileCheck -check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu6.00-- -o - %s | FileCheck -check-prefix=GCN %s define <2 x i16> @extract_2xi16(ptr addrspace(1) %p0, ptr addrspace(1) %p1, i1 %c0) { ; GCN-LABEL: extract_2xi16: diff --git a/llvm/test/CodeGen/AMDGPU/extract-vector-elt-build-vector-combine.ll b/llvm/test/CodeGen/AMDGPU/extract-vector-elt-build-vector-combine.ll index 601974f2afadc..06252c3c108ab 100644 --- a/llvm/test/CodeGen/AMDGPU/extract-vector-elt-build-vector-combine.ll +++ b/llvm/test/CodeGen/AMDGPU/extract-vector-elt-build-vector-combine.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck -check-prefix=GCN %s ; GCN-LABEL: {{^}}store_build_vector_multiple_uses_v4i32: ; GCN: buffer_load_dword diff --git a/llvm/test/CodeGen/AMDGPU/extractelt-to-trunc.ll b/llvm/test/CodeGen/AMDGPU/extractelt-to-trunc.ll index a4552bf4d61b4..c623fb44b94f6 100644 --- a/llvm/test/CodeGen/AMDGPU/extractelt-to-trunc.ll +++ b/llvm/test/CodeGen/AMDGPU/extractelt-to-trunc.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -mtriple=amdgcn-- -mcpu=gfx600 | FileCheck %s -check-prefix=GCN +; RUN: llc < %s -mtriple=amdgpu6.00-- | FileCheck %s -check-prefix=GCN declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone diff --git a/llvm/test/CodeGen/AMDGPU/fabs.f64.ll b/llvm/test/CodeGen/AMDGPU/fabs.f64.ll index 6e46597b23f24..e7cc6e0a8e910 100644 --- a/llvm/test/CodeGen/AMDGPU/fabs.f64.ll +++ b/llvm/test/CodeGen/AMDGPU/fabs.f64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -check-prefix=SI %s +; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck -check-prefix=SI %s declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone diff --git a/llvm/test/CodeGen/AMDGPU/fadd-fma-fmul-combine.ll b/llvm/test/CodeGen/AMDGPU/fadd-fma-fmul-combine.ll index a9fcf9228a16e..ed2bebeda941d 100644 --- a/llvm/test/CodeGen/AMDGPU/fadd-fma-fmul-combine.ll +++ b/llvm/test/CodeGen/AMDGPU/fadd-fma-fmul-combine.ll @@ -1,9 +1,9 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 -mattr=+fast-fmaf,+mad-mac-f32-insts -denormal-fp-math-f32=preserve-sign < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-FLUSH %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 -mattr=-fast-fmaf,+mad-mac-f32-insts -denormal-fp-math-f32=preserve-sign < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-FLUSH %s +; RUN: llc -mtriple=amdgpu6.00 -mattr=+fast-fmaf,+mad-mac-f32-insts -denormal-fp-math-f32=preserve-sign < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-FLUSH %s +; RUN: llc -mtriple=amdgpu6.00 -mattr=-fast-fmaf,+mad-mac-f32-insts -denormal-fp-math-f32=preserve-sign < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-FLUSH %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 -mattr=+fast-fmaf,+mad-mac-f32-insts -denormal-fp-math-f32=ieee < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-FASTFMA %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 -mattr=-fast-fmaf,+mad-mac-f32-insts -denormal-fp-math-f32=ieee < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-SLOWFMA %s +; RUN: llc -mtriple=amdgpu6.00 -mattr=+fast-fmaf,+mad-mac-f32-insts -denormal-fp-math-f32=ieee < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-FASTFMA %s +; RUN: llc -mtriple=amdgpu6.00 -mattr=-fast-fmaf,+mad-mac-f32-insts -denormal-fp-math-f32=ieee < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-SLOWFMA %s ; FIXME: This should also fold when fma is actually fast if an FMA ; exists in the original program. diff --git a/llvm/test/CodeGen/AMDGPU/fix-sgpr-copies.mir b/llvm/test/CodeGen/AMDGPU/fix-sgpr-copies.mir index d1d82b92e534b..28b0420f28143 100644 --- a/llvm/test/CodeGen/AMDGPU/fix-sgpr-copies.mir +++ b/llvm/test/CodeGen/AMDGPU/fix-sgpr-copies.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -run-pass=si-fix-sgpr-copies -verify-machineinstrs -o - %s | FileCheck --check-prefix=GCN %s +# RUN: llc -mtriple=amdgpu6.00 -run-pass=si-fix-sgpr-copies -verify-machineinstrs -o - %s | FileCheck --check-prefix=GCN %s # GCN-LABEL: name: fix-sgpr-copies # GCN: V_ADD_CO_U32_e32 diff --git a/llvm/test/CodeGen/AMDGPU/fix-vgpr-copies.mir b/llvm/test/CodeGen/AMDGPU/fix-vgpr-copies.mir index de48b1b79565f..14542e10318db 100644 --- a/llvm/test/CodeGen/AMDGPU/fix-vgpr-copies.mir +++ b/llvm/test/CodeGen/AMDGPU/fix-vgpr-copies.mir @@ -1,5 +1,5 @@ -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -start-after=greedy -disable-copyprop -stop-after=si-optimize-exec-masking -o - %s | FileCheck %s -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -passes=si-fix-vgpr-copies,si-optimize-exec-masking -o - %s | FileCheck %s +# RUN: llc -mtriple=amdgpu6.00 -start-after=greedy -disable-copyprop -stop-after=si-optimize-exec-masking -o - %s | FileCheck %s +# RUN: llc -mtriple=amdgpu6.00 -passes=si-fix-vgpr-copies,si-optimize-exec-masking -o - %s | FileCheck %s # Check that we first do all vector instructions and only then change exec # CHECK-DAG: COPY $vgpr10_vgpr11 diff --git a/llvm/test/CodeGen/AMDGPU/fold-cndmask.mir b/llvm/test/CodeGen/AMDGPU/fold-cndmask.mir index 6a7e8de72c651..366e1d67f1f5f 100644 --- a/llvm/test/CodeGen/AMDGPU/fold-cndmask.mir +++ b/llvm/test/CodeGen/AMDGPU/fold-cndmask.mir @@ -1,4 +1,4 @@ -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -run-pass si-fold-operands -verify-machineinstrs -o - %s | FileCheck %s +# RUN: llc -mtriple=amdgpu6.00 -run-pass si-fold-operands -verify-machineinstrs -o - %s | FileCheck %s # CHECK: %1:vgpr_32 = V_MOV_B32_e32 0, implicit $exec # CHECK: %2:vgpr_32 = V_MOV_B32_e32 0, implicit $exec diff --git a/llvm/test/CodeGen/AMDGPU/fold-fi-mubuf.mir b/llvm/test/CodeGen/AMDGPU/fold-fi-mubuf.mir index aa2890f7331e2..6618a6dc6b7e6 100644 --- a/llvm/test/CodeGen/AMDGPU/fold-fi-mubuf.mir +++ b/llvm/test/CodeGen/AMDGPU/fold-fi-mubuf.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -verify-machineinstrs -run-pass si-fold-operands,dead-mi-elimination %s -o - | FileCheck -check-prefix=GCN %s +# RUN: llc -mtriple=amdgpu7.00-amd-amdhsa -verify-machineinstrs -run-pass si-fold-operands,dead-mi-elimination %s -o - | FileCheck -check-prefix=GCN %s # Kernels can have no FP --- diff --git a/llvm/test/CodeGen/AMDGPU/fold-fi-operand-shrink.mir b/llvm/test/CodeGen/AMDGPU/fold-fi-operand-shrink.mir index 18b7e4e6a44fe..576095af50950 100644 --- a/llvm/test/CodeGen/AMDGPU/fold-fi-operand-shrink.mir +++ b/llvm/test/CodeGen/AMDGPU/fold-fi-operand-shrink.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -verify-machineinstrs -run-pass si-fold-operands,dead-mi-elimination %s -o - | FileCheck -check-prefix=GCN %s +# RUN: llc -mtriple=amdgpu7.00-amd-amdhsa -verify-machineinstrs -run-pass si-fold-operands,dead-mi-elimination %s -o - | FileCheck -check-prefix=GCN %s --- diff --git a/llvm/test/CodeGen/AMDGPU/fold-fmul-to-neg-abs.ll b/llvm/test/CodeGen/AMDGPU/fold-fmul-to-neg-abs.ll index 6330b28d21323..7bf98d8ce88ef 100644 --- a/llvm/test/CodeGen/AMDGPU/fold-fmul-to-neg-abs.ll +++ b/llvm/test/CodeGen/AMDGPU/fold-fmul-to-neg-abs.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck -check-prefix=GCN %s ; GCN-LABEL: {{^}}fold_mul_neg: ; GCN: load_dword [[V:v[0-9]+]] diff --git a/llvm/test/CodeGen/AMDGPU/fold-imm-copy.mir b/llvm/test/CodeGen/AMDGPU/fold-imm-copy.mir index 24f8624d4d8b2..3bceb03469f82 100644 --- a/llvm/test/CodeGen/AMDGPU/fold-imm-copy.mir +++ b/llvm/test/CodeGen/AMDGPU/fold-imm-copy.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -run-pass si-fold-operands -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s +# RUN: llc -mtriple=amdgpu6.00 -run-pass si-fold-operands -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s --- name: fold-imm-copy diff --git a/llvm/test/CodeGen/AMDGPU/fold-immediate-operand-shrink-with-carry.mir b/llvm/test/CodeGen/AMDGPU/fold-immediate-operand-shrink-with-carry.mir index 8e096cca089aa..25140fe5aab5e 100644 --- a/llvm/test/CodeGen/AMDGPU/fold-immediate-operand-shrink-with-carry.mir +++ b/llvm/test/CodeGen/AMDGPU/fold-immediate-operand-shrink-with-carry.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -verify-machineinstrs -run-pass si-fold-operands,dead-mi-elimination %s -o - | FileCheck -check-prefix=GCN %s +# RUN: llc -mtriple=amdgpu7.00-amd-amdhsa -verify-machineinstrs -run-pass si-fold-operands,dead-mi-elimination %s -o - | FileCheck -check-prefix=GCN %s --- diff --git a/llvm/test/CodeGen/AMDGPU/fold-immediate-operand-shrink.mir b/llvm/test/CodeGen/AMDGPU/fold-immediate-operand-shrink.mir index c2e91f8013ed2..ffd683f1811b9 100644 --- a/llvm/test/CodeGen/AMDGPU/fold-immediate-operand-shrink.mir +++ b/llvm/test/CodeGen/AMDGPU/fold-immediate-operand-shrink.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -verify-machineinstrs -run-pass si-fold-operands,dead-mi-elimination %s -o - | FileCheck -check-prefix=GCN %s +# RUN: llc -mtriple=amdgpu7.00-amd-amdhsa -verify-machineinstrs -run-pass si-fold-operands,dead-mi-elimination %s -o - | FileCheck -check-prefix=GCN %s --- diff --git a/llvm/test/CodeGen/AMDGPU/fold-immediate-output-mods.mir b/llvm/test/CodeGen/AMDGPU/fold-immediate-output-mods.mir index b74fd11ce2479..60de197abbe1e 100644 --- a/llvm/test/CodeGen/AMDGPU/fold-immediate-output-mods.mir +++ b/llvm/test/CodeGen/AMDGPU/fold-immediate-output-mods.mir @@ -1,5 +1,5 @@ -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -run-pass peephole-opt -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -passes peephole-opt -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s +# RUN: llc -mtriple=amdgpu6.00 -run-pass peephole-opt -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s +# RUN: llc -mtriple=amdgpu6.00 -passes peephole-opt -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s ... # GCN-LABEL: name: no_fold_imm_madak_mac_clamp_f32 # GCN: %23:vgpr_32 = V_MOV_B32_e32 1090519040, implicit $exec diff --git a/llvm/test/CodeGen/AMDGPU/fold-implicit-operand.mir b/llvm/test/CodeGen/AMDGPU/fold-implicit-operand.mir index a954e8772aff3..9bc0a06666383 100644 --- a/llvm/test/CodeGen/AMDGPU/fold-implicit-operand.mir +++ b/llvm/test/CodeGen/AMDGPU/fold-implicit-operand.mir @@ -1,4 +1,4 @@ -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -run-pass si-fold-operands -verify-machineinstrs -o - %s | FileCheck %s +# RUN: llc -mtriple=amdgpu6.00 -run-pass si-fold-operands -verify-machineinstrs -o - %s | FileCheck %s --- # Make sure there is no crash when trying to fold an immediate into an # implicit use diff --git a/llvm/test/CodeGen/AMDGPU/fold-over-exec.mir b/llvm/test/CodeGen/AMDGPU/fold-over-exec.mir index e0fa35e994da4..60680e9b232d2 100644 --- a/llvm/test/CodeGen/AMDGPU/fold-over-exec.mir +++ b/llvm/test/CodeGen/AMDGPU/fold-over-exec.mir @@ -1,4 +1,4 @@ -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -verify-machineinstrs -run-pass si-fold-operands %s -o - | FileCheck %s +# RUN: llc -mtriple=amdgpu6.00 -verify-machineinstrs -run-pass si-fold-operands %s -o - | FileCheck %s # CHECK-LABEL: bb.2: # CHECK: %I_out diff --git a/llvm/test/CodeGen/AMDGPU/fold-readlane.mir b/llvm/test/CodeGen/AMDGPU/fold-readlane.mir index d6452b8d11d3f..7caa7a4ef9db6 100644 --- a/llvm/test/CodeGen/AMDGPU/fold-readlane.mir +++ b/llvm/test/CodeGen/AMDGPU/fold-readlane.mir @@ -1,4 +1,4 @@ -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -run-pass si-fold-operands -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s +# RUN: llc -mtriple=amdgpu6.00 -run-pass si-fold-operands -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s # GCN-LABEL: name: fold-imm-readfirstlane{{$}} # GCN: %1:sreg_32_xm0 = S_MOV_B32 123 diff --git a/llvm/test/CodeGen/AMDGPU/force-alwaysinline-lds-global-address-codegen.ll b/llvm/test/CodeGen/AMDGPU/force-alwaysinline-lds-global-address-codegen.ll index 87afa6b8130d8..93878053755f9 100644 --- a/llvm/test/CodeGen/AMDGPU/force-alwaysinline-lds-global-address-codegen.ll +++ b/llvm/test/CodeGen/AMDGPU/force-alwaysinline-lds-global-address-codegen.ll @@ -1,6 +1,6 @@ -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -amdgpu-function-calls -amdgpu-stress-function-calls -amdgpu-enable-lower-module-lds=false < %s | FileCheck -check-prefix=GCN %s -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -amdgpu-stress-function-calls -amdgpu-enable-lower-module-lds=false < %s | FileCheck -check-prefix=GCN %s -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -amdgpu-enable-lower-module-lds=false < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu7.00-amd-amdhsa -amdgpu-function-calls -amdgpu-stress-function-calls -amdgpu-enable-lower-module-lds=false < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu7.00-amd-amdhsa -amdgpu-stress-function-calls -amdgpu-enable-lower-module-lds=false < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu7.00-amd-amdhsa -amdgpu-enable-lower-module-lds=false < %s | FileCheck -check-prefix=GCN %s @lds0 = addrspace(3) global i32 poison, align 4 diff --git a/llvm/test/CodeGen/AMDGPU/fp-to-int-to-fp.ll b/llvm/test/CodeGen/AMDGPU/fp-to-int-to-fp.ll index 187a6f4c74fe9..743c9f25c2f2e 100644 --- a/llvm/test/CodeGen/AMDGPU/fp-to-int-to-fp.ll +++ b/llvm/test/CodeGen/AMDGPU/fp-to-int-to-fp.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck %s +; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck %s ; Test folding of float->int->float roundtrips into float-only operations. diff --git a/llvm/test/CodeGen/AMDGPU/frame-lowering-entry-all-sgpr-used.mir b/llvm/test/CodeGen/AMDGPU/frame-lowering-entry-all-sgpr-used.mir index cbf6f7850e60e..0cd7b6d37fe2f 100644 --- a/llvm/test/CodeGen/AMDGPU/frame-lowering-entry-all-sgpr-used.mir +++ b/llvm/test/CodeGen/AMDGPU/frame-lowering-entry-all-sgpr-used.mir @@ -1,4 +1,4 @@ -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -verify-machineinstrs -run-pass=prolog-epilog %s -o - | FileCheck %s +# RUN: llc -mtriple=amdgpu7.00-amd-amdhsa -verify-machineinstrs -run-pass=prolog-epilog %s -o - | FileCheck %s # CHECK-LABEL: all_sgpr_used # CHECK: V_CMP_LT_U32_e64 diff --git a/llvm/test/CodeGen/AMDGPU/freeze-other-uses-issue-198094.ll b/llvm/test/CodeGen/AMDGPU/freeze-other-uses-issue-198094.ll index c3747d31cb460..4c98ac4536fcb 100644 --- a/llvm/test/CodeGen/AMDGPU/freeze-other-uses-issue-198094.ll +++ b/llvm/test/CodeGen/AMDGPU/freeze-other-uses-issue-198094.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck %s +; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck %s define void @repro(<6 x i32> %a, i32 %i) { ; CHECK-LABEL: repro: diff --git a/llvm/test/CodeGen/AMDGPU/global-alias.ll b/llvm/test/CodeGen/AMDGPU/global-alias.ll index 51e9132cd07a9..e200a9aba7070 100644 --- a/llvm/test/CodeGen/AMDGPU/global-alias.ll +++ b/llvm/test/CodeGen/AMDGPU/global-alias.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 %s -o - | FileCheck %s +; RUN: llc -mtriple=amdgpu6.00 %s -o - | FileCheck %s @foo_a = alias void (ptr), ptr @foo @bar_a = alias void (ptr), ptr @foo_a diff --git a/llvm/test/CodeGen/AMDGPU/hoist-cond.ll b/llvm/test/CodeGen/AMDGPU/hoist-cond.ll index 38de9914c7d50..6615a5beb9d66 100644 --- a/llvm/test/CodeGen/AMDGPU/hoist-cond.ll +++ b/llvm/test/CodeGen/AMDGPU/hoist-cond.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 -disable-block-placement < %s | FileCheck %s +; RUN: llc -mtriple=amdgpu6.00 -disable-block-placement < %s | FileCheck %s ; Check that invariant compare is hoisted out of the loop. ; At the same time condition shall not be serialized into a VGPR and deserialized later diff --git a/llvm/test/CodeGen/AMDGPU/hsa-metadata-deduced-arg-attr.ll b/llvm/test/CodeGen/AMDGPU/hsa-metadata-deduced-arg-attr.ll index d8a7fb9ec0c0f..e73ece65b5532 100644 --- a/llvm/test/CodeGen/AMDGPU/hsa-metadata-deduced-arg-attr.ll +++ b/llvm/test/CodeGen/AMDGPU/hsa-metadata-deduced-arg-attr.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck %s +; RUN: llc -mtriple=amdgpu7.00-amd-amdhsa -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck %s ; CHECK: amdhsa.kernels: ; CHECK-NEXT: - .args: diff --git a/llvm/test/CodeGen/AMDGPU/hsa-metadata-invalid-ocl-version-1.ll b/llvm/test/CodeGen/AMDGPU/hsa-metadata-invalid-ocl-version-1.ll index 584488b9196f9..1ac7e24582f99 100644 --- a/llvm/test/CodeGen/AMDGPU/hsa-metadata-invalid-ocl-version-1.ll +++ b/llvm/test/CodeGen/AMDGPU/hsa-metadata-invalid-ocl-version-1.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck %s +; RUN: llc -mtriple=amdgpu7.00-amd-amdhsa -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck %s ; Make sure llc does not crash for invalid opencl version metadata. diff --git a/llvm/test/CodeGen/AMDGPU/hsa-metadata-invalid-ocl-version-3.ll b/llvm/test/CodeGen/AMDGPU/hsa-metadata-invalid-ocl-version-3.ll index e2cf6b083d0fc..fbbc83762e064 100644 --- a/llvm/test/CodeGen/AMDGPU/hsa-metadata-invalid-ocl-version-3.ll +++ b/llvm/test/CodeGen/AMDGPU/hsa-metadata-invalid-ocl-version-3.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck %s +; RUN: llc -mtriple=amdgpu7.00-amd-amdhsa -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck %s ; Make sure llc does not crash for invalid opencl version metadata. diff --git a/llvm/test/CodeGen/AMDGPU/huge-number-operand-folds.mir b/llvm/test/CodeGen/AMDGPU/huge-number-operand-folds.mir index a25f897085567..48b438d6e10e2 100644 --- a/llvm/test/CodeGen/AMDGPU/huge-number-operand-folds.mir +++ b/llvm/test/CodeGen/AMDGPU/huge-number-operand-folds.mir @@ -1,4 +1,4 @@ -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -verify-machineinstrs -run-pass=si-fold-operands %s -o - | FileCheck -check-prefix=GCN %s +# RUN: llc -mtriple=amdgpu7.00-amd-amdhsa -verify-machineinstrs -run-pass=si-fold-operands %s -o - | FileCheck -check-prefix=GCN %s # We were storing fold candidate uses in an unsigned char, which this exceeds. # The use operand overflows and the expected register operand hits the immediate 0. diff --git a/llvm/test/CodeGen/AMDGPU/i1-copies-rpo.mir b/llvm/test/CodeGen/AMDGPU/i1-copies-rpo.mir index 3f2594b6842f7..a6091103b2f1c 100644 --- a/llvm/test/CodeGen/AMDGPU/i1-copies-rpo.mir +++ b/llvm/test/CodeGen/AMDGPU/i1-copies-rpo.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -verify-machineinstrs -run-pass=si-i1-copies -o - %s | FileCheck %s +# RUN: llc -mtriple=amdgpu7.00-amd-amdhsa -verify-machineinstrs -run-pass=si-i1-copies -o - %s | FileCheck %s # The strange block ordering visits the use before the def. --- diff --git a/llvm/test/CodeGen/AMDGPU/i1-copy-from-loop.ll b/llvm/test/CodeGen/AMDGPU/i1-copy-from-loop.ll index 8a3d6d997b0b7..0420f8394c8dd 100644 --- a/llvm/test/CodeGen/AMDGPU/i1-copy-from-loop.ll +++ b/llvm/test/CodeGen/AMDGPU/i1-copy-from-loop.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=amdgcn-- -mcpu=gfx600 < %s | FileCheck -check-prefix=SI %s +; RUN: llc -mtriple=amdgpu6.00-- < %s | FileCheck -check-prefix=SI %s define amdgpu_ps void @i1_copy_from_loop(ptr addrspace(8) inreg %rsrc, i32 %tid) { ; SI-LABEL: i1_copy_from_loop: diff --git a/llvm/test/CodeGen/AMDGPU/i1-copy-phi-uniform-branch.ll b/llvm/test/CodeGen/AMDGPU/i1-copy-phi-uniform-branch.ll index 62190dfc380b5..4a792d64496d7 100644 --- a/llvm/test/CodeGen/AMDGPU/i1-copy-phi-uniform-branch.ll +++ b/llvm/test/CodeGen/AMDGPU/i1-copy-phi-uniform-branch.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck -check-prefix=GCN %s ; GCN-LABEL: {{^}}test_dont_clobber_scc: diff --git a/llvm/test/CodeGen/AMDGPU/implicit-def-muse.ll b/llvm/test/CodeGen/AMDGPU/implicit-def-muse.ll index a510c8b48982b..bd56a25e33e4e 100644 --- a/llvm/test/CodeGen/AMDGPU/implicit-def-muse.ll +++ b/llvm/test/CodeGen/AMDGPU/implicit-def-muse.ll @@ -1,5 +1,5 @@ -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 -stop-after=amdgpu-isel -o - %s | FileCheck %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 -stop-after=amdgpu-isel -enable-new-pm -o - %s | FileCheck %s +; RUN: llc -mtriple=amdgpu6.00 -stop-after=amdgpu-isel -o - %s | FileCheck %s +; RUN: llc -mtriple=amdgpu6.00 -stop-after=amdgpu-isel -enable-new-pm -o - %s | FileCheck %s ; CHECK-LABEL: vcopy_i1_undef ; CHECK: [[IMPDEF0:%[0-9]+]]:vreg_1 = IMPLICIT_DEF diff --git a/llvm/test/CodeGen/AMDGPU/indirect-call.ll b/llvm/test/CodeGen/AMDGPU/indirect-call.ll index 32387a9fe61ff..1dbc21136362d 100644 --- a/llvm/test/CodeGen/AMDGPU/indirect-call.ll +++ b/llvm/test/CodeGen/AMDGPU/indirect-call.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 < %s | FileCheck -check-prefix=GCN %s -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -global-isel -global-isel-abort=2 < %s | FileCheck -check-prefix=GISEL %s +; RUN: llc -mtriple=amdgpu7.00-amd-amdhsa < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu7.00-amd-amdhsa -global-isel -global-isel-abort=2 < %s | FileCheck -check-prefix=GISEL %s @gv.fptr0 = external hidden unnamed_addr addrspace(4) constant ptr, align 4 @gv.fptr1 = external hidden unnamed_addr addrspace(4) constant ptr, align 4 diff --git a/llvm/test/CodeGen/AMDGPU/insert-waitcnts-exp.mir b/llvm/test/CodeGen/AMDGPU/insert-waitcnts-exp.mir index 49a93afcd471b..4f4ca476197a0 100644 --- a/llvm/test/CodeGen/AMDGPU/insert-waitcnts-exp.mir +++ b/llvm/test/CodeGen/AMDGPU/insert-waitcnts-exp.mir @@ -1,4 +1,4 @@ -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -verify-machineinstrs -run-pass si-insert-waitcnts -o - %s | FileCheck %s +# RUN: llc -mtriple=amdgpu6.00 -verify-machineinstrs -run-pass si-insert-waitcnts -o - %s | FileCheck %s --- | define amdgpu_ps <4 x float> @exp_done_waitcnt(<4 x i32> inreg, <4 x i32> inreg, i32 inreg %w, float %v) #0 { diff --git a/llvm/test/CodeGen/AMDGPU/invalid-addrspacecast.ll b/llvm/test/CodeGen/AMDGPU/invalid-addrspacecast.ll index 3fb8144ab90cc..2bc6f0bcdb711 100644 --- a/llvm/test/CodeGen/AMDGPU/invalid-addrspacecast.ll +++ b/llvm/test/CodeGen/AMDGPU/invalid-addrspacecast.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 -; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 < %s | FileCheck --check-prefixes=CHECK,SDAG %s -; RUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 < %s | FileCheck --check-prefixes=CHECK,GISEL %s +; RUN: llc -global-isel=0 -mtriple=amdgpu7.00-amd-amdhsa < %s | FileCheck --check-prefixes=CHECK,SDAG %s +; RUN: llc -global-isel=1 -mtriple=amdgpu7.00-amd-amdhsa < %s | FileCheck --check-prefixes=CHECK,GISEL %s ; Check illegal casts are codegened as poison, and not an error. diff --git a/llvm/test/CodeGen/AMDGPU/invalid-inline-asm-constraint-crash.ll b/llvm/test/CodeGen/AMDGPU/invalid-inline-asm-constraint-crash.ll index 23a7fb70d8011..87ccad63246c1 100644 --- a/llvm/test/CodeGen/AMDGPU/invalid-inline-asm-constraint-crash.ll +++ b/llvm/test/CodeGen/AMDGPU/invalid-inline-asm-constraint-crash.ll @@ -1,4 +1,4 @@ -; RUN: not llc -mtriple=amdgcn -mcpu=gfx600 < %s 2>&1 | FileCheck -check-prefix=ERR %s +; RUN: not llc -mtriple=amdgpu6.00 < %s 2>&1 | FileCheck -check-prefix=ERR %s ; ERR: error: could not allocate output register for constraint 'q' define void @crash_use_invalid_output_constraint_block(ptr addrspace(1) %arg) { diff --git a/llvm/test/CodeGen/AMDGPU/invariant-load-no-alias-store.ll b/llvm/test/CodeGen/AMDGPU/invariant-load-no-alias-store.ll index 043f1ae3dd323..fa5813c60637d 100644 --- a/llvm/test/CodeGen/AMDGPU/invariant-load-no-alias-store.ll +++ b/llvm/test/CodeGen/AMDGPU/invariant-load-no-alias-store.ll @@ -1,4 +1,4 @@ -; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx600 -amdgpu-load-store-vectorizer=0 < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgpu6.00 -amdgpu-load-store-vectorizer=0 < %s | FileCheck -check-prefix=GCN %s ; GatherAllAliases gives up on trying to analyze cases where the ; pointer may have been loaded from an aliased store, so make sure diff --git a/llvm/test/CodeGen/AMDGPU/invert-br-undef-vcc.mir b/llvm/test/CodeGen/AMDGPU/invert-br-undef-vcc.mir index 6e4679fb5ae26..533ffde5c0caf 100644 --- a/llvm/test/CodeGen/AMDGPU/invert-br-undef-vcc.mir +++ b/llvm/test/CodeGen/AMDGPU/invert-br-undef-vcc.mir @@ -1,4 +1,4 @@ -# RUN: llc -run-pass block-placement -mtriple=amdgcn -mcpu=gfx600 -verify-machineinstrs -o - %s | FileCheck %s +# RUN: llc -run-pass block-placement -mtriple=amdgpu6.00 -verify-machineinstrs -o - %s | FileCheck %s --- | define amdgpu_kernel void @invert_br_undef_vcc(float %cond, ptr addrspace(1) %out) #0 { diff --git a/llvm/test/CodeGen/AMDGPU/ipra-regmask.ll b/llvm/test/CodeGen/AMDGPU/ipra-regmask.ll index 3e429f7308072..dd9a5f53ec630 100644 --- a/llvm/test/CodeGen/AMDGPU/ipra-regmask.ll +++ b/llvm/test/CodeGen/AMDGPU/ipra-regmask.ll @@ -1,9 +1,9 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -enable-ipra -print-regusage -filetype=null 2>&1 < %s | FileCheck %s -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -enable-new-pm=1 -enable-ipra -print-regusage -filetype=null 2>&1 < %s | FileCheck %s +; RUN: llc -mtriple=amdgpu7.00-amd-amdhsa -enable-ipra -print-regusage -filetype=null 2>&1 < %s | FileCheck %s +; RUN: llc -mtriple=amdgpu7.00-amd-amdhsa -enable-new-pm=1 -enable-ipra -print-regusage -filetype=null 2>&1 < %s | FileCheck %s -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -stop-after=prolog-epilog -o - %s \ -; RUN: | llc -x=mir -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -passes="module(require<reg-usage>,function(machine-function(reg-usage-collector)),print<reg-usage>)" -filetype=null 2>&1 \ +; RUN: llc -mtriple=amdgpu7.00-amd-amdhsa -stop-after=prolog-epilog -o - %s \ +; RUN: | llc -x=mir -mtriple=amdgpu7.00-amd-amdhsa -passes="module(require<reg-usage>,function(machine-function(reg-usage-collector)),print<reg-usage>)" -filetype=null 2>&1 \ ; RUN: | FileCheck %s ; Make sure the expected regmask is generated for sub/superregisters. diff --git a/llvm/test/CodeGen/AMDGPU/ipra-return-address-save-restore.ll b/llvm/test/CodeGen/AMDGPU/ipra-return-address-save-restore.ll index 41f19f0b988e1..5d6010e46236a 100644 --- a/llvm/test/CodeGen/AMDGPU/ipra-return-address-save-restore.ll +++ b/llvm/test/CodeGen/AMDGPU/ipra-return-address-save-restore.ll @@ -1,5 +1,5 @@ -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -enable-ipra=1 < %s | FileCheck -check-prefix=GCN %s -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -enable-ipra=0 < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu7.00-amd-amdhsa -enable-ipra=1 < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu7.00-amd-amdhsa -enable-ipra=0 < %s | FileCheck -check-prefix=GCN %s ; This test is to make sure the return address registers, if clobbered in the ; function or the function has calls, are save/restored when IPRA is enabled/disabled. diff --git a/llvm/test/CodeGen/AMDGPU/kernarg-stack-alignment.ll b/llvm/test/CodeGen/AMDGPU/kernarg-stack-alignment.ll index a5b1a3270f7ce..18098ee086e50 100644 --- a/llvm/test/CodeGen/AMDGPU/kernarg-stack-alignment.ll +++ b/llvm/test/CodeGen/AMDGPU/kernarg-stack-alignment.ll @@ -1,4 +1,4 @@ -; RUN: llc -O0 -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck %s +; RUN: llc -O0 -mtriple=amdgpu6.00 < %s | FileCheck %s ; Test that the alignment of kernel arguments does not impact the ; alignment of the stack _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
