llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-backend-amdgpu @llvm/pr-subscribers-llvm-globalisel Author: Matt Arsenault (arsenm) <details> <summary>Changes</summary> Fold the explicit -mcpu subtarget into the amdgpu subarch triple on llc/opt RUN lines (e.g. -mtriple=amdgcn -mcpu=gfx600 -> -mtriple=amdgpu6.00), now that these tests carry an explicit -mcpu following the default-subtarget pinning. Codegen output is unchanged. Co-Authored-By: Claude <noreply@<!-- -->anthropic.com> (Claude-Opus-4.8) --- Patch is 69.20 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/209777.diff 100 Files Affected: - (modified) llvm/test/CodeGen/AMDGPU/kernel_code_t_recurse.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/kill-infinite-loop.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/knownbits-recursion.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/lcssa-optnone.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/lds-alignment.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/lds-m0-init-in-loop.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/lds-size.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/liveness.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/livevars-implicitdef.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll (+3-3) - (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.class.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dispatch.id.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.div.fmas.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.div.scale.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdiv.fast.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.implicit.ptr.buffer.hsa.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.implicit.ptr.buffer.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.lds.kernel.id.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mul.i24.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mul.u24.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rcp.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.legacy.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.getpc.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.barrier.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.unreachable.ll (+4-4) - (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wave.barrier.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/llvm.dbg.value.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/long-branch-reserve-register.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/lower-control-flow-live-variables-update.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/lower-control-flow-live-variables-update.xfail.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/lower-range-metadata-intrinsic-call.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/machinelicm-convergent.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/machinelicm-copy-like-instrs.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/mad24-get-global-id.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/madak-inline-constant.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/madmk.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/mcp-use-before-def.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/mem-builtins.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/memory-legalizer-store-infinite-loop.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/merge-load-store-physreg.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/merge-load-store.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/merge-m0.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/mir-print-dead-csr-fi.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/movrels-bug.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/new-pm-machine-analysis.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/no-hsa-graphics-shaders.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/no-limit-coalesce.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/no-shrink-extloads.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/nullptr-long-address-spaces.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/nullptr.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/omod-nsz-flag.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/opencl-image-metadata.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/opt-sgpr-to-vgpr-copy.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/opt_exec_copy_fold.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/optimize-exec-masking-pre-ra.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/optimize-if-exec-masking.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/optimize-negated-cond-exec-masking.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/optimize-negated-cond.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/partially-dead-super-register-immediate.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/peephole-opt-regseq-removal.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/pei-reg-scavenger-position.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/preserve-user-waitcnt.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/promote-alloca-stored-pointer-value.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/rcp_iflag.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/read-register-invalid-type-i32.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/read-register-invalid-type-i64.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/reduce-saveexec.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/reduce-store-width-alignment.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/regcoal-subrange-join-seg.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/regcoal-subrange-join.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/regcoalesce-cannot-join-failures.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/regcoalesce-dbg.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/regcoalesce-keep-valid-lanes-implicit-def-bug39602.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/regcoalesce-prune.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/regcoalescer-resolve-lane-conflict-by-subranges.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/register-count-comments.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/remaining-virtual-register-operands.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/remat-dead-subreg.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/rename-independent-subregs-mac-operands.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/rename-independent-subregs.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/rewrite-partial-reg-uses-dbg.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/rewrite-partial-reg-uses-gen.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/rewrite-partial-reg-uses.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/sched.barrier.inverted.mask.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/schedule-global-loads.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/schedule-physregdeps.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/schedule-regpressure.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/select-constant-cttz.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/select-opt.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/set-wave-priority.ll (+4-4) - (modified) llvm/test/CodeGen/AMDGPU/setcc-select-hi32mask.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/setcc-select.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/setcc-sext.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/setcc.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/sgpr-spill-wrong-stack-id.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/sgpr-to-vreg1-copy.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/sgprcopies.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/shrink-vop3-carry-out.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/si-fix-sgpr-copies.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/si-i1-copies.mir (+1-1) ``````````diff diff --git a/llvm/test/CodeGen/AMDGPU/kernel_code_t_recurse.ll b/llvm/test/CodeGen/AMDGPU/kernel_code_t_recurse.ll index 39115568c224f..8c27aff378f91 100644 --- a/llvm/test/CodeGen/AMDGPU/kernel_code_t_recurse.ll +++ b/llvm/test/CodeGen/AMDGPU/kernel_code_t_recurse.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx600 < %s | FileCheck %s +; RUN: llc -mtriple=amdgpu6.00-mesa-mesa3d < %s | FileCheck %s ; CHECK-LABEL: non_kernel_recursion: define void @non_kernel_recursion(i32 %val) #2 { diff --git a/llvm/test/CodeGen/AMDGPU/kill-infinite-loop.ll b/llvm/test/CodeGen/AMDGPU/kill-infinite-loop.ll index 77c14cfcc732a..d2603b76c5ee7 100644 --- a/llvm/test/CodeGen/AMDGPU/kill-infinite-loop.ll +++ b/llvm/test/CodeGen/AMDGPU/kill-infinite-loop.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -enable-var-scope %s +; RUN: llc -mtriple=amdgpu6.00 -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -enable-var-scope %s ; Although it's modeled without any control flow in order to get better code ; out of the structurizer, @llvm.amdgcn.kill actually ends the thread that calls diff --git a/llvm/test/CodeGen/AMDGPU/knownbits-recursion.ll b/llvm/test/CodeGen/AMDGPU/knownbits-recursion.ll index ca1346171cb57..ceaa18de60354 100644 --- a/llvm/test/CodeGen/AMDGPU/knownbits-recursion.ll +++ b/llvm/test/CodeGen/AMDGPU/knownbits-recursion.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck -check-prefix=GCN %s ; Check we can compile this test without infinite loop in the ; DAG.computeKnownBits() due to missing (Depth + 1) argument in diff --git a/llvm/test/CodeGen/AMDGPU/lcssa-optnone.ll b/llvm/test/CodeGen/AMDGPU/lcssa-optnone.ll index a49e5feb59f20..0804da880fb7f 100644 --- a/llvm/test/CodeGen/AMDGPU/lcssa-optnone.ll +++ b/llvm/test/CodeGen/AMDGPU/lcssa-optnone.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 -O0 -o - %s | FileCheck %s +; RUN: llc -mtriple=amdgpu6.00 -O0 -o - %s | FileCheck %s ; CHECK-LABEL: non_uniform_loop ; CHECK: s_endpgm diff --git a/llvm/test/CodeGen/AMDGPU/lds-alignment.ll b/llvm/test/CodeGen/AMDGPU/lds-alignment.ll index 4d5e2709dc6eb..20a189c5f91f2 100644 --- a/llvm/test/CodeGen/AMDGPU/lds-alignment.ll +++ b/llvm/test/CodeGen/AMDGPU/lds-alignment.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn-unknown-amdhsa -mcpu=gfx700 < %s | FileCheck -check-prefix=HSA %s +; RUN: llc -mtriple=amdgpu7.00-unknown-amdhsa < %s | FileCheck -check-prefix=HSA %s @lds.align16.0 = internal unnamed_addr addrspace(3) global [38 x i8] poison, align 16 @lds.align16.1 = internal unnamed_addr addrspace(3) global [38 x i8] poison, align 16 diff --git a/llvm/test/CodeGen/AMDGPU/lds-m0-init-in-loop.ll b/llvm/test/CodeGen/AMDGPU/lds-m0-init-in-loop.ll index a212ebacf8c2e..3b66ef5d30d68 100644 --- a/llvm/test/CodeGen/AMDGPU/lds-m0-init-in-loop.ll +++ b/llvm/test/CodeGen/AMDGPU/lds-m0-init-in-loop.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck -check-prefix=GCN %s ; Make sure that m0 is not reinitialized in the loop. diff --git a/llvm/test/CodeGen/AMDGPU/lds-size.ll b/llvm/test/CodeGen/AMDGPU/lds-size.ll index a2471c4c45b7e..bee26bac57ca7 100644 --- a/llvm/test/CodeGen/AMDGPU/lds-size.ll +++ b/llvm/test/CodeGen/AMDGPU/lds-size.ll @@ -1,5 +1,5 @@ -; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 < %s | FileCheck -check-prefix=ALL -check-prefix=HSA %s -; RUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 < %s | FileCheck -check-prefix=ALL -check-prefix=HSA %s +; RUN: llc -global-isel=0 -mtriple=amdgpu7.00-amd-amdhsa < %s | FileCheck -check-prefix=ALL -check-prefix=HSA %s +; RUN: llc -global-isel=1 -mtriple=amdgpu7.00-amd-amdhsa < %s | FileCheck -check-prefix=ALL -check-prefix=HSA %s ; RUN: llc -mtriple=r600 -mcpu=redwood < %s | FileCheck -check-prefix=ALL -check-prefix=EG %s ; This test makes sure we do not double count global values when they are diff --git a/llvm/test/CodeGen/AMDGPU/liveness.mir b/llvm/test/CodeGen/AMDGPU/liveness.mir index a5bf63f555d85..18c6898e33692 100644 --- a/llvm/test/CodeGen/AMDGPU/liveness.mir +++ b/llvm/test/CodeGen/AMDGPU/liveness.mir @@ -1,5 +1,5 @@ -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -run-pass liveintervals -verify-machineinstrs -filetype=null -debug-only=regalloc %s 2>&1 | FileCheck %s -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -passes='print<live-intervals>' -filetype=null -debug-only=regalloc %s 2>&1 | FileCheck %s +# RUN: llc -mtriple=amdgpu6.00 -run-pass liveintervals -verify-machineinstrs -filetype=null -debug-only=regalloc %s 2>&1 | FileCheck %s +# RUN: llc -mtriple=amdgpu6.00 -passes='print<live-intervals>' -filetype=null -debug-only=regalloc %s 2>&1 | FileCheck %s # REQUIRES: asserts # We currently maintain a main liveness range which operates like a superset of # all subregister liveranges. We may need to create additional SSA values at diff --git a/llvm/test/CodeGen/AMDGPU/livevars-implicitdef.mir b/llvm/test/CodeGen/AMDGPU/livevars-implicitdef.mir index ed78b6da798a1..5753f57481c08 100644 --- a/llvm/test/CodeGen/AMDGPU/livevars-implicitdef.mir +++ b/llvm/test/CodeGen/AMDGPU/livevars-implicitdef.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 --run-pass=livevars -o - %s | FileCheck %s +# RUN: llc -mtriple=amdgpu6.00 --run-pass=livevars -o - %s | FileCheck %s --- # Check that super register is defined for an sgpr copy. name: sgpr_copy diff --git a/llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll b/llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll index 2f3bc3f259e89..2ec3cebd36ae5 100644 --- a/llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll +++ b/llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll @@ -1,10 +1,10 @@ -; RUN: llc -enable-new-pm -mtriple=amdgcn--amdhsa -mcpu=gfx700 -O0 -print-pipeline-passes=tree < %s 2>&1 \ +; RUN: llc -enable-new-pm -mtriple=amdgpu7.00--amdhsa -O0 -print-pipeline-passes=tree < %s 2>&1 \ ; RUN: | FileCheck -check-prefix=GCN-O0 %s -; RUN: llc -enable-new-pm -mtriple=amdgcn--amdhsa -mcpu=gfx700 -print-pipeline-passes=tree < %s 2>&1 \ +; RUN: llc -enable-new-pm -mtriple=amdgpu7.00--amdhsa -print-pipeline-passes=tree < %s 2>&1 \ ; RUN: | FileCheck -check-prefix=GCN-O2 %s -; RUN: llc -O3 -enable-new-pm -mtriple=amdgcn--amdhsa -mcpu=gfx700 -print-pipeline-passes=tree < %s 2>&1 \ +; RUN: llc -O3 -enable-new-pm -mtriple=amdgpu7.00--amdhsa -print-pipeline-passes=tree < %s 2>&1 \ ; RUN: | FileCheck -check-prefix=GCN-O3 %s ; GCN-O0: require<MachineModuleAnalysis> diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.class.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.class.ll index 9f91d38dd0ead..b22cc75294e5f 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.class.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.class.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 -; RUN: llc -global-isel=0 -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -enable-var-scope -check-prefixes=SI,SI-SDAG %s -; RUN: llc -global-isel=1 -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -enable-var-scope -check-prefixes=SI,SI-GISEL %s +; RUN: llc -global-isel=0 -amdgpu-scalarize-global-loads=false -mtriple=amdgpu6.00 < %s | FileCheck -enable-var-scope -check-prefixes=SI,SI-SDAG %s +; RUN: llc -global-isel=1 -amdgpu-scalarize-global-loads=false -mtriple=amdgpu6.00 < %s | FileCheck -enable-var-scope -check-prefixes=SI,SI-GISEL %s declare i1 @llvm.amdgcn.class.f32(float, i32) #1 declare i1 @llvm.amdgcn.class.f64(double, i32) #1 diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dispatch.id.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dispatch.id.ll index 5e594c5054bc9..4914d0dde51d1 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dispatch.id.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dispatch.id.ll @@ -1,5 +1,5 @@ -; RUN: llc -global-isel=0 -mtriple=amdgcn--amdhsa -mcpu=gfx700 < %s | FileCheck -check-prefix=GCN %s -; RUN: llc -global-isel -mtriple=amdgcn--amdhsa -mcpu=gfx700 < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -global-isel=0 -mtriple=amdgpu7.00--amdhsa < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -global-isel -mtriple=amdgpu7.00--amdhsa < %s | FileCheck -check-prefix=GCN %s declare i64 @llvm.amdgcn.dispatch.id() #1 diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.div.fmas.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.div.fmas.ll index 272b0a2a84938..f4a1817113457 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.div.fmas.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.div.fmas.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 -; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI %s -; XUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI %s +; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgpu6.00 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI %s +; XUN: llc -mtriple=amdgpu8.02 -mattr=-flat-for-global < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI %s ; FIXME: Enable for VI. diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.div.scale.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.div.scale.ll index a67ee629f9053..e9151b344b7e4 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.div.scale.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.div.scale.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -enable-var-scope -check-prefix=SI %s +; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck -enable-var-scope -check-prefix=SI %s declare i32 @llvm.amdgcn.workitem.id.x() #1 declare { float, i1 } @llvm.amdgcn.div.scale.f32(float, float, i1) #1 diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdiv.fast.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdiv.fast.ll index 67592219598f6..462ada162a004 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdiv.fast.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdiv.fast.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck %s +; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck %s declare float @llvm.amdgcn.fdiv.fast(float, float) #0 diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.implicit.ptr.buffer.hsa.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.implicit.ptr.buffer.hsa.ll index 6138701dae22d..3ef45aefd8910 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.implicit.ptr.buffer.hsa.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.implicit.ptr.buffer.hsa.ll @@ -1,4 +1,4 @@ -; RUN: not llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 < %s 2>&1 | FileCheck -check-prefix=ERROR %s +; RUN: not llc -mtriple=amdgpu7.00-amd-amdhsa < %s 2>&1 | FileCheck -check-prefix=ERROR %s ; ERROR: in function test_kernel{{.*}}: non-hsa intrinsic with hsa target define amdgpu_kernel void @test_kernel(ptr addrspace(1) %out) #1 { diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.implicit.ptr.buffer.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.implicit.ptr.buffer.ll index 2512fb2774565..ea627732e703f 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.implicit.ptr.buffer.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.implicit.ptr.buffer.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx600 < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu6.00-mesa-mesa3d < %s | FileCheck -check-prefix=GCN %s ; FIXME: Requires stack object to not assert ; GCN-LABEL: {{^}}test_ps: diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.lds.kernel.id.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.lds.kernel.id.ll index c20a44822aee4..7dd71951713bf 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.lds.kernel.id.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.lds.kernel.id.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx700 < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu7.00--amdhsa < %s | FileCheck -check-prefix=GCN %s declare i32 @llvm.amdgcn.lds.kernel.id() declare i32 @llvm.amdgcn.workgroup.id.x() diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mul.i24.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mul.i24.ll index eee0592dc2e2d..17d4293e7e1bb 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mul.i24.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mul.i24.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck -check-prefix=GCN %s ; GCN-LABEL: {{^}}test_mul_i24: ; GCN: v_mul_i32_i24 diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mul.u24.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mul.u24.ll index 99f5537db2d9b..5c15734b8b31b 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mul.u24.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mul.u24.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck -check-prefix=GCN %s ; GCN-LABEL: {{^}}test_mul_u24: ; GCN: v_mul_u32_u24 diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rcp.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rcp.ll index f1fbfebba148c..ec50350ed599b 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rcp.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rcp.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -enable-var-scope -check-prefix=SI -check-prefix=FUNC %s +; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck -enable-var-scope -check-prefix=SI -check-prefix=FUNC %s declare float @llvm.amdgcn.rcp.f32(float) #0 declare double @llvm.amdgcn.rcp.f64(double) #0 diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.legacy.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.legacy.ll index c8dfdabed44ff..cf04a66b6229d 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.legacy.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.legacy.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s +; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s declare float @llvm.amdgcn.rsq.legacy(float) #0 diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.getpc.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.getpc.ll index 98c3fa9b12b6f..c47334e15911d 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.getpc.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.getpc.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck -check-prefix=GCN %s declare i64 @llvm.amdgcn.s.getpc() #0 diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.barrier.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.barrier.ll index 4a2737535defe..88396740a05e8 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.barrier.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.barrier.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -check-prefix=GCN %s -; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -global-isel=0 -mtriple=amdgpu6.00 < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -global-isel=1 -mtriple=amdgpu6.00 < %s | FileCheck -check-prefix=GCN %s define amdgpu_kernel void @test_sched_barrier() #0 { ; GCN-LABEL: test_sched_barrier: diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.unreachable.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.unreachable.ll index e24596cb89cd9..19b1b71ede48f 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.unreachable.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.unreachable.ll @@ -1,7 +1,7 @@ -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 %s -filetype=obj -filetype=null -; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx600 %s -filetype=obj -filetype=null -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck %s -; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck %s +; RUN: llc -mtriple=amdgpu6.00 %s -filetype=obj -filetype=null +; RUN: llc -global-isel=1 -mtriple=amdgpu6.00 %s -filetype=obj -filetype=null +; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck %s +; RUN: llc -global-isel=1 -mtriple=amdgpu6.00 < %s | FileCheck %s define amdgpu_kernel void @f() { ; CHECK: ; divergent unreachable call void @llvm.amdgcn.unreachable() diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wave.barrier.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wave.barrier.ll index 6baf319dc0fbb..bcefb161be44d 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wave.barrier.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wave.barrier.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck -check-prefix=GCN %s ; GCN-LABEL: {{^}}test_wave_barrier: ; GCN-DAG: ; wave barrier diff --git a/llvm/test/CodeGen/AMDGPU/llvm.dbg.value.ll b/llvm/test/CodeGen/AMDGPU/llvm.dbg.value.ll index c90dceeba0611..c3aafd84bd54c 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.dbg.value.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.dbg.value.ll @@ -1,5 +1,5 @@ -; RUN: llc -O0 -mtriple=amdgcn-unknown-amdhsa -mcpu=gfx700 < %s | FileCheck -check-prefixes=GCN,NOOPT %s -; RUN: llc -mtriple=amdgcn-unknown-amdhsa -mcpu=gfx700 < %s | FileCheck -check-prefixes=GCN,OPT %s +; RUN: llc -O0 -mtriple=amdgpu7.00-unknown-amdhsa < %s | FileCheck -check-prefixes=GCN,NOOPT %s +; RUN: llc -mtriple=amdgpu7.00-unknown-amdhsa < %s | FileCheck -check-prefixes=GCN,OPT %s ; GCN-LABEL: {{^}}test_debug_value: diff --git a/llvm/test/CodeGen/AMDGPU/long-branch-reserve-register.ll b/llvm/test/CodeGen/AMDGPU/long-branch-reserve-register.ll index 343efc07cd089..8c7dcd9253e8a 100644 --- a/llvm/test/CodeGen/AMDGPU/long-branch-reserve-register.ll +++ b/llvm/test/CodeGen/AMDGPU/long-branch-reserve-register.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3 -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 -amdgpu-s-branch-bits=4 -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -enable-var-scope -check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu6.00 -amdgpu-s-branch-bits=4 -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -enable-var-scope -check-prefix=GCN %s ; OBJ: Relocations [ ; OBJ-NEXT: ] diff --git a/llvm/test/CodeGen/AMDGPU/lower-control-flow-live-variables-update.mir b/llvm/test/CodeGen/AMDGPU/lower-control-flow-live-variables-update.mir index 54b969bcf252d..32746ef5fce9e 100644 --- a/llvm/test/CodeGen/AMDGPU/lower-control-flow-live-variables-update.mir +++ b/llvm/test/CodeGen/AMDGPU/lower-control-flow-live-variables-update.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -start-before=livevars -stop-after=twoaddressinstruction -verify-machineinstrs -o - %s | FileCheck %s +# RUN: llc -mtriple=amdgpu7.00-amd-amdhsa -start-before=livevars -stop-after=twoaddressinstruction -verify-machineinstrs -o - %s | FileCheck %s # FIXME: update_mir_test_checks tries to incorrectly re-use a variable # name used for a copy, so some of the check variable names were diff --git a/llvm/test/CodeGen/AMDGPU/lower-control-flow-live-variables-update.xfail.mir b/llvm/test/CodeGen/AMDGPU/lower-control-flow-live-variables-update.xfail.mir index c86596ca82e8b..7a6fb07b598bb 100644 --- a/llvm/test/CodeGen/AMDGPU/lower-control-flow-live-variables-update.xfail.mir +++ b/llvm/test/CodeGen/AMDGPU/lower-control-flow-live-variables-update.xfail.mir @@ -1,4 +1,4 @@ -# RUN: not --crash llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -start-before=livevars -stop-after=twoaddressinstruction -verify-machineinstrs -o - %s 2>&1 | FileCheck %s +# RUN: not --crash llc -mtriple=amdgpu7.00-amd-amdhsa -start-before=livevars -stop-after=twoaddressinstruction -verify-machineinstrs -o - %s 2>&1 | FileCheck %s ... [truncated] `````````` </details> https://github.com/llvm/llvm-project/pull/209777 _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
