https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/209817
>From 5587d53073674251309f505c79749a063cb54ee0 Mon Sep 17 00:00:00 2001 From: Matt Arsenault <[email protected]> Date: Fri, 26 Jun 2026 16:45:27 +0200 Subject: [PATCH] AMDGPU: Migrate more tests to using subarch triple commands (57) Mostly mechanical updates with some light cleanups manually applied. Co-authored-by: Claude (Opus 4.8) <[email protected]> --- .../irtranslator-amdgpu_kernel-system-sgprs.ll | 2 +- llvm/test/CodeGen/AMDGPU/GlobalISel/shufflevector.ll | 2 +- llvm/test/CodeGen/AMDGPU/always-uniform.ll | 2 +- llvm/test/CodeGen/AMDGPU/amdgpu-mul24-knownbits.ll | 4 ++-- .../AMDGPU/amdgpu-simplify-libcall-pow-codegen.ll | 2 +- .../AMDGPU/amdgpu-simplify-libcall-rootn-codegen.ll | 2 +- .../AMDGPU/attributor-flatscratchinit-globalisel.ll | 2 +- llvm/test/CodeGen/AMDGPU/call-encoding.ll | 10 +++++----- .../AMDGPU/global-atomics-fp-wrong-subtarget.ll | 2 +- llvm/test/CodeGen/AMDGPU/global_smrd.ll | 2 +- llvm/test/CodeGen/AMDGPU/inline-calls.ll | 4 ++-- llvm/test/CodeGen/AMDGPU/inlineasm-sgmask.ll | 2 +- .../AMDGPU/insert-subvector-unused-scratch.ll | 2 +- .../test/CodeGen/AMDGPU/madmk-madak-encoding-size.ll | 2 +- llvm/test/CodeGen/AMDGPU/mesa_regression.ll | 2 +- .../CodeGen/AMDGPU/not-scalarize-volatile-load.ll | 2 +- .../optimize-exec-mask-pre-ra-def-after-use.mir | 2 +- llvm/test/CodeGen/AMDGPU/permlane-op-sel.ll | 2 +- llvm/test/CodeGen/AMDGPU/permlane16_var-op-sel.ll | 2 +- .../CodeGen/AMDGPU/promote-alloca-shufflevector.ll | 2 +- .../CodeGen/AMDGPU/promote-constOffset-to-imm.ll | 12 ++++++------ .../CodeGen/AMDGPU/sgpr-spills-split-regalloc.ll | 2 +- .../AMDGPU/spill_more_than_wavesize_csr_sgprs.ll | 2 +- .../unpack-non-coissue-insts-post-ra-scheduler.mir | 6 +++--- .../CodeGen/AMDGPU/vgpr-large-tuple-alloc-error.ll | 8 ++++---- 25 files changed, 41 insertions(+), 41 deletions(-) diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_kernel-system-sgprs.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_kernel-system-sgprs.ll index eb7227c489b95..717f6a10cf691 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_kernel-system-sgprs.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_kernel-system-sgprs.ll @@ -1,4 +1,4 @@ -; RUN: opt -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -passes=amdgpu-attributor < %s | llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -amdgpu-ir-lower-kernel-arguments=0 -stop-after=irtranslator -o - | FileCheck -check-prefix=HSA %s +; RUN: opt -mtriple=amdgpu8.03-amd-amdhsa -passes=amdgpu-attributor < %s | llc -global-isel -mtriple=amdgpu8.03-amd-amdhsa -amdgpu-ir-lower-kernel-arguments=0 -stop-after=irtranslator -o - | FileCheck -check-prefix=HSA %s ; HSA-LABEL: name: default_kernel ; HSA: liveins: diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/shufflevector.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/shufflevector.ll index 29309b4242b8a..ae717254140f9 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/shufflevector.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/shufflevector.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 < %s | FileCheck -check-prefix=GFX942 %s +; RUN: llc -global-isel -mtriple=amdgpu9.42-amd-amdhsa < %s | FileCheck -check-prefix=GFX942 %s define void @shuffle_to_extract(ptr addrspace(3) %in, ptr addrspace(3) %out) { ; GFX942-LABEL: shuffle_to_extract: diff --git a/llvm/test/CodeGen/AMDGPU/always-uniform.ll b/llvm/test/CodeGen/AMDGPU/always-uniform.ll index b10408f8c2684..fd67d08d05292 100644 --- a/llvm/test/CodeGen/AMDGPU/always-uniform.ll +++ b/llvm/test/CodeGen/AMDGPU/always-uniform.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3 -; RUN: llc -mtriple=amdgcn-amdhsa -mcpu=fiji -amdgpu-scalarize-global-loads < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu8.03-amdhsa -amdgpu-scalarize-global-loads < %s | FileCheck -check-prefix=GCN %s declare i32 @llvm.amdgcn.workitem.id.x() declare i32 @llvm.amdgcn.readfirstlane(i32) diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-mul24-knownbits.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-mul24-knownbits.ll index 3003d456320d5..635beeaa27c0b 100644 --- a/llvm/test/CodeGen/AMDGPU/amdgpu-mul24-knownbits.ll +++ b/llvm/test/CodeGen/AMDGPU/amdgpu-mul24-knownbits.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck --check-prefix=GCN %s -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -early-live-intervals < %s | FileCheck --check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu9.00-amd-amdhsa < %s | FileCheck --check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu9.00-amd-amdhsa -early-live-intervals < %s | FileCheck --check-prefix=GCN %s define weak_odr amdgpu_kernel void @test_mul24_knownbits_kernel(ptr addrspace(1) %p) #4 { ; GCN-LABEL: test_mul24_knownbits_kernel: diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow-codegen.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow-codegen.ll index 20d421abf6a14..98ba5d998c5d2 100644 --- a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow-codegen.ll +++ b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow-codegen.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 -; RUN: opt -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -passes=amdgpu-simplifylib,instcombine -amdgpu-prelink < %s | llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -amdgpu-prelink | FileCheck %s +; RUN: opt -mtriple=amdgpu9.00-amd-amdhsa -passes=amdgpu-simplifylib,instcombine -amdgpu-prelink < %s | llc -mtriple=amdgpu9.00-amd-amdhsa -amdgpu-prelink | FileCheck %s declare hidden float @_Z3powff(float, float) declare hidden double @_Z3powdd(double, double) diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-rootn-codegen.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-rootn-codegen.ll index 7af5b0e177b7f..4832d44c2b621 100644 --- a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-rootn-codegen.ll +++ b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-rootn-codegen.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 -; RUN: opt -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -passes=amdgpu-simplifylib,instcombine < %s | llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 | FileCheck %s +; RUN: opt -mtriple=amdgpu9.00-amd-amdhsa -passes=amdgpu-simplifylib,instcombine < %s | llc -mtriple=amdgpu9.00-amd-amdhsa | FileCheck %s ; Make sure the output of fast rootn expansion actually codegens in ; scalar and vector case. diff --git a/llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit-globalisel.ll b/llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit-globalisel.ll index 35f0ccf5ba62f..aab2968ae7e20 100644 --- a/llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit-globalisel.ll +++ b/llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit-globalisel.ll @@ -1,5 +1,5 @@ ; Test the generation of the attribute amdgpu-no-flat-scratch-init -; RUN: opt -S -O2 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 %s | llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -global-isel -stop-after=irtranslator | FileCheck -check-prefixes=GFX10 %s +; RUN: opt -S -O2 -mtriple=amdgpu10.10-amd-amdhsa %s | llc -global-isel -stop-after=irtranslator | FileCheck -check-prefixes=GFX10 %s ;; tests of addrspacecast diff --git a/llvm/test/CodeGen/AMDGPU/call-encoding.ll b/llvm/test/CodeGen/AMDGPU/call-encoding.ll index 6c36c2424a66e..be5196b0e141c 100644 --- a/llvm/test/CodeGen/AMDGPU/call-encoding.ll +++ b/llvm/test/CodeGen/AMDGPU/call-encoding.ll @@ -1,8 +1,8 @@ -; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -filetype=obj < %s | llvm-objdump --triple=amdgcn--amdhsa --mcpu=fiji -d - | FileCheck --check-prefix=GCN %s -; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -filetype=obj < %s | llvm-objdump --triple=amdgcn--amdhsa --mcpu=gfx900 -d - | FileCheck --check-prefix=GCN %s -; RUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -filetype=obj < %s | llvm-objdump --triple=amdgcn--amdhsa --mcpu=fiji -d - | FileCheck --check-prefix=GCN %s -; RUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -filetype=obj < %s | llvm-objdump --triple=amdgcn--amdhsa --mcpu=gfx900 -d - | FileCheck --check-prefix=GCN %s -; XUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -filetype=obj < %s | llvm-objdump --triple=amdgcn--amdhsa --mcpu=hawaii -d - | FileCheck --check-prefixes=GCN,CI %s +; RUN: llc -global-isel=0 -mtriple=amdgpu8.03-amd-amdhsa -filetype=obj < %s | llvm-objdump --triple=amdgpu8.03--amdhsa -d - | FileCheck --check-prefix=GCN %s +; RUN: llc -global-isel=0 -mtriple=amdgpu9.00-amd-amdhsa -filetype=obj < %s | llvm-objdump --triple=amdgpu9.00--amdhsa -d - | FileCheck --check-prefix=GCN %s +; RUN: llc -global-isel=1 -mtriple=amdgpu8.03-amd-amdhsa -filetype=obj < %s | llvm-objdump --triple=amdgpu8.03--amdhsa -d - | FileCheck --check-prefix=GCN %s +; RUN: llc -global-isel=1 -mtriple=amdgpu9.00-amd-amdhsa -filetype=obj < %s | llvm-objdump --triple=amdgpu9.00--amdhsa -d - | FileCheck --check-prefix=GCN %s +; XUN: llc -mtriple=amdgpu7.01-amd-amdhsa -filetype=obj < %s | llvm-objdump --triple=amdgpu7.01--amdhsa -d - | FileCheck --check-prefixes=GCN,CI %s ; GCN: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-NEXT: s_setpc_b64 diff --git a/llvm/test/CodeGen/AMDGPU/global-atomics-fp-wrong-subtarget.ll b/llvm/test/CodeGen/AMDGPU/global-atomics-fp-wrong-subtarget.ll index 6922e7a353e59..2f5d579d34a5a 100644 --- a/llvm/test/CodeGen/AMDGPU/global-atomics-fp-wrong-subtarget.ll +++ b/llvm/test/CodeGen/AMDGPU/global-atomics-fp-wrong-subtarget.ll @@ -1,5 +1,5 @@ ; RUN: llc -mtriple=amdgpu8.03 < %s | FileCheck -enable-var-scope -check-prefix=GCN %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx803 -filetype=obj < %s | llvm-objdump --triple=amdgcn--amdhsa --mcpu=gfx803 -d - | FileCheck -check-prefix=DISASSEMBLY-VI %s +; RUN: llc -mtriple=amdgpu8.03 -filetype=obj < %s | llvm-objdump --triple=amdgpu8.03--amdhsa -d - | FileCheck -check-prefix=DISASSEMBLY-VI %s ; Make sure we can encode and don't fail on functions which have ; instructions not actually supported by the subtarget. diff --git a/llvm/test/CodeGen/AMDGPU/global_smrd.ll b/llvm/test/CodeGen/AMDGPU/global_smrd.ll index 1007b61c237df..23626eb27af4c 100644 --- a/llvm/test/CodeGen/AMDGPU/global_smrd.ll +++ b/llvm/test/CodeGen/AMDGPU/global_smrd.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=fiji -amdgpu-scalarize-global-loads=true < %s | FileCheck %s +; RUN: llc -mtriple=amdgpu8.03--amdhsa -amdgpu-scalarize-global-loads=true < %s | FileCheck %s ; uniform loads ; CHECK-LABEL: @uniform_load diff --git a/llvm/test/CodeGen/AMDGPU/inline-calls.ll b/llvm/test/CodeGen/AMDGPU/inline-calls.ll index 5695e6d1df48d..f9fe36317333e 100644 --- a/llvm/test/CodeGen/AMDGPU/inline-calls.ll +++ b/llvm/test/CodeGen/AMDGPU/inline-calls.ll @@ -1,5 +1,5 @@ -; RUN: llc -mtriple=amdgcn-unknown-linux-gnu -mcpu=tahiti < %s | FileCheck %s -; RUN: llc -mtriple=amdgcn-unknown-linux-gnu -mcpu=tonga < %s | FileCheck %s +; RUN: llc -mtriple=amdgpu6.00-unknown-linux-gnu < %s | FileCheck %s +; RUN: llc -mtriple=amdgpu8.02-unknown-linux-gnu < %s | FileCheck %s ; RUN: llc -mtriple r600-unknown-linux-gnu -mcpu=redwood < %s | FileCheck %s --check-prefix=R600 ; ALL-NOT: {{^}}func: diff --git a/llvm/test/CodeGen/AMDGPU/inlineasm-sgmask.ll b/llvm/test/CodeGen/AMDGPU/inlineasm-sgmask.ll index 9861f178cc3c5..5233616c5d134 100644 --- a/llvm/test/CodeGen/AMDGPU/inlineasm-sgmask.ll +++ b/llvm/test/CodeGen/AMDGPU/inlineasm-sgmask.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 < %s | FileCheck %s +; RUN: llc -mtriple=amdgpu9.42-amd-amdhsa < %s | FileCheck %s define protected amdgpu_kernel void @test_valu(ptr addrspace(1) noalias noundef writeonly captures(none) %to.coerce, ptr addrspace(1) noalias noundef readonly captures(none) %from.coerce, i32 noundef %k, ptr addrspace(1) noundef writeonly captures(none) %ret.coerce, i32 noundef %length) local_unnamed_addr #0 { ; CHECK-LABEL: test_valu diff --git a/llvm/test/CodeGen/AMDGPU/insert-subvector-unused-scratch.ll b/llvm/test/CodeGen/AMDGPU/insert-subvector-unused-scratch.ll index 332795cd0fceb..4f4c13321e15b 100644 --- a/llvm/test/CodeGen/AMDGPU/insert-subvector-unused-scratch.ll +++ b/llvm/test/CodeGen/AMDGPU/insert-subvector-unused-scratch.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn-amd-- -mcpu=bonaire < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu7.04-amd-- < %s | FileCheck -check-prefix=GCN %s ; Before the fix that this test was committed with, this code would leave ; an unused stack slot, causing ScratchSize to be non-zero. diff --git a/llvm/test/CodeGen/AMDGPU/madmk-madak-encoding-size.ll b/llvm/test/CodeGen/AMDGPU/madmk-madak-encoding-size.ll index 620afd2df4d1b..8b82392b19689 100644 --- a/llvm/test/CodeGen/AMDGPU/madmk-madak-encoding-size.ll +++ b/llvm/test/CodeGen/AMDGPU/madmk-madak-encoding-size.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 -filetype=obj < %s | llvm-objdump --triple=amdgcn-amd-amdhsa --mcpu=gfx803 --disassemble - | FileCheck %s +; RUN: llc -mtriple=amdgpu8.03-amd-amdhsa -filetype=obj < %s | llvm-objdump --triple=amdgpu8.03-amd-amdhsa --disassemble - | FileCheck %s ; Make sure computed instruction sizes for madak/madmk are correct and ; pass the instruction size verifier. diff --git a/llvm/test/CodeGen/AMDGPU/mesa_regression.ll b/llvm/test/CodeGen/AMDGPU/mesa_regression.ll index 05e844b00cecb..d7ef664b737f0 100644 --- a/llvm/test/CodeGen/AMDGPU/mesa_regression.ll +++ b/llvm/test/CodeGen/AMDGPU/mesa_regression.ll @@ -1,4 +1,4 @@ -; RUN: llc -O2 -mtriple=amdgcn--amdhsa -mcpu=fiji -amdgpu-scalarize-global-loads=false < %s | FileCheck %s +; RUN: llc -O2 -mtriple=amdgpu8.03--amdhsa -amdgpu-scalarize-global-loads=false < %s | FileCheck %s ; CHECK-LABEL: %entry ; CHECK: flat_load_dwordx4 diff --git a/llvm/test/CodeGen/AMDGPU/not-scalarize-volatile-load.ll b/llvm/test/CodeGen/AMDGPU/not-scalarize-volatile-load.ll index 360d74f2ca570..2a236bfb193d3 100644 --- a/llvm/test/CodeGen/AMDGPU/not-scalarize-volatile-load.ll +++ b/llvm/test/CodeGen/AMDGPU/not-scalarize-volatile-load.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=fiji -amdgpu-scalarize-global-loads < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu8.03--amdhsa -amdgpu-scalarize-global-loads < %s | FileCheck -check-prefix=GCN %s ; GCN-LABEL: @volatile_load ; GCN: s_load_dwordx2 s[[[LO_SREG:[0-9]+]]:[[HI_SREG:[0-9]+]]], s{{\[[0-9]+:[0-9]+\]}}, 0x0 diff --git a/llvm/test/CodeGen/AMDGPU/optimize-exec-mask-pre-ra-def-after-use.mir b/llvm/test/CodeGen/AMDGPU/optimize-exec-mask-pre-ra-def-after-use.mir index 95b2be6d1b4da..391f20b241c3b 100644 --- a/llvm/test/CodeGen/AMDGPU/optimize-exec-mask-pre-ra-def-after-use.mir +++ b/llvm/test/CodeGen/AMDGPU/optimize-exec-mask-pre-ra-def-after-use.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1030 -verify-machineinstrs -run-pass=si-optimize-exec-masking-pre-ra %s -o - | FileCheck --check-prefix=GCN %s +# RUN: llc -mtriple=amdgpu10.30-amd-amdhsa -verify-machineinstrs -run-pass=si-optimize-exec-masking-pre-ra %s -o - | FileCheck --check-prefix=GCN %s # %8 is defined at the end, but it will be used in bb.2. # Make sure we properly extend its liverange to the beginning of the bb.2. diff --git a/llvm/test/CodeGen/AMDGPU/permlane-op-sel.ll b/llvm/test/CodeGen/AMDGPU/permlane-op-sel.ll index d13a72933b556..40e32066acc8a 100644 --- a/llvm/test/CodeGen/AMDGPU/permlane-op-sel.ll +++ b/llvm/test/CodeGen/AMDGPU/permlane-op-sel.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn -mcpu=gfx1030 -filetype=obj < %s | llvm-objdump --triple=amdgcn--amdhsa --mcpu=gfx1030 -d - | FileCheck -check-prefix=OBJ %s +; RUN: llc -mtriple=amdgpu10.30 -filetype=obj < %s | llvm-objdump --triple=amdgpu10.30--amdhsa -d - | FileCheck -check-prefix=OBJ %s ; RUN: llc -mtriple=amdgpu10.30 -show-mc-encoding < %s | FileCheck -check-prefix=ASM %s declare i32 @llvm.amdgcn.permlane16(i32, i32, i32, i32, i1, i1) diff --git a/llvm/test/CodeGen/AMDGPU/permlane16_var-op-sel.ll b/llvm/test/CodeGen/AMDGPU/permlane16_var-op-sel.ll index d5ef306b1a99e..e836e1ca5a5e3 100644 --- a/llvm/test/CodeGen/AMDGPU/permlane16_var-op-sel.ll +++ b/llvm/test/CodeGen/AMDGPU/permlane16_var-op-sel.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -filetype=obj < %s | llvm-objdump --triple=amdgcn--amdhsa --mcpu=gfx1200 -d - | FileCheck -check-prefix=OBJ %s +; RUN: llc -mtriple=amdgpu12.00 -filetype=obj < %s | llvm-objdump --triple=amdgpu12.00--amdhsa -d - | FileCheck -check-prefix=OBJ %s ; RUN: llc -mtriple=amdgpu12.00 -show-mc-encoding < %s | FileCheck -check-prefix=ASM %s declare i32 @llvm.amdgcn.permlane16.var(i32, i32, i32, i1, i1) diff --git a/llvm/test/CodeGen/AMDGPU/promote-alloca-shufflevector.ll b/llvm/test/CodeGen/AMDGPU/promote-alloca-shufflevector.ll index 7c82500c9b999..052da57217699 100644 --- a/llvm/test/CodeGen/AMDGPU/promote-alloca-shufflevector.ll +++ b/llvm/test/CodeGen/AMDGPU/promote-alloca-shufflevector.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5 -; RUN: opt -mtriple=amdgcn -passes=amdgpu-promote-alloca-to-vector -S < %s | FileCheck %s +; RUN: opt -mtriple=amdgpu -passes=amdgpu-promote-alloca-to-vector -S < %s | FileCheck %s ; Skip promote-alloca in case of an index which is known to be out of bounds. diff --git a/llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll b/llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll index c99a32356da7a..5b232348c4577 100644 --- a/llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll +++ b/llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll @@ -1,10 +1,10 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=amdgcn -mcpu=gfx803 < %s | FileCheck -check-prefixes=GFX8 %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX9,GFX900 %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10 %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx90a < %s | FileCheck -check-prefixes=GFX9,GFX90A %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s +; RUN: llc -mtriple=amdgpu8.03 < %s | FileCheck -check-prefixes=GFX8 %s +; RUN: llc -mtriple=amdgpu9.00 < %s | FileCheck -check-prefixes=GFX9,GFX900 %s +; RUN: llc -mtriple=amdgpu10.10 < %s | FileCheck -check-prefixes=GFX10 %s +; RUN: llc -mtriple=amdgpu9.0a < %s | FileCheck -check-prefixes=GFX9,GFX90A %s +; RUN: llc -mtriple=amdgpu11.00 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s +; RUN: llc -mtriple=amdgpu11.00 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s declare i64 @_Z13get_global_idj(i32) #0 diff --git a/llvm/test/CodeGen/AMDGPU/sgpr-spills-split-regalloc.ll b/llvm/test/CodeGen/AMDGPU/sgpr-spills-split-regalloc.ll index e4b1e4d5c0ba4..96537ae2a2eb1 100644 --- a/llvm/test/CodeGen/AMDGPU/sgpr-spills-split-regalloc.ll +++ b/llvm/test/CodeGen/AMDGPU/sgpr-spills-split-regalloc.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 -O0 < %s | FileCheck -enable-var-scope -check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu8.03-amd-amdhsa -O0 < %s | FileCheck -enable-var-scope -check-prefix=GCN %s define void @child_function() #0 { ; GCN-LABEL: child_function: diff --git a/llvm/test/CodeGen/AMDGPU/spill_more_than_wavesize_csr_sgprs.ll b/llvm/test/CodeGen/AMDGPU/spill_more_than_wavesize_csr_sgprs.ll index 31078bd01c7d5..5246e8dd741e9 100644 --- a/llvm/test/CodeGen/AMDGPU/spill_more_than_wavesize_csr_sgprs.ll +++ b/llvm/test/CodeGen/AMDGPU/spill_more_than_wavesize_csr_sgprs.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 < %s | FileCheck -enable-var-scope %s +; RUN: llc -mtriple=amdgpu8.03-amd-amdhsa < %s | FileCheck -enable-var-scope %s define void @spill_more_than_wavesize_csr_sgprs() #0 { ; CHECK-LABEL: spill_more_than_wavesize_csr_sgprs: diff --git a/llvm/test/CodeGen/AMDGPU/unpack-non-coissue-insts-post-ra-scheduler.mir b/llvm/test/CodeGen/AMDGPU/unpack-non-coissue-insts-post-ra-scheduler.mir index bf7bda6c6f0e4..5685df559b082 100644 --- a/llvm/test/CodeGen/AMDGPU/unpack-non-coissue-insts-post-ra-scheduler.mir +++ b/llvm/test/CodeGen/AMDGPU/unpack-non-coissue-insts-post-ra-scheduler.mir @@ -1,7 +1,7 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6 -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx950 -run-pass=si-pre-emit-peephole -o - %s | FileCheck -check-prefix=GFX950 %s -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 -run-pass=si-pre-emit-peephole -o - %s | FileCheck -check-prefix=GFX942 %s -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -run-pass=si-pre-emit-peephole -o - %s | FileCheck -check-prefix=GFX90A %s +# RUN: llc -mtriple=amdgpu9.50-amd-amdhsa -run-pass=si-pre-emit-peephole -o - %s | FileCheck -check-prefix=GFX950 %s +# RUN: llc -mtriple=amdgpu9.42-amd-amdhsa -run-pass=si-pre-emit-peephole -o - %s | FileCheck -check-prefix=GFX942 %s +# RUN: llc -mtriple=amdgpu9.0a-amd-amdhsa -run-pass=si-pre-emit-peephole -o - %s | FileCheck -check-prefix=GFX90A %s --- name: test_pk_mul_unpacking_f32 diff --git a/llvm/test/CodeGen/AMDGPU/vgpr-large-tuple-alloc-error.ll b/llvm/test/CodeGen/AMDGPU/vgpr-large-tuple-alloc-error.ll index f2320c57d6329..1402f472ba813 100644 --- a/llvm/test/CodeGen/AMDGPU/vgpr-large-tuple-alloc-error.ll +++ b/llvm/test/CodeGen/AMDGPU/vgpr-large-tuple-alloc-error.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -O0 < %s | FileCheck -check-prefix=GFX900 %s -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -O0 < %s | FileCheck -check-prefix=GFX906 %s -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -O0 < %s | FileCheck -check-prefix=GFX908 %s -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -O0 < %s | FileCheck -check-prefix=GFX90a %s +; RUN: llc -mtriple=amdgpu9.00-amd-amdhsa -O0 < %s | FileCheck -check-prefix=GFX900 %s +; RUN: llc -mtriple=amdgpu9.06-amd-amdhsa -O0 < %s | FileCheck -check-prefix=GFX906 %s +; RUN: llc -mtriple=amdgpu9.08-amd-amdhsa -O0 < %s | FileCheck -check-prefix=GFX908 %s +; RUN: llc -mtriple=amdgpu9.0a-amd-amdhsa -O0 < %s | FileCheck -check-prefix=GFX90a %s ; This test used to crash for gfx908 while allocating the tuple. Compared to the other subtargets, ; gfx908 marks an extra VGPR reserved for AGPR to VGPR copy that puts more register pressure. _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
