https://github.com/saxlungs updated https://github.com/llvm/llvm-project/pull/209890
>From d38cffdf67e620294f4ce6d315c9fdd3a955091e Mon Sep 17 00:00:00 2001 From: Domenic Nutile <[email protected]> Date: Wed, 15 Jul 2026 15:54:17 -0400 Subject: [PATCH] [AMDGPU] Refactor some existing test files with true16/fake16 split, add some new test cases --- .../AMDGPU/gfx11-twoaddr-fma-fake16.mir | 102 +++++ .../test/CodeGen/AMDGPU/gfx11-twoaddr-fma.mir | 103 +++-- llvm/test/CodeGen/AMDGPU/llvm.ldexp.ll | 212 ++++++++- ...schedule-regpressure-ilp-metric-spills.mir | 384 ++++++++-------- llvm/test/CodeGen/AMDGPU/shrink-fake16.mir | 55 +++ llvm/test/CodeGen/AMDGPU/shrink-true16.mir | 60 ++- llvm/test/CodeGen/AMDGPU/v_swap_b16.mir | 409 ++++++++++++++++++ .../CodeGen/AMDGPU/waitcnt-vinterp-fake16.mir | 30 ++ llvm/test/CodeGen/AMDGPU/waitcnt-vinterp.mir | 48 +- 9 files changed, 1127 insertions(+), 276 deletions(-) create mode 100644 llvm/test/CodeGen/AMDGPU/gfx11-twoaddr-fma-fake16.mir create mode 100644 llvm/test/CodeGen/AMDGPU/shrink-fake16.mir create mode 100644 llvm/test/CodeGen/AMDGPU/v_swap_b16.mir create mode 100644 llvm/test/CodeGen/AMDGPU/waitcnt-vinterp-fake16.mir diff --git a/llvm/test/CodeGen/AMDGPU/gfx11-twoaddr-fma-fake16.mir b/llvm/test/CodeGen/AMDGPU/gfx11-twoaddr-fma-fake16.mir new file mode 100644 index 0000000000000..ddf3aa2e17ca4 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/gfx11-twoaddr-fma-fake16.mir @@ -0,0 +1,102 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 %s -run-pass twoaddressinstruction -verify-machineinstrs -o - | FileCheck --check-prefixes=GFX11 %s +# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 %s --passes=two-address-instruction -verify-each -o - | FileCheck --check-prefixes=GFX11 %s + +--- +name: test_fmamk_reg_imm_f16 +registers: + - { id: 0, class: vreg_64 } + - { id: 1, class: vgpr_32 } + - { id: 2, class: vgpr_32 } + - { id: 3, class: vgpr_32 } + - { id: 4, class: vgpr_32 } +body: | + bb.0: + + ; GFX11-LABEL: name: test_fmamk_reg_imm_f16 + ; GFX11: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF + ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[DEF]].sub1 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[DEF]].sub0 + ; GFX11-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1078523331, implicit $exec + ; GFX11-NEXT: [[V_FMA_F16_gfx9_fake16_e64_:%[0-9]+]]:vgpr_32 = V_FMA_F16_gfx9_fake16_e64 0, killed [[COPY1]], 0, [[V_MOV_B32_e32_]], 0, killed [[COPY]], 0, 0, 0, implicit $mode, implicit $exec + %0 = IMPLICIT_DEF + %1 = COPY %0.sub1 + %2 = COPY %0.sub0 + %3 = V_MOV_B32_e32 1078523331, implicit $exec + %4 = V_FMAC_F16_fake16_e64 0, killed %2, 0, %3, 0, killed %1, 0, 0, implicit $mode, implicit $exec + +... + +--- +name: test_fmamk_imm_reg_f16 +registers: + - { id: 0, class: vreg_64 } + - { id: 1, class: vgpr_32 } + - { id: 2, class: vgpr_32 } + - { id: 3, class: vgpr_32 } + - { id: 4, class: vgpr_32 } +body: | + bb.0: + + ; GFX11-LABEL: name: test_fmamk_imm_reg_f16 + ; GFX11: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF + ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[DEF]].sub1 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[DEF]].sub0 + ; GFX11-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1078523331, implicit $exec + ; GFX11-NEXT: [[V_FMA_F16_gfx9_fake16_e64_:%[0-9]+]]:vgpr_32 = V_FMA_F16_gfx9_fake16_e64 0, [[COPY1]], 0, killed [[V_MOV_B32_e32_]], 0, killed [[COPY]], 0, 0, 0, implicit $mode, implicit $exec + %0 = IMPLICIT_DEF + %1 = COPY %0.sub1 + %2 = COPY %0.sub0 + %3 = V_MOV_B32_e32 1078523331, implicit $exec + %4 = V_FMAC_F16_fake16_e64 0, %2, 0, killed %3, 0, killed %1, 0, 0, implicit $mode, implicit $exec + +... + +--- +name: test_fmaak_f16 +registers: + - { id: 0, class: vreg_64 } + - { id: 1, class: vgpr_32 } + - { id: 2, class: vgpr_32 } + - { id: 3, class: vgpr_32 } + - { id: 4, class: vgpr_32 } +body: | + bb.0: + + ; GFX11-LABEL: name: test_fmaak_f16 + ; GFX11: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF + ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[DEF]].sub0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[DEF]].sub1 + ; GFX11-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1078523331, implicit $exec + ; GFX11-NEXT: [[V_FMA_F16_gfx9_fake16_e64_:%[0-9]+]]:vgpr_32 = V_FMA_F16_gfx9_fake16_e64 0, killed [[COPY]], 0, [[COPY1]], 0, [[V_MOV_B32_e32_]], 0, 0, 0, implicit $mode, implicit $exec + %0 = IMPLICIT_DEF + %1 = COPY %0.sub0 + %2 = COPY %0.sub1 + %3 = V_MOV_B32_e32 1078523331, implicit $exec + %4 = V_FMAC_F16_fake16_e64 0, killed %1, 0, %2, 0, %3, 0, 0, implicit $mode, implicit $exec +... + +--- +name: test_fmaak_inline_literal_f16 +tracksRegLiveness: true +liveins: + - { reg: '$vgpr0', virtual-reg: '%0' } +body: | + bb.0: + liveins: $vgpr0 + + ; GFX11-LABEL: name: test_fmaak_inline_literal_f16 + ; GFX11: liveins: $vgpr0 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY killed $vgpr0 + ; GFX11-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 49664, implicit $exec + ; GFX11-NEXT: [[V_FMA_F16_gfx9_fake16_e64_:%[0-9]+]]:vgpr_32 = V_FMA_F16_gfx9_fake16_e64 0, 16384, 0, killed [[COPY]], 0, [[V_MOV_B32_e32_]], 0, 0, 0, implicit $mode, implicit $exec + ; GFX11-NEXT: S_ENDPGM 0 + %0:vgpr_32 = COPY killed $vgpr0 + + %1:vgpr_32 = V_MOV_B32_e32 49664, implicit $exec + %2:vgpr_32 = V_FMAC_F16_fake16_e64 0, 16384, 0, killed %0, 0, %1, 0, 0, implicit $mode, implicit $exec + S_ENDPGM 0 + +... + diff --git a/llvm/test/CodeGen/AMDGPU/gfx11-twoaddr-fma.mir b/llvm/test/CodeGen/AMDGPU/gfx11-twoaddr-fma.mir index acea2e501283b..b4c9be4a2f928 100644 --- a/llvm/test/CodeGen/AMDGPU/gfx11-twoaddr-fma.mir +++ b/llvm/test/CodeGen/AMDGPU/gfx11-twoaddr-fma.mir @@ -1,86 +1,86 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgpu11.00 -mattr=-real-true16 %s -run-pass twoaddressinstruction -verify-machineinstrs -o - | FileCheck --check-prefixes=GFX11 %s -# RUN: llc -mtriple=amdgpu11.00 -mattr=-real-true16 %s --passes=two-address-instruction -verify-each -o - | FileCheck --check-prefixes=GFX11 %s +# RUN: llc -mtriple=amdgpu11.00 -mattr=+real-true16 %s -run-pass twoaddressinstruction -verify-machineinstrs -o - | FileCheck --check-prefixes=GFX11 %s +# RUN: llc -mtriple=amdgpu11.00 -mattr=+real-true16 %s --passes=two-address-instruction -verify-each -o - | FileCheck --check-prefixes=GFX11 %s --- name: test_fmamk_reg_imm_f16 registers: - - { id: 0, class: vreg_64 } - - { id: 1, class: vgpr_32 } - - { id: 2, class: vgpr_32 } - - { id: 3, class: vgpr_32 } - - { id: 4, class: vgpr_32 } + - { id: 0, class: vgpr_32 } + - { id: 1, class: vgpr_16 } + - { id: 2, class: vgpr_16 } + - { id: 3, class: vgpr_16 } + - { id: 4, class: vgpr_16 } body: | bb.0: ; GFX11-LABEL: name: test_fmamk_reg_imm_f16 - ; GFX11: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF - ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[DEF]].sub1 - ; GFX11-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[DEF]].sub0 - ; GFX11-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1078523331, implicit $exec - ; GFX11-NEXT: [[V_FMA_F16_gfx9_fake16_e64_:%[0-9]+]]:vgpr_32 = V_FMA_F16_gfx9_fake16_e64 0, killed [[COPY1]], 0, [[V_MOV_B32_e32_]], 0, killed [[COPY]], 0, 0, 0, implicit $mode, implicit $exec + ; GFX11: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF + ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_16 = COPY [[DEF]].hi16 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:vgpr_16 = COPY [[DEF]].lo16 + ; GFX11-NEXT: [[V_MOV_B16_t16_e64_:%[0-9]+]]:vgpr_16 = V_MOV_B16_t16_e64 0, 1078, 0, implicit $exec + ; GFX11-NEXT: [[V_FMA_F16_gfx9_t16_e64_:%[0-9]+]]:vgpr_16 = V_FMA_F16_gfx9_t16_e64 0, killed [[COPY1]], 0, [[V_MOV_B16_t16_e64_]], 0, killed [[COPY]], 0, 0, 0, implicit $mode, implicit $exec %0 = IMPLICIT_DEF - %1 = COPY %0.sub1 - %2 = COPY %0.sub0 - %3 = V_MOV_B32_e32 1078523331, implicit $exec - %4 = V_FMAC_F16_fake16_e64 0, killed %2, 0, %3, 0, killed %1, 0, 0, implicit $mode, implicit $exec + %1 = COPY %0.hi16 + %2 = COPY %0.lo16 + %3 = V_MOV_B16_t16_e64 0, 1078, 0, implicit $exec + %4 = V_FMAC_F16_t16_e64 0, killed %2, 0, %3, 0, killed %1, 0, 0, 0, implicit $mode, implicit $exec ... --- name: test_fmamk_imm_reg_f16 registers: - - { id: 0, class: vreg_64 } - - { id: 1, class: vgpr_32 } - - { id: 2, class: vgpr_32 } - - { id: 3, class: vgpr_32 } - - { id: 4, class: vgpr_32 } + - { id: 0, class: vgpr_32 } + - { id: 1, class: vgpr_16 } + - { id: 2, class: vgpr_16 } + - { id: 3, class: vgpr_16 } + - { id: 4, class: vgpr_16 } body: | bb.0: ; GFX11-LABEL: name: test_fmamk_imm_reg_f16 - ; GFX11: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF - ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[DEF]].sub1 - ; GFX11-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[DEF]].sub0 - ; GFX11-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1078523331, implicit $exec - ; GFX11-NEXT: [[V_FMA_F16_gfx9_fake16_e64_:%[0-9]+]]:vgpr_32 = V_FMA_F16_gfx9_fake16_e64 0, [[COPY1]], 0, killed [[V_MOV_B32_e32_]], 0, killed [[COPY]], 0, 0, 0, implicit $mode, implicit $exec + ; GFX11: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF + ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_16 = COPY [[DEF]].hi16 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:vgpr_16 = COPY [[DEF]].lo16 + ; GFX11-NEXT: [[V_MOV_B16_t16_e64_:%[0-9]+]]:vgpr_16 = V_MOV_B16_t16_e64 0, 1078, 0, implicit $exec + ; GFX11-NEXT: [[V_FMA_F16_gfx9_t16_e64_:%[0-9]+]]:vgpr_16 = V_FMA_F16_gfx9_t16_e64 0, [[COPY1]], 0, killed [[V_MOV_B16_t16_e64_]], 0, killed [[COPY]], 0, 0, 0, implicit $mode, implicit $exec %0 = IMPLICIT_DEF - %1 = COPY %0.sub1 - %2 = COPY %0.sub0 - %3 = V_MOV_B32_e32 1078523331, implicit $exec - %4 = V_FMAC_F16_fake16_e64 0, %2, 0, killed %3, 0, killed %1, 0, 0, implicit $mode, implicit $exec + %1 = COPY %0.hi16 + %2 = COPY %0.lo16 + %3 = V_MOV_B16_t16_e64 0, 1078, 0, implicit $exec + %4 = V_FMAC_F16_t16_e64 0, %2, 0, killed %3, 0, killed %1, 0, 0, 0, implicit $mode, implicit $exec ... --- name: test_fmaak_f16 registers: - - { id: 0, class: vreg_64 } - - { id: 1, class: vgpr_32 } - - { id: 2, class: vgpr_32 } - - { id: 3, class: vgpr_32 } - - { id: 4, class: vgpr_32 } + - { id: 0, class: vgpr_32 } + - { id: 1, class: vgpr_16 } + - { id: 2, class: vgpr_16 } + - { id: 3, class: vgpr_16 } + - { id: 4, class: vgpr_16 } body: | bb.0: ; GFX11-LABEL: name: test_fmaak_f16 - ; GFX11: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF - ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[DEF]].sub0 - ; GFX11-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[DEF]].sub1 - ; GFX11-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1078523331, implicit $exec - ; GFX11-NEXT: [[V_FMA_F16_gfx9_fake16_e64_:%[0-9]+]]:vgpr_32 = V_FMA_F16_gfx9_fake16_e64 0, killed [[COPY]], 0, [[COPY1]], 0, [[V_MOV_B32_e32_]], 0, 0, 0, implicit $mode, implicit $exec + ; GFX11: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF + ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_16 = COPY [[DEF]].hi16 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:vgpr_16 = COPY [[DEF]].lo16 + ; GFX11-NEXT: [[V_MOV_B16_t16_e64_:%[0-9]+]]:vgpr_16 = V_MOV_B16_t16_e64 0, 1078, 0, implicit $exec + ; GFX11-NEXT: [[V_FMA_F16_gfx9_t16_e64_:%[0-9]+]]:vgpr_16 = V_FMA_F16_gfx9_t16_e64 0, killed [[COPY]], 0, [[COPY1]], 0, [[V_MOV_B16_t16_e64_]], 0, 0, 0, implicit $mode, implicit $exec %0 = IMPLICIT_DEF - %1 = COPY %0.sub0 - %2 = COPY %0.sub1 - %3 = V_MOV_B32_e32 1078523331, implicit $exec - %4 = V_FMAC_F16_fake16_e64 0, killed %1, 0, %2, 0, %3, 0, 0, implicit $mode, implicit $exec + %1 = COPY %0.hi16 + %2 = COPY %0.lo16 + %3 = V_MOV_B16_t16_e64 0, 1078, 0, implicit $exec + %4 = V_FMAC_F16_t16_e64 0, killed %1, 0, %2, 0, %3, 0, 0, 0, implicit $mode, implicit $exec ... --- name: test_fmaak_inline_literal_f16 tracksRegLiveness: true liveins: - - { reg: '$vgpr0', virtual-reg: '%0' } + - { reg: '$vgpr0_hi16', virtual-reg: '%0' } body: | bb.0: liveins: $vgpr0 @@ -88,14 +88,13 @@ body: | ; GFX11-LABEL: name: test_fmaak_inline_literal_f16 ; GFX11: liveins: $vgpr0 ; GFX11-NEXT: {{ $}} - ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY killed $vgpr0 - ; GFX11-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 49664, implicit $exec - ; GFX11-NEXT: [[V_FMA_F16_gfx9_fake16_e64_:%[0-9]+]]:vgpr_32 = V_FMA_F16_gfx9_fake16_e64 0, 16384, 0, killed [[COPY]], 0, [[V_MOV_B32_e32_]], 0, 0, 0, implicit $mode, implicit $exec + ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_16 = COPY killed $vgpr0_hi16 + ; GFX11-NEXT: [[V_MOV_B16_t16_e64_:%[0-9]+]]:vgpr_16 = V_MOV_B16_t16_e64 0, 999, 0, implicit $exec + ; GFX11-NEXT: [[V_FMA_F16_gfx9_t16_e64_:%[0-9]+]]:vgpr_16 = V_FMA_F16_gfx9_t16_e64 0, 16384, 0, killed [[COPY]], 0, [[V_MOV_B16_t16_e64_]], 0, 0, 0, implicit $mode, implicit $exec ; GFX11-NEXT: S_ENDPGM 0 - %0:vgpr_32 = COPY killed $vgpr0 - - %1:vgpr_32 = V_MOV_B32_e32 49664, implicit $exec - %2:vgpr_32 = V_FMAC_F16_fake16_e64 0, 16384, 0, killed %0, 0, %1, 0, 0, implicit $mode, implicit $exec + %0:vgpr_16 = COPY killed $vgpr0_hi16 + %1:vgpr_16 = V_MOV_B16_t16_e64 0, 999, 0, implicit $exec + %2:vgpr_16 = V_FMAC_F16_t16_e64 0, 16384, 0, killed %0, 0, %1, 0, 0, 0, implicit $mode, implicit $exec S_ENDPGM 0 ... diff --git a/llvm/test/CodeGen/AMDGPU/llvm.ldexp.ll b/llvm/test/CodeGen/AMDGPU/llvm.ldexp.ll index baefe561e94ae..865cc0e61a919 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.ldexp.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.ldexp.ll @@ -1071,6 +1071,214 @@ define amdgpu_ps double @test_ldexp_f64_i32_uniform(double inreg %a, i32 inreg % ret double %result } +define half @test_ldexp_f16_i32_neg(ptr addrspace(1) %out, half %a, i32 %b) { +; GFX6-LABEL: test_ldexp_f16_i32_neg: +; GFX6: ; %bb.0: +; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX6-NEXT: v_cvt_f32_f16_e32 v0, v2 +; GFX6-NEXT: v_sub_i32_e32 v1, vcc, 0, v3 +; GFX6-NEXT: v_ldexp_f32_e32 v0, v0, v1 +; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0 +; GFX6-NEXT: s_setpc_b64 s[30:31] +; +; GFX8-LABEL: test_ldexp_f16_i32_neg: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_sub_u32_e32 v0, vcc, 0, v3 +; GFX8-NEXT: s_movk_i32 s4, 0x8000 +; GFX8-NEXT: v_mov_b32_e32 v1, 0x7fff +; GFX8-NEXT: v_med3_i32 v0, v0, s4, v1 +; GFX8-NEXT: v_ldexp_f16_e32 v0, v2, v0 +; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: test_ldexp_f16_i32_neg: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_sub_u32_e32 v0, 0, v3 +; GFX9-NEXT: s_movk_i32 s4, 0x8000 +; GFX9-NEXT: v_mov_b32_e32 v1, 0x7fff +; GFX9-NEXT: v_med3_i32 v0, v0, s4, v1 +; GFX9-NEXT: v_ldexp_f16_e32 v0, v2, v0 +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-SDAG-TRUE16-LABEL: test_ldexp_f16_i32_neg: +; GFX11-SDAG-TRUE16: ; %bb.0: +; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-SDAG-TRUE16-NEXT: v_sub_nc_u32_e32 v0, 0, v3 +; GFX11-SDAG-TRUE16-NEXT: s_movk_i32 s0, 0x8000 +; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) +; GFX11-SDAG-TRUE16-NEXT: v_med3_i32 v0, v0, s0, 0x7fff +; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-SDAG-TRUE16-NEXT: v_ldexp_f16_e32 v0.l, v2.l, v0.l +; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-SDAG-FAKE16-LABEL: test_ldexp_f16_i32_neg: +; GFX11-SDAG-FAKE16: ; %bb.0: +; GFX11-SDAG-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-SDAG-FAKE16-NEXT: v_sub_nc_u32_e32 v0, 0, v3 +; GFX11-SDAG-FAKE16-NEXT: s_movk_i32 s0, 0x8000 +; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) +; GFX11-SDAG-FAKE16-NEXT: v_med3_i32 v0, v0, s0, 0x7fff +; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-SDAG-FAKE16-NEXT: v_ldexp_f16_e32 v0, v2, v0 +; GFX11-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-GISEL-TRUE16-LABEL: test_ldexp_f16_i32_neg: +; GFX11-GISEL-TRUE16: ; %bb.0: +; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-GISEL-TRUE16-NEXT: v_sub_nc_u32_e32 v0, 0, v3 +; GFX11-GISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 0x7fff +; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-GISEL-TRUE16-NEXT: v_med3_i32 v0, 0xffff8000, v0, v1 +; GFX11-GISEL-TRUE16-NEXT: v_ldexp_f16_e32 v0.l, v2.l, v0.l +; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-GISEL-FAKE16-LABEL: test_ldexp_f16_i32_neg: +; GFX11-GISEL-FAKE16: ; %bb.0: +; GFX11-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-GISEL-FAKE16-NEXT: v_sub_nc_u32_e32 v0, 0, v3 +; GFX11-GISEL-FAKE16-NEXT: s_movk_i32 s0, 0x8000 +; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) +; GFX11-GISEL-FAKE16-NEXT: v_med3_i32 v0, v0, s0, 0x7fff +; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-GISEL-FAKE16-NEXT: v_ldexp_f16_e32 v0, v2, v0 +; GFX11-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31] + %b.neg = sub i32 0, %b + %result = call half @llvm.ldexp.f16_i32(half %a, i32 %b.neg) + ret half %result +} + +define half @ldexp_f16_i32_imm_a(ptr addrspace(1) %out, i32 %b) { +; GFX6-LABEL: ldexp_f16_i32_imm_a: +; GFX6: ; %bb.0: +; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX6-NEXT: v_ldexp_f32_e32 v0, 2.0, v2 +; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0 +; GFX6-NEXT: s_setpc_b64 s[30:31] +; +; GFX8-SDAG-LABEL: ldexp_f16_i32_imm_a: +; GFX8-SDAG: ; %bb.0: +; GFX8-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-SDAG-NEXT: s_movk_i32 s4, 0x8000 +; GFX8-SDAG-NEXT: v_mov_b32_e32 v0, 0x7fff +; GFX8-SDAG-NEXT: v_med3_i32 v0, v2, s4, v0 +; GFX8-SDAG-NEXT: v_ldexp_f16_e32 v0, 2.0, v0 +; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-SDAG-LABEL: ldexp_f16_i32_imm_a: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: s_movk_i32 s4, 0x8000 +; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, 0x7fff +; GFX9-SDAG-NEXT: v_med3_i32 v0, v2, s4, v0 +; GFX9-SDAG-NEXT: v_ldexp_f16_e32 v0, 2.0, v0 +; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-SDAG-TRUE16-LABEL: ldexp_f16_i32_imm_a: +; GFX11-SDAG-TRUE16: ; %bb.0: +; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-SDAG-TRUE16-NEXT: s_movk_i32 s0, 0x8000 +; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-SDAG-TRUE16-NEXT: v_med3_i32 v0, v2, s0, 0x7fff +; GFX11-SDAG-TRUE16-NEXT: v_ldexp_f16_e32 v0.l, 2.0, v0.l +; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-SDAG-FAKE16-LABEL: ldexp_f16_i32_imm_a: +; GFX11-SDAG-FAKE16: ; %bb.0: +; GFX11-SDAG-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-SDAG-FAKE16-NEXT: s_movk_i32 s0, 0x8000 +; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-SDAG-FAKE16-NEXT: v_med3_i32 v0, v2, s0, 0x7fff +; GFX11-SDAG-FAKE16-NEXT: v_ldexp_f16_e32 v0, 2.0, v0 +; GFX11-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX8-GISEL-LABEL: ldexp_f16_i32_imm_a: +; GFX8-GISEL: ; %bb.0: +; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-GISEL-NEXT: v_mov_b32_e32 v0, 0xffff8000 +; GFX8-GISEL-NEXT: v_mov_b32_e32 v1, 0x7fff +; GFX8-GISEL-NEXT: v_med3_i32 v0, v2, v0, v1 +; GFX8-GISEL-NEXT: v_ldexp_f16_e32 v0, 2.0, v0 +; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-GISEL-LABEL: ldexp_f16_i32_imm_a: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, 0xffff8000 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, 0x7fff +; GFX9-GISEL-NEXT: v_med3_i32 v0, v2, v0, v1 +; GFX9-GISEL-NEXT: v_ldexp_f16_e32 v0, 2.0, v0 +; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-GISEL-TRUE16-LABEL: ldexp_f16_i32_imm_a: +; GFX11-GISEL-TRUE16: ; %bb.0: +; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-GISEL-TRUE16-NEXT: v_mov_b32_e32 v0, 0x7fff +; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-GISEL-TRUE16-NEXT: v_med3_i32 v0, 0xffff8000, v2, v0 +; GFX11-GISEL-TRUE16-NEXT: v_ldexp_f16_e32 v0.l, 2.0, v0.l +; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-GISEL-FAKE16-LABEL: ldexp_f16_i32_imm_a: +; GFX11-GISEL-FAKE16: ; %bb.0: +; GFX11-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-GISEL-FAKE16-NEXT: v_mov_b32_e32 v0, 0x7fff +; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-GISEL-FAKE16-NEXT: v_med3_i32 v0, 0xffff8000, v2, v0 +; GFX11-GISEL-FAKE16-NEXT: v_ldexp_f16_e32 v0, 2.0, v0 +; GFX11-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31] + %result = call half @llvm.ldexp.f16_i32(half 2.0, i32 %b) + ret half %result +} + +define half @test_ldexp_f16_i32_imm_b(ptr addrspace(1) %out, half %a) { +; GFX6-LABEL: test_ldexp_f16_i32_imm_b: +; GFX6: ; %bb.0: +; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX6-NEXT: v_cvt_f32_f16_e32 v0, v2 +; GFX6-NEXT: v_ldexp_f32_e64 v0, v0, 2 +; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0 +; GFX6-NEXT: s_setpc_b64 s[30:31] +; +; GFX8-LABEL: test_ldexp_f16_i32_imm_b: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_ldexp_f16_e64 v0, v2, 2 +; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: test_ldexp_f16_i32_imm_b: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_ldexp_f16_e64 v0, v2, 2 +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-SDAG-TRUE16-LABEL: test_ldexp_f16_i32_imm_b: +; GFX11-SDAG-TRUE16: ; %bb.0: +; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-SDAG-TRUE16-NEXT: v_ldexp_f16_e64 v0.l, v2.l, 2 +; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-SDAG-FAKE16-LABEL: test_ldexp_f16_i32_imm_b: +; GFX11-SDAG-FAKE16: ; %bb.0: +; GFX11-SDAG-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-SDAG-FAKE16-NEXT: v_ldexp_f16_e64 v0, v2, 2 +; GFX11-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-GISEL-TRUE16-LABEL: test_ldexp_f16_i32_imm_b: +; GFX11-GISEL-TRUE16: ; %bb.0: +; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-GISEL-TRUE16-NEXT: v_ldexp_f16_e64 v0.l, v2.l, 2 +; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-GISEL-FAKE16-LABEL: test_ldexp_f16_i32_imm_b: +; GFX11-GISEL-FAKE16: ; %bb.0: +; GFX11-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-GISEL-FAKE16-NEXT: v_ldexp_f16_e64 v0, v2, 2 +; GFX11-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31] + %result = call half @llvm.ldexp.f16_i32(half %a, i32 2) + ret half %result +} + declare float @llvm.ldexp.f32.i32(float, i32) #0 declare float @llvm.ldexp.f32.i16(float, i16) #0 declare float @llvm.ldexp.f32.i64(float, i64) #0 @@ -1091,7 +1299,3 @@ attributes #0 = { nounwind readnone } ;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: ; GFX6-GISEL: {{.*}} ; GFX6-SDAG: {{.*}} -; GFX8-GISEL: {{.*}} -; GFX8-SDAG: {{.*}} -; GFX9-GISEL: {{.*}} -; GFX9-SDAG: {{.*}} diff --git a/llvm/test/CodeGen/AMDGPU/schedule-regpressure-ilp-metric-spills.mir b/llvm/test/CodeGen/AMDGPU/schedule-regpressure-ilp-metric-spills.mir index fec3c1b3a6e1d..6d9f8b6b3c2c5 100644 --- a/llvm/test/CodeGen/AMDGPU/schedule-regpressure-ilp-metric-spills.mir +++ b/llvm/test/CodeGen/AMDGPU/schedule-regpressure-ilp-metric-spills.mir @@ -424,18 +424,18 @@ body: | %264:vgpr_32 = V_LSHL_OR_B32_e64 %254, 8, %263, implicit $exec %265:vreg_128 = DS_READ_B128_gfx9 %264, 0, 0, implicit $exec :: (load (s128), addrspace 3) %266:vreg_128 = DS_READ_B128_gfx9 %264, 16, 0, implicit $exec :: (load (s128), addrspace 3) - %267:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %265.sub0, 0, 0, implicit $mode, implicit $exec - %268:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %265.sub1, 0, 0, implicit $mode, implicit $exec - %269:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %265.sub2, 0, 0, implicit $mode, implicit $exec - %270:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %265.sub3, 0, 0, implicit $mode, implicit $exec - %271:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %266.sub0, 0, 0, implicit $mode, implicit $exec - %272:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %266.sub1, 0, 0, implicit $mode, implicit $exec - %273:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %266.sub2, 0, 0, implicit $mode, implicit $exec - %274:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %266.sub3, 0, 0, implicit $mode, implicit $exec - undef %275.sub3:vreg_128 = V_PACK_B32_F16_e64 0, %273, 0, %274, 0, 0, implicit $mode, implicit $exec - %275.sub2:vreg_128 = V_PACK_B32_F16_e64 0, %271, 0, %272, 0, 0, implicit $mode, implicit $exec - %275.sub1:vreg_128 = V_PACK_B32_F16_e64 0, %269, 0, %270, 0, 0, implicit $mode, implicit $exec - %275.sub0:vreg_128 = V_PACK_B32_F16_e64 0, %267, 0, %268, 0, 0, implicit $mode, implicit $exec + %267:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %265.sub0, 0, 0, 0, implicit $mode, implicit $exec + %268:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %265.sub1, 0, 0, 0, implicit $mode, implicit $exec + %269:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %265.sub2, 0, 0, 0, implicit $mode, implicit $exec + %270:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %265.sub3, 0, 0, 0, implicit $mode, implicit $exec + %271:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %266.sub0, 0, 0, 0, implicit $mode, implicit $exec + %272:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %266.sub1, 0, 0, 0, implicit $mode, implicit $exec + %273:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %266.sub2, 0, 0, 0, implicit $mode, implicit $exec + %274:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %266.sub3, 0, 0, 0, implicit $mode, implicit $exec + undef %275.sub3:vreg_128 = V_PACK_B32_F16_t16_e64 0, %273, 0, %274, 0, 0, implicit $mode, implicit $exec + %275.sub2:vreg_128 = V_PACK_B32_F16_t16_e64 0, %271, 0, %272, 0, 0, implicit $mode, implicit $exec + %275.sub1:vreg_128 = V_PACK_B32_F16_t16_e64 0, %269, 0, %270, 0, 0, implicit $mode, implicit $exec + %275.sub0:vreg_128 = V_PACK_B32_F16_t16_e64 0, %267, 0, %268, 0, 0, implicit $mode, implicit $exec %4.sub2:sgpr_128 = S_LSHL_B32 %10, 1, implicit-def dead $scc %4.sub3:sgpr_128 = COPY %171.sub3 %276:vgpr_32 = V_LSHLREV_B32_e64 1, %260.sub0, implicit $exec @@ -446,18 +446,18 @@ body: | DS_WRITE2ST64_B32_gfx9 %262, %212.sub6, %212.sub7, 6, 7, 0, implicit $exec :: (store (s32), addrspace 3) %277:vreg_128 = DS_READ_B128_gfx9 %264, 0, 0, implicit $exec :: (load (s128), addrspace 3) %278:vreg_128 = DS_READ_B128_gfx9 %264, 16, 0, implicit $exec :: (load (s128), addrspace 3) - %279:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %277.sub0, 0, 0, implicit $mode, implicit $exec - %280:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %277.sub1, 0, 0, implicit $mode, implicit $exec - %281:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %277.sub2, 0, 0, implicit $mode, implicit $exec - %282:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %277.sub3, 0, 0, implicit $mode, implicit $exec - %283:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %278.sub0, 0, 0, implicit $mode, implicit $exec - %284:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %278.sub1, 0, 0, implicit $mode, implicit $exec - %285:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %278.sub2, 0, 0, implicit $mode, implicit $exec - %286:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %278.sub3, 0, 0, implicit $mode, implicit $exec - undef %287.sub3:vreg_128 = V_PACK_B32_F16_e64 0, %285, 0, %286, 0, 0, implicit $mode, implicit $exec - %287.sub2:vreg_128 = V_PACK_B32_F16_e64 0, %283, 0, %284, 0, 0, implicit $mode, implicit $exec - %287.sub1:vreg_128 = V_PACK_B32_F16_e64 0, %281, 0, %282, 0, 0, implicit $mode, implicit $exec - %287.sub0:vreg_128 = V_PACK_B32_F16_e64 0, %279, 0, %280, 0, 0, implicit $mode, implicit $exec + %279:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %277.sub0, 0, 0, 0, implicit $mode, implicit $exec + %280:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %277.sub1, 0, 0, 0, implicit $mode, implicit $exec + %281:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %277.sub2, 0, 0, 0, implicit $mode, implicit $exec + %282:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %277.sub3, 0, 0, 0, implicit $mode, implicit $exec + %283:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %278.sub0, 0, 0, 0, implicit $mode, implicit $exec + %284:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %278.sub1, 0, 0, 0, implicit $mode, implicit $exec + %285:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %278.sub2, 0, 0, 0, implicit $mode, implicit $exec + %286:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %278.sub3, 0, 0, 0, implicit $mode, implicit $exec + undef %287.sub3:vreg_128 = V_PACK_B32_F16_t16_e64 0, %285, 0, %286, 0, 0, implicit $mode, implicit $exec + %287.sub2:vreg_128 = V_PACK_B32_F16_t16_e64 0, %283, 0, %284, 0, 0, implicit $mode, implicit $exec + %287.sub1:vreg_128 = V_PACK_B32_F16_t16_e64 0, %281, 0, %282, 0, 0, implicit $mode, implicit $exec + %287.sub0:vreg_128 = V_PACK_B32_F16_t16_e64 0, %279, 0, %280, 0, 0, implicit $mode, implicit $exec BUFFER_STORE_DWORDX4_OFFEN_exact %287, %276, %4, 0, 128, 0, 0, implicit $exec :: (dereferenceable store (s128), align 1, addrspace 7) DS_WRITE2ST64_B32_gfx9 %262, %246.sub0, %246.sub1, 0, 1, 0, implicit $exec :: (store (s32), addrspace 3) DS_WRITE2ST64_B32_gfx9 %262, %246.sub2, %246.sub3, 2, 3, 0, implicit $exec :: (store (s32), addrspace 3) @@ -465,18 +465,18 @@ body: | DS_WRITE2ST64_B32_gfx9 %262, %246.sub6, %246.sub7, 6, 7, 0, implicit $exec :: (store (s32), addrspace 3) %288:vreg_128 = DS_READ_B128_gfx9 %264, 0, 0, implicit $exec :: (load (s128), addrspace 3) %289:vreg_128 = DS_READ_B128_gfx9 %264, 16, 0, implicit $exec :: (load (s128), addrspace 3) - %290:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %288.sub0, 0, 0, implicit $mode, implicit $exec - %291:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %288.sub1, 0, 0, implicit $mode, implicit $exec - %292:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %288.sub2, 0, 0, implicit $mode, implicit $exec - %293:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %288.sub3, 0, 0, implicit $mode, implicit $exec - %294:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %289.sub0, 0, 0, implicit $mode, implicit $exec - %295:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %289.sub1, 0, 0, implicit $mode, implicit $exec - %296:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %289.sub2, 0, 0, implicit $mode, implicit $exec - %297:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %289.sub3, 0, 0, implicit $mode, implicit $exec - undef %298.sub3:vreg_128 = V_PACK_B32_F16_e64 0, %296, 0, %297, 0, 0, implicit $mode, implicit $exec - %298.sub2:vreg_128 = V_PACK_B32_F16_e64 0, %294, 0, %295, 0, 0, implicit $mode, implicit $exec - %298.sub1:vreg_128 = V_PACK_B32_F16_e64 0, %292, 0, %293, 0, 0, implicit $mode, implicit $exec - %298.sub0:vreg_128 = V_PACK_B32_F16_e64 0, %290, 0, %291, 0, 0, implicit $mode, implicit $exec + %290:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %288.sub0, 0, 0, 0, implicit $mode, implicit $exec + %291:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %288.sub1, 0, 0, 0, implicit $mode, implicit $exec + %292:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %288.sub2, 0, 0, 0, implicit $mode, implicit $exec + %293:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %288.sub3, 0, 0, 0, implicit $mode, implicit $exec + %294:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %289.sub0, 0, 0, 0, implicit $mode, implicit $exec + %295:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %289.sub1, 0, 0, 0, implicit $mode, implicit $exec + %296:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %289.sub2, 0, 0, 0, implicit $mode, implicit $exec + %297:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %289.sub3, 0, 0, 0, implicit $mode, implicit $exec + undef %298.sub3:vreg_128 = V_PACK_B32_F16_t16_e64 0, %296, 0, %297, 0, 0, implicit $mode, implicit $exec + %298.sub2:vreg_128 = V_PACK_B32_F16_t16_e64 0, %294, 0, %295, 0, 0, implicit $mode, implicit $exec + %298.sub1:vreg_128 = V_PACK_B32_F16_t16_e64 0, %292, 0, %293, 0, 0, implicit $mode, implicit $exec + %298.sub0:vreg_128 = V_PACK_B32_F16_t16_e64 0, %290, 0, %291, 0, 0, implicit $mode, implicit $exec BUFFER_STORE_DWORDX4_OFFEN_exact %298, %276, %4, 0, 256, 0, 0, implicit $exec :: (dereferenceable store (s128), align 1, addrspace 7) %299:vgpr_32 = V_ADD_U32_e64 192, %260.sub0, 0, implicit $exec DS_WRITE2ST64_B32_gfx9 %262, %250.sub0, %250.sub1, 0, 1, 0, implicit $exec :: (store (s32), addrspace 3) @@ -485,18 +485,18 @@ body: | DS_WRITE2ST64_B32_gfx9 %262, %250.sub6, %250.sub7, 6, 7, 0, implicit $exec :: (store (s32), addrspace 3) %300:vreg_128 = DS_READ_B128_gfx9 %264, 0, 0, implicit $exec :: (load (s128), addrspace 3) %301:vreg_128 = DS_READ_B128_gfx9 %264, 16, 0, implicit $exec :: (load (s128), addrspace 3) - %302:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %300.sub0, 0, 0, implicit $mode, implicit $exec - %303:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %300.sub1, 0, 0, implicit $mode, implicit $exec - %304:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %300.sub2, 0, 0, implicit $mode, implicit $exec - %305:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %300.sub3, 0, 0, implicit $mode, implicit $exec - %306:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %301.sub0, 0, 0, implicit $mode, implicit $exec - %307:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %301.sub1, 0, 0, implicit $mode, implicit $exec - %308:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %301.sub2, 0, 0, implicit $mode, implicit $exec - %309:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %301.sub3, 0, 0, implicit $mode, implicit $exec - undef %310.sub3:vreg_128 = V_PACK_B32_F16_e64 0, %308, 0, %309, 0, 0, implicit $mode, implicit $exec - %310.sub2:vreg_128 = V_PACK_B32_F16_e64 0, %306, 0, %307, 0, 0, implicit $mode, implicit $exec - %310.sub1:vreg_128 = V_PACK_B32_F16_e64 0, %304, 0, %305, 0, 0, implicit $mode, implicit $exec - %310.sub0:vreg_128 = V_PACK_B32_F16_e64 0, %302, 0, %303, 0, 0, implicit $mode, implicit $exec + %302:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %300.sub0, 0, 0, 0, implicit $mode, implicit $exec + %303:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %300.sub1, 0, 0, 0, implicit $mode, implicit $exec + %304:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %300.sub2, 0, 0, 0, implicit $mode, implicit $exec + %305:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %300.sub3, 0, 0, 0, implicit $mode, implicit $exec + %306:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %301.sub0, 0, 0, 0, implicit $mode, implicit $exec + %307:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %301.sub1, 0, 0, 0, implicit $mode, implicit $exec + %308:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %301.sub2, 0, 0, 0, implicit $mode, implicit $exec + %309:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %301.sub3, 0, 0, 0, implicit $mode, implicit $exec + undef %310.sub3:vreg_128 = V_PACK_B32_F16_t16_e64 0, %308, 0, %309, 0, 0, implicit $mode, implicit $exec + %310.sub2:vreg_128 = V_PACK_B32_F16_t16_e64 0, %306, 0, %307, 0, 0, implicit $mode, implicit $exec + %310.sub1:vreg_128 = V_PACK_B32_F16_t16_e64 0, %304, 0, %305, 0, 0, implicit $mode, implicit $exec + %310.sub0:vreg_128 = V_PACK_B32_F16_t16_e64 0, %302, 0, %303, 0, 0, implicit $mode, implicit $exec %311:vgpr_32 = V_LSHLREV_B32_e64 1, %299, implicit $exec BUFFER_STORE_DWORDX4_OFFEN_exact %310, %311, %4, 0, 0, 0, 0, implicit $exec :: (dereferenceable store (s128), align 1, addrspace 7) %312:sreg_32 = nsw S_LSHL_B32 %9, 5, implicit-def dead $scc @@ -506,18 +506,18 @@ body: | DS_WRITE2ST64_B32_gfx9 %262, %253.sub6, %253.sub7, 6, 7, 0, implicit $exec :: (store (s32), addrspace 3) %313:vreg_128 = DS_READ_B128_gfx9 %264, 0, 0, implicit $exec :: (load (s128), addrspace 3) %314:vreg_128 = DS_READ_B128_gfx9 %264, 16, 0, implicit $exec :: (load (s128), addrspace 3) - %315:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %313.sub0, 0, 0, implicit $mode, implicit $exec - %316:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %313.sub1, 0, 0, implicit $mode, implicit $exec - %317:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %313.sub2, 0, 0, implicit $mode, implicit $exec - %318:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %313.sub3, 0, 0, implicit $mode, implicit $exec - %319:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %314.sub0, 0, 0, implicit $mode, implicit $exec - %320:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %314.sub1, 0, 0, implicit $mode, implicit $exec - %321:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %314.sub2, 0, 0, implicit $mode, implicit $exec - %322:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %314.sub3, 0, 0, implicit $mode, implicit $exec - undef %323.sub3:vreg_128 = V_PACK_B32_F16_e64 0, %321, 0, %322, 0, 0, implicit $mode, implicit $exec - %323.sub2:vreg_128 = V_PACK_B32_F16_e64 0, %319, 0, %320, 0, 0, implicit $mode, implicit $exec - %323.sub1:vreg_128 = V_PACK_B32_F16_e64 0, %317, 0, %318, 0, 0, implicit $mode, implicit $exec - %323.sub0:vreg_128 = V_PACK_B32_F16_e64 0, %315, 0, %316, 0, 0, implicit $mode, implicit $exec + %315:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %313.sub0, 0, 0, 0, implicit $mode, implicit $exec + %316:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %313.sub1, 0, 0, 0, implicit $mode, implicit $exec + %317:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %313.sub2, 0, 0, 0, implicit $mode, implicit $exec + %318:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %313.sub3, 0, 0, 0, implicit $mode, implicit $exec + %319:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %314.sub0, 0, 0, 0, implicit $mode, implicit $exec + %320:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %314.sub1, 0, 0, 0, implicit $mode, implicit $exec + %321:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %314.sub2, 0, 0, 0, implicit $mode, implicit $exec + %322:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %314.sub3, 0, 0, 0, implicit $mode, implicit $exec + undef %323.sub3:vreg_128 = V_PACK_B32_F16_t16_e64 0, %321, 0, %322, 0, 0, implicit $mode, implicit $exec + %323.sub2:vreg_128 = V_PACK_B32_F16_t16_e64 0, %319, 0, %320, 0, 0, implicit $mode, implicit $exec + %323.sub1:vreg_128 = V_PACK_B32_F16_t16_e64 0, %317, 0, %318, 0, 0, implicit $mode, implicit $exec + %323.sub0:vreg_128 = V_PACK_B32_F16_t16_e64 0, %315, 0, %316, 0, 0, implicit $mode, implicit $exec %324:vgpr_32 = V_ADD_LSHL_U32_e64 %299, %312, 1, implicit $exec BUFFER_STORE_DWORDX4_OFFEN_exact %323, %324, %4, 0, 0, 0, 0, implicit $exec :: (dereferenceable store (s128), align 1, addrspace 7) DS_WRITE2ST64_B32_gfx9 %262, %214.sub0, %214.sub1, 0, 1, 0, implicit $exec :: (store (s32), addrspace 3) @@ -526,18 +526,18 @@ body: | DS_WRITE2ST64_B32_gfx9 %262, %214.sub6, %214.sub7, 6, 7, 0, implicit $exec :: (store (s32), addrspace 3) %325:vreg_128 = DS_READ_B128_gfx9 %264, 0, 0, implicit $exec :: (load (s128), addrspace 3) %326:vreg_128 = DS_READ_B128_gfx9 %264, 16, 0, implicit $exec :: (load (s128), addrspace 3) - %327:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %325.sub0, 0, 0, implicit $mode, implicit $exec - %328:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %325.sub1, 0, 0, implicit $mode, implicit $exec - %329:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %325.sub2, 0, 0, implicit $mode, implicit $exec - %330:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %325.sub3, 0, 0, implicit $mode, implicit $exec - %331:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %326.sub0, 0, 0, implicit $mode, implicit $exec - %332:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %326.sub1, 0, 0, implicit $mode, implicit $exec - %333:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %326.sub2, 0, 0, implicit $mode, implicit $exec - %334:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %326.sub3, 0, 0, implicit $mode, implicit $exec - undef %335.sub3:vreg_128 = V_PACK_B32_F16_e64 0, %333, 0, %334, 0, 0, implicit $mode, implicit $exec - %335.sub2:vreg_128 = V_PACK_B32_F16_e64 0, %331, 0, %332, 0, 0, implicit $mode, implicit $exec - %335.sub1:vreg_128 = V_PACK_B32_F16_e64 0, %329, 0, %330, 0, 0, implicit $mode, implicit $exec - %335.sub0:vreg_128 = V_PACK_B32_F16_e64 0, %327, 0, %328, 0, 0, implicit $mode, implicit $exec + %327:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %325.sub0, 0, 0, 0, implicit $mode, implicit $exec + %328:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %325.sub1, 0, 0, 0, implicit $mode, implicit $exec + %329:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %325.sub2, 0, 0, 0, implicit $mode, implicit $exec + %330:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %325.sub3, 0, 0, 0, implicit $mode, implicit $exec + %331:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %326.sub0, 0, 0, 0, implicit $mode, implicit $exec + %332:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %326.sub1, 0, 0, 0, implicit $mode, implicit $exec + %333:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %326.sub2, 0, 0, 0, implicit $mode, implicit $exec + %334:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %326.sub3, 0, 0, 0, implicit $mode, implicit $exec + undef %335.sub3:vreg_128 = V_PACK_B32_F16_t16_e64 0, %333, 0, %334, 0, 0, implicit $mode, implicit $exec + %335.sub2:vreg_128 = V_PACK_B32_F16_t16_e64 0, %331, 0, %332, 0, 0, implicit $mode, implicit $exec + %335.sub1:vreg_128 = V_PACK_B32_F16_t16_e64 0, %329, 0, %330, 0, 0, implicit $mode, implicit $exec + %335.sub0:vreg_128 = V_PACK_B32_F16_t16_e64 0, %327, 0, %328, 0, 0, implicit $mode, implicit $exec %336:vgpr_32 = V_ADD_U32_e64 -128, %324, 0, implicit $exec BUFFER_STORE_DWORDX4_OFFEN_exact %335, %336, %4, 0, 0, 0, 0, implicit $exec :: (dereferenceable store (s128), align 1, addrspace 7) DS_WRITE2ST64_B32_gfx9 %262, %247.sub0, %247.sub1, 0, 1, 0, implicit $exec :: (store (s32), addrspace 3) @@ -546,18 +546,18 @@ body: | DS_WRITE2ST64_B32_gfx9 %262, %247.sub6, %247.sub7, 6, 7, 0, implicit $exec :: (store (s32), addrspace 3) %337:vreg_128 = DS_READ_B128_gfx9 %264, 0, 0, implicit $exec :: (load (s128), addrspace 3) %338:vreg_128 = DS_READ_B128_gfx9 %264, 16, 0, implicit $exec :: (load (s128), addrspace 3) - %339:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %337.sub0, 0, 0, implicit $mode, implicit $exec - %340:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %337.sub1, 0, 0, implicit $mode, implicit $exec - %341:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %337.sub2, 0, 0, implicit $mode, implicit $exec - %342:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %337.sub3, 0, 0, implicit $mode, implicit $exec - %343:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %338.sub0, 0, 0, implicit $mode, implicit $exec - %344:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %338.sub1, 0, 0, implicit $mode, implicit $exec - %345:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %338.sub2, 0, 0, implicit $mode, implicit $exec - %346:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %338.sub3, 0, 0, implicit $mode, implicit $exec - undef %347.sub3:vreg_128 = V_PACK_B32_F16_e64 0, %345, 0, %346, 0, 0, implicit $mode, implicit $exec - %347.sub2:vreg_128 = V_PACK_B32_F16_e64 0, %343, 0, %344, 0, 0, implicit $mode, implicit $exec - %347.sub1:vreg_128 = V_PACK_B32_F16_e64 0, %341, 0, %342, 0, 0, implicit $mode, implicit $exec - %347.sub0:vreg_128 = V_PACK_B32_F16_e64 0, %339, 0, %340, 0, 0, implicit $mode, implicit $exec + %339:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %337.sub0, 0, 0, 0, implicit $mode, implicit $exec + %340:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %337.sub1, 0, 0, 0, implicit $mode, implicit $exec + %341:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %337.sub2, 0, 0, 0, implicit $mode, implicit $exec + %342:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %337.sub3, 0, 0, 0, implicit $mode, implicit $exec + %343:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %338.sub0, 0, 0, 0, implicit $mode, implicit $exec + %344:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %338.sub1, 0, 0, 0, implicit $mode, implicit $exec + %345:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %338.sub2, 0, 0, 0, implicit $mode, implicit $exec + %346:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %338.sub3, 0, 0, 0, implicit $mode, implicit $exec + undef %347.sub3:vreg_128 = V_PACK_B32_F16_t16_e64 0, %345, 0, %346, 0, 0, implicit $mode, implicit $exec + %347.sub2:vreg_128 = V_PACK_B32_F16_t16_e64 0, %343, 0, %344, 0, 0, implicit $mode, implicit $exec + %347.sub1:vreg_128 = V_PACK_B32_F16_t16_e64 0, %341, 0, %342, 0, 0, implicit $mode, implicit $exec + %347.sub0:vreg_128 = V_PACK_B32_F16_t16_e64 0, %339, 0, %340, 0, 0, implicit $mode, implicit $exec %348:vgpr_32 = V_ADD_U32_e64 -256, %324, 0, implicit $exec BUFFER_STORE_DWORDX4_OFFEN_exact %347, %348, %4, 0, 0, 0, 0, implicit $exec :: (dereferenceable store (s128), align 1, addrspace 7) %349:vgpr_32 = V_ADD_U32_e64 %312, %260.sub0, 0, implicit $exec @@ -567,18 +567,18 @@ body: | DS_WRITE2ST64_B32_gfx9 %262, %213.sub6, %213.sub7, 6, 7, 0, implicit $exec :: (store (s32), addrspace 3) %350:vreg_128 = DS_READ_B128_gfx9 %264, 0, 0, implicit $exec :: (load (s128), addrspace 3) %351:vreg_128 = DS_READ_B128_gfx9 %264, 16, 0, implicit $exec :: (load (s128), addrspace 3) - %352:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %350.sub0, 0, 0, implicit $mode, implicit $exec - %353:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %350.sub1, 0, 0, implicit $mode, implicit $exec - %354:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %350.sub2, 0, 0, implicit $mode, implicit $exec - %355:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %350.sub3, 0, 0, implicit $mode, implicit $exec - %356:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %351.sub0, 0, 0, implicit $mode, implicit $exec - %357:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %351.sub1, 0, 0, implicit $mode, implicit $exec - %358:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %351.sub2, 0, 0, implicit $mode, implicit $exec - %359:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %351.sub3, 0, 0, implicit $mode, implicit $exec - undef %360.sub3:vreg_128 = V_PACK_B32_F16_e64 0, %358, 0, %359, 0, 0, implicit $mode, implicit $exec - %360.sub2:vreg_128 = V_PACK_B32_F16_e64 0, %356, 0, %357, 0, 0, implicit $mode, implicit $exec - %360.sub1:vreg_128 = V_PACK_B32_F16_e64 0, %354, 0, %355, 0, 0, implicit $mode, implicit $exec - %360.sub0:vreg_128 = V_PACK_B32_F16_e64 0, %352, 0, %353, 0, 0, implicit $mode, implicit $exec + %352:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %350.sub0, 0, 0, 0, implicit $mode, implicit $exec + %353:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %350.sub1, 0, 0, 0, implicit $mode, implicit $exec + %354:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %350.sub2, 0, 0, 0, implicit $mode, implicit $exec + %355:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %350.sub3, 0, 0, 0, implicit $mode, implicit $exec + %356:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %351.sub0, 0, 0, 0, implicit $mode, implicit $exec + %357:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %351.sub1, 0, 0, 0, implicit $mode, implicit $exec + %358:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %351.sub2, 0, 0, 0, implicit $mode, implicit $exec + %359:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %351.sub3, 0, 0, 0, implicit $mode, implicit $exec + undef %360.sub3:vreg_128 = V_PACK_B32_F16_t16_e64 0, %358, 0, %359, 0, 0, implicit $mode, implicit $exec + %360.sub2:vreg_128 = V_PACK_B32_F16_t16_e64 0, %356, 0, %357, 0, 0, implicit $mode, implicit $exec + %360.sub1:vreg_128 = V_PACK_B32_F16_t16_e64 0, %354, 0, %355, 0, 0, implicit $mode, implicit $exec + %360.sub0:vreg_128 = V_PACK_B32_F16_t16_e64 0, %352, 0, %353, 0, 0, implicit $mode, implicit $exec %361:vgpr_32 = V_LSHLREV_B32_e64 1, %349, implicit $exec BUFFER_STORE_DWORDX4_OFFEN_exact %360, %361, %4, 0, 0, 0, 0, implicit $exec :: (dereferenceable store (s128), align 1, addrspace 7) %362:vgpr_32 = V_ADD_U32_e64 %312, %349, 0, implicit $exec @@ -588,18 +588,18 @@ body: | DS_WRITE2ST64_B32_gfx9 %262, %216.sub6, %216.sub7, 6, 7, 0, implicit $exec :: (store (s32), addrspace 3) %363:vreg_128 = DS_READ_B128_gfx9 %264, 0, 0, implicit $exec :: (load (s128), addrspace 3) %364:vreg_128 = DS_READ_B128_gfx9 %264, 16, 0, implicit $exec :: (load (s128), addrspace 3) - %365:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %363.sub0, 0, 0, implicit $mode, implicit $exec - %366:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %363.sub1, 0, 0, implicit $mode, implicit $exec - %367:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %363.sub2, 0, 0, implicit $mode, implicit $exec - %368:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %363.sub3, 0, 0, implicit $mode, implicit $exec - %369:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %364.sub0, 0, 0, implicit $mode, implicit $exec - %370:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %364.sub1, 0, 0, implicit $mode, implicit $exec - %371:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %364.sub2, 0, 0, implicit $mode, implicit $exec - %372:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %364.sub3, 0, 0, implicit $mode, implicit $exec - undef %373.sub3:vreg_128 = V_PACK_B32_F16_e64 0, %371, 0, %372, 0, 0, implicit $mode, implicit $exec - %373.sub2:vreg_128 = V_PACK_B32_F16_e64 0, %369, 0, %370, 0, 0, implicit $mode, implicit $exec - %373.sub1:vreg_128 = V_PACK_B32_F16_e64 0, %367, 0, %368, 0, 0, implicit $mode, implicit $exec - %373.sub0:vreg_128 = V_PACK_B32_F16_e64 0, %365, 0, %366, 0, 0, implicit $mode, implicit $exec + %365:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %363.sub0, 0, 0, 0, implicit $mode, implicit $exec + %366:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %363.sub1, 0, 0, 0, implicit $mode, implicit $exec + %367:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %363.sub2, 0, 0, 0, implicit $mode, implicit $exec + %368:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %363.sub3, 0, 0, 0, implicit $mode, implicit $exec + %369:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %364.sub0, 0, 0, 0, implicit $mode, implicit $exec + %370:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %364.sub1, 0, 0, 0, implicit $mode, implicit $exec + %371:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %364.sub2, 0, 0, 0, implicit $mode, implicit $exec + %372:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %364.sub3, 0, 0, 0, implicit $mode, implicit $exec + undef %373.sub3:vreg_128 = V_PACK_B32_F16_t16_e64 0, %371, 0, %372, 0, 0, implicit $mode, implicit $exec + %373.sub2:vreg_128 = V_PACK_B32_F16_t16_e64 0, %369, 0, %370, 0, 0, implicit $mode, implicit $exec + %373.sub1:vreg_128 = V_PACK_B32_F16_t16_e64 0, %367, 0, %368, 0, 0, implicit $mode, implicit $exec + %373.sub0:vreg_128 = V_PACK_B32_F16_t16_e64 0, %365, 0, %366, 0, 0, implicit $mode, implicit $exec %374:vgpr_32 = V_LSHLREV_B32_e64 1, %362, implicit $exec BUFFER_STORE_DWORDX4_OFFEN_exact %373, %374, %4, 0, 0, 0, 0, implicit $exec :: (dereferenceable store (s128), align 1, addrspace 7) DS_WRITE2ST64_B32_gfx9 %262, %248.sub0, %248.sub1, 0, 1, 0, implicit $exec :: (store (s32), addrspace 3) @@ -608,18 +608,18 @@ body: | DS_WRITE2ST64_B32_gfx9 %262, %248.sub6, %248.sub7, 6, 7, 0, implicit $exec :: (store (s32), addrspace 3) %375:vreg_128 = DS_READ_B128_gfx9 %264, 0, 0, implicit $exec :: (load (s128), addrspace 3) %376:vreg_128 = DS_READ_B128_gfx9 %264, 16, 0, implicit $exec :: (load (s128), addrspace 3) - %377:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %375.sub0, 0, 0, implicit $mode, implicit $exec - %378:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %375.sub1, 0, 0, implicit $mode, implicit $exec - %379:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %375.sub2, 0, 0, implicit $mode, implicit $exec - %380:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %375.sub3, 0, 0, implicit $mode, implicit $exec - %381:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %376.sub0, 0, 0, implicit $mode, implicit $exec - %382:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %376.sub1, 0, 0, implicit $mode, implicit $exec - %383:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %376.sub2, 0, 0, implicit $mode, implicit $exec - %384:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %376.sub3, 0, 0, implicit $mode, implicit $exec - undef %385.sub3:vreg_128 = V_PACK_B32_F16_e64 0, %383, 0, %384, 0, 0, implicit $mode, implicit $exec - %385.sub2:vreg_128 = V_PACK_B32_F16_e64 0, %381, 0, %382, 0, 0, implicit $mode, implicit $exec - %385.sub1:vreg_128 = V_PACK_B32_F16_e64 0, %379, 0, %380, 0, 0, implicit $mode, implicit $exec - %385.sub0:vreg_128 = V_PACK_B32_F16_e64 0, %377, 0, %378, 0, 0, implicit $mode, implicit $exec + %377:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %375.sub0, 0, 0, 0, implicit $mode, implicit $exec + %378:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %375.sub1, 0, 0, 0, implicit $mode, implicit $exec + %379:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %375.sub2, 0, 0, 0, implicit $mode, implicit $exec + %380:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %375.sub3, 0, 0, 0, implicit $mode, implicit $exec + %381:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %376.sub0, 0, 0, 0, implicit $mode, implicit $exec + %382:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %376.sub1, 0, 0, 0, implicit $mode, implicit $exec + %383:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %376.sub2, 0, 0, 0, implicit $mode, implicit $exec + %384:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %376.sub3, 0, 0, 0, implicit $mode, implicit $exec + undef %385.sub3:vreg_128 = V_PACK_B32_F16_t16_e64 0, %383, 0, %384, 0, 0, implicit $mode, implicit $exec + %385.sub2:vreg_128 = V_PACK_B32_F16_t16_e64 0, %381, 0, %382, 0, 0, implicit $mode, implicit $exec + %385.sub1:vreg_128 = V_PACK_B32_F16_t16_e64 0, %379, 0, %380, 0, 0, implicit $mode, implicit $exec + %385.sub0:vreg_128 = V_PACK_B32_F16_t16_e64 0, %377, 0, %378, 0, 0, implicit $mode, implicit $exec BUFFER_STORE_DWORDX4_OFFEN_exact %385, %374, %4, 0, 128, 0, 0, implicit $exec :: (dereferenceable store (s128), align 1, addrspace 7) DS_WRITE2ST64_B32_gfx9 %262, %217.sub0, %217.sub1, 0, 1, 0, implicit $exec :: (store (s32), addrspace 3) DS_WRITE2ST64_B32_gfx9 %262, %217.sub2, %217.sub3, 2, 3, 0, implicit $exec :: (store (s32), addrspace 3) @@ -627,18 +627,18 @@ body: | DS_WRITE2ST64_B32_gfx9 %262, %217.sub6, %217.sub7, 6, 7, 0, implicit $exec :: (store (s32), addrspace 3) %386:vreg_128 = DS_READ_B128_gfx9 %264, 0, 0, implicit $exec :: (load (s128), addrspace 3) %387:vreg_128 = DS_READ_B128_gfx9 %264, 16, 0, implicit $exec :: (load (s128), addrspace 3) - %388:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %386.sub0, 0, 0, implicit $mode, implicit $exec - %389:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %386.sub1, 0, 0, implicit $mode, implicit $exec - %390:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %386.sub2, 0, 0, implicit $mode, implicit $exec - %391:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %386.sub3, 0, 0, implicit $mode, implicit $exec - %392:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %387.sub0, 0, 0, implicit $mode, implicit $exec - %393:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %387.sub1, 0, 0, implicit $mode, implicit $exec - %394:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %387.sub2, 0, 0, implicit $mode, implicit $exec - %395:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %387.sub3, 0, 0, implicit $mode, implicit $exec - undef %396.sub3:vreg_128 = V_PACK_B32_F16_e64 0, %394, 0, %395, 0, 0, implicit $mode, implicit $exec - %396.sub2:vreg_128 = V_PACK_B32_F16_e64 0, %392, 0, %393, 0, 0, implicit $mode, implicit $exec - %396.sub1:vreg_128 = V_PACK_B32_F16_e64 0, %390, 0, %391, 0, 0, implicit $mode, implicit $exec - %396.sub0:vreg_128 = V_PACK_B32_F16_e64 0, %388, 0, %389, 0, 0, implicit $mode, implicit $exec + %388:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %386.sub0, 0, 0, 0, implicit $mode, implicit $exec + %389:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %386.sub1, 0, 0, 0, implicit $mode, implicit $exec + %390:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %386.sub2, 0, 0, 0, implicit $mode, implicit $exec + %391:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %386.sub3, 0, 0, 0, implicit $mode, implicit $exec + %392:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %387.sub0, 0, 0, 0, implicit $mode, implicit $exec + %393:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %387.sub1, 0, 0, 0, implicit $mode, implicit $exec + %394:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %387.sub2, 0, 0, 0, implicit $mode, implicit $exec + %395:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %387.sub3, 0, 0, 0, implicit $mode, implicit $exec + undef %396.sub3:vreg_128 = V_PACK_B32_F16_t16_e64 0, %394, 0, %395, 0, 0, implicit $mode, implicit $exec + %396.sub2:vreg_128 = V_PACK_B32_F16_t16_e64 0, %392, 0, %393, 0, 0, implicit $mode, implicit $exec + %396.sub1:vreg_128 = V_PACK_B32_F16_t16_e64 0, %390, 0, %391, 0, 0, implicit $mode, implicit $exec + %396.sub0:vreg_128 = V_PACK_B32_F16_t16_e64 0, %388, 0, %389, 0, 0, implicit $mode, implicit $exec BUFFER_STORE_DWORDX4_OFFEN_exact %396, %374, %4, 0, 256, 0, 0, implicit $exec :: (dereferenceable store (s128), align 1, addrspace 7) %397:vgpr_32 = V_ADD_U32_e64 192, %362, 0, implicit $exec DS_WRITE2ST64_B32_gfx9 %262, %251.sub0, %251.sub1, 0, 1, 0, implicit $exec :: (store (s32), addrspace 3) @@ -647,18 +647,18 @@ body: | DS_WRITE2ST64_B32_gfx9 %262, %251.sub6, %251.sub7, 6, 7, 0, implicit $exec :: (store (s32), addrspace 3) %398:vreg_128 = DS_READ_B128_gfx9 %264, 0, 0, implicit $exec :: (load (s128), addrspace 3) %399:vreg_128 = DS_READ_B128_gfx9 %264, 16, 0, implicit $exec :: (load (s128), addrspace 3) - %400:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %398.sub0, 0, 0, implicit $mode, implicit $exec - %401:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %398.sub1, 0, 0, implicit $mode, implicit $exec - %402:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %398.sub2, 0, 0, implicit $mode, implicit $exec - %403:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %398.sub3, 0, 0, implicit $mode, implicit $exec - %404:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %399.sub0, 0, 0, implicit $mode, implicit $exec - %405:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %399.sub1, 0, 0, implicit $mode, implicit $exec - %406:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %399.sub2, 0, 0, implicit $mode, implicit $exec - %407:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %399.sub3, 0, 0, implicit $mode, implicit $exec - undef %408.sub3:vreg_128 = V_PACK_B32_F16_e64 0, %406, 0, %407, 0, 0, implicit $mode, implicit $exec - %408.sub2:vreg_128 = V_PACK_B32_F16_e64 0, %404, 0, %405, 0, 0, implicit $mode, implicit $exec - %408.sub1:vreg_128 = V_PACK_B32_F16_e64 0, %402, 0, %403, 0, 0, implicit $mode, implicit $exec - %408.sub0:vreg_128 = V_PACK_B32_F16_e64 0, %400, 0, %401, 0, 0, implicit $mode, implicit $exec + %400:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %398.sub0, 0, 0, 0, implicit $mode, implicit $exec + %401:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %398.sub1, 0, 0, 0, implicit $mode, implicit $exec + %402:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %398.sub2, 0, 0, 0, implicit $mode, implicit $exec + %403:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %398.sub3, 0, 0, 0, implicit $mode, implicit $exec + %404:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %399.sub0, 0, 0, 0, implicit $mode, implicit $exec + %405:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %399.sub1, 0, 0, 0, implicit $mode, implicit $exec + %406:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %399.sub2, 0, 0, 0, implicit $mode, implicit $exec + %407:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %399.sub3, 0, 0, 0, implicit $mode, implicit $exec + undef %408.sub3:vreg_128 = V_PACK_B32_F16_t16_e64 0, %406, 0, %407, 0, 0, implicit $mode, implicit $exec + %408.sub2:vreg_128 = V_PACK_B32_F16_t16_e64 0, %404, 0, %405, 0, 0, implicit $mode, implicit $exec + %408.sub1:vreg_128 = V_PACK_B32_F16_t16_e64 0, %402, 0, %403, 0, 0, implicit $mode, implicit $exec + %408.sub0:vreg_128 = V_PACK_B32_F16_t16_e64 0, %400, 0, %401, 0, 0, implicit $mode, implicit $exec %409:vgpr_32 = V_LSHLREV_B32_e64 1, %397, implicit $exec BUFFER_STORE_DWORDX4_OFFEN_exact %408, %409, %4, 0, 0, 0, 0, implicit $exec :: (dereferenceable store (s128), align 1, addrspace 7) DS_WRITE2ST64_B32_gfx9 %262, %252.sub0, %252.sub1, 0, 1, 0, implicit $exec :: (store (s32), addrspace 3) @@ -667,18 +667,18 @@ body: | DS_WRITE2ST64_B32_gfx9 %262, %252.sub6, %252.sub7, 6, 7, 0, implicit $exec :: (store (s32), addrspace 3) %410:vreg_128 = DS_READ_B128_gfx9 %264, 0, 0, implicit $exec :: (load (s128), addrspace 3) %411:vreg_128 = DS_READ_B128_gfx9 %264, 16, 0, implicit $exec :: (load (s128), addrspace 3) - %412:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %410.sub0, 0, 0, implicit $mode, implicit $exec - %413:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %410.sub1, 0, 0, implicit $mode, implicit $exec - %414:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %410.sub2, 0, 0, implicit $mode, implicit $exec - %415:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %410.sub3, 0, 0, implicit $mode, implicit $exec - %416:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %411.sub0, 0, 0, implicit $mode, implicit $exec - %417:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %411.sub1, 0, 0, implicit $mode, implicit $exec - %418:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %411.sub2, 0, 0, implicit $mode, implicit $exec - %419:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %411.sub3, 0, 0, implicit $mode, implicit $exec - undef %420.sub3:vreg_128 = V_PACK_B32_F16_e64 0, %418, 0, %419, 0, 0, implicit $mode, implicit $exec - %420.sub2:vreg_128 = V_PACK_B32_F16_e64 0, %416, 0, %417, 0, 0, implicit $mode, implicit $exec - %420.sub1:vreg_128 = V_PACK_B32_F16_e64 0, %414, 0, %415, 0, 0, implicit $mode, implicit $exec - %420.sub0:vreg_128 = V_PACK_B32_F16_e64 0, %412, 0, %413, 0, 0, implicit $mode, implicit $exec + %412:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %410.sub0, 0, 0, 0, implicit $mode, implicit $exec + %413:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %410.sub1, 0, 0, 0, implicit $mode, implicit $exec + %414:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %410.sub2, 0, 0, 0, implicit $mode, implicit $exec + %415:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %410.sub3, 0, 0, 0, implicit $mode, implicit $exec + %416:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %411.sub0, 0, 0, 0, implicit $mode, implicit $exec + %417:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %411.sub1, 0, 0, 0, implicit $mode, implicit $exec + %418:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %411.sub2, 0, 0, 0, implicit $mode, implicit $exec + %419:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %411.sub3, 0, 0, 0, implicit $mode, implicit $exec + undef %420.sub3:vreg_128 = V_PACK_B32_F16_t16_e64 0, %418, 0, %419, 0, 0, implicit $mode, implicit $exec + %420.sub2:vreg_128 = V_PACK_B32_F16_t16_e64 0, %416, 0, %417, 0, 0, implicit $mode, implicit $exec + %420.sub1:vreg_128 = V_PACK_B32_F16_t16_e64 0, %414, 0, %415, 0, 0, implicit $mode, implicit $exec + %420.sub0:vreg_128 = V_PACK_B32_F16_t16_e64 0, %412, 0, %413, 0, 0, implicit $mode, implicit $exec %421:vgpr_32 = V_ADD_LSHL_U32_e64 %397, %312, 1, implicit $exec BUFFER_STORE_DWORDX4_OFFEN_exact %420, %421, %4, 0, 0, 0, 0, implicit $exec :: (dereferenceable store (s128), align 1, addrspace 7) DS_WRITE2ST64_B32_gfx9 %262, %220.sub0, %220.sub1, 0, 1, 0, implicit $exec :: (store (s32), addrspace 3) @@ -687,18 +687,18 @@ body: | DS_WRITE2ST64_B32_gfx9 %262, %220.sub6, %220.sub7, 6, 7, 0, implicit $exec :: (store (s32), addrspace 3) %422:vreg_128 = DS_READ_B128_gfx9 %264, 0, 0, implicit $exec :: (load (s128), addrspace 3) %423:vreg_128 = DS_READ_B128_gfx9 %264, 16, 0, implicit $exec :: (load (s128), addrspace 3) - %424:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %422.sub0, 0, 0, implicit $mode, implicit $exec - %425:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %422.sub1, 0, 0, implicit $mode, implicit $exec - %426:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %422.sub2, 0, 0, implicit $mode, implicit $exec - %427:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %422.sub3, 0, 0, implicit $mode, implicit $exec - %428:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %423.sub0, 0, 0, implicit $mode, implicit $exec - %429:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %423.sub1, 0, 0, implicit $mode, implicit $exec - %430:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %423.sub2, 0, 0, implicit $mode, implicit $exec - %431:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %423.sub3, 0, 0, implicit $mode, implicit $exec - undef %432.sub3:vreg_128 = V_PACK_B32_F16_e64 0, %430, 0, %431, 0, 0, implicit $mode, implicit $exec - %432.sub2:vreg_128 = V_PACK_B32_F16_e64 0, %428, 0, %429, 0, 0, implicit $mode, implicit $exec - %432.sub1:vreg_128 = V_PACK_B32_F16_e64 0, %426, 0, %427, 0, 0, implicit $mode, implicit $exec - %432.sub0:vreg_128 = V_PACK_B32_F16_e64 0, %424, 0, %425, 0, 0, implicit $mode, implicit $exec + %424:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %422.sub0, 0, 0, 0, implicit $mode, implicit $exec + %425:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %422.sub1, 0, 0, 0, implicit $mode, implicit $exec + %426:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %422.sub2, 0, 0, 0, implicit $mode, implicit $exec + %427:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %422.sub3, 0, 0, 0, implicit $mode, implicit $exec + %428:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %423.sub0, 0, 0, 0, implicit $mode, implicit $exec + %429:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %423.sub1, 0, 0, 0, implicit $mode, implicit $exec + %430:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %423.sub2, 0, 0, 0, implicit $mode, implicit $exec + %431:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %423.sub3, 0, 0, 0, implicit $mode, implicit $exec + undef %432.sub3:vreg_128 = V_PACK_B32_F16_t16_e64 0, %430, 0, %431, 0, 0, implicit $mode, implicit $exec + %432.sub2:vreg_128 = V_PACK_B32_F16_t16_e64 0, %428, 0, %429, 0, 0, implicit $mode, implicit $exec + %432.sub1:vreg_128 = V_PACK_B32_F16_t16_e64 0, %426, 0, %427, 0, 0, implicit $mode, implicit $exec + %432.sub0:vreg_128 = V_PACK_B32_F16_t16_e64 0, %424, 0, %425, 0, 0, implicit $mode, implicit $exec %433:vgpr_32 = V_ADD_U32_e64 -128, %421, 0, implicit $exec BUFFER_STORE_DWORDX4_OFFEN_exact %432, %433, %4, 0, 0, 0, 0, implicit $exec :: (dereferenceable store (s128), align 1, addrspace 7) DS_WRITE2ST64_B32_gfx9 %262, %249.sub0, %249.sub1, 0, 1, 0, implicit $exec :: (store (s32), addrspace 3) @@ -707,18 +707,18 @@ body: | DS_WRITE2ST64_B32_gfx9 %262, %249.sub6, %249.sub7, 6, 7, 0, implicit $exec :: (store (s32), addrspace 3) %434:vreg_128 = DS_READ_B128_gfx9 %264, 0, 0, implicit $exec :: (load (s128), addrspace 3) %435:vreg_128 = DS_READ_B128_gfx9 %264, 16, 0, implicit $exec :: (load (s128), addrspace 3) - %436:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %434.sub0, 0, 0, implicit $mode, implicit $exec - %437:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %434.sub1, 0, 0, implicit $mode, implicit $exec - %438:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %434.sub2, 0, 0, implicit $mode, implicit $exec - %439:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %434.sub3, 0, 0, implicit $mode, implicit $exec - %440:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %435.sub0, 0, 0, implicit $mode, implicit $exec - %441:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %435.sub1, 0, 0, implicit $mode, implicit $exec - %442:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %435.sub2, 0, 0, implicit $mode, implicit $exec - %443:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %435.sub3, 0, 0, implicit $mode, implicit $exec - undef %444.sub3:vreg_128 = V_PACK_B32_F16_e64 0, %442, 0, %443, 0, 0, implicit $mode, implicit $exec - %444.sub2:vreg_128 = V_PACK_B32_F16_e64 0, %440, 0, %441, 0, 0, implicit $mode, implicit $exec - %444.sub1:vreg_128 = V_PACK_B32_F16_e64 0, %438, 0, %439, 0, 0, implicit $mode, implicit $exec - %444.sub0:vreg_128 = V_PACK_B32_F16_e64 0, %436, 0, %437, 0, 0, implicit $mode, implicit $exec + %436:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %434.sub0, 0, 0, 0, implicit $mode, implicit $exec + %437:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %434.sub1, 0, 0, 0, implicit $mode, implicit $exec + %438:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %434.sub2, 0, 0, 0, implicit $mode, implicit $exec + %439:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %434.sub3, 0, 0, 0, implicit $mode, implicit $exec + %440:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %435.sub0, 0, 0, 0, implicit $mode, implicit $exec + %441:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %435.sub1, 0, 0, 0, implicit $mode, implicit $exec + %442:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %435.sub2, 0, 0, 0, implicit $mode, implicit $exec + %443:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %435.sub3, 0, 0, 0, implicit $mode, implicit $exec + undef %444.sub3:vreg_128 = V_PACK_B32_F16_t16_e64 0, %442, 0, %443, 0, 0, implicit $mode, implicit $exec + %444.sub2:vreg_128 = V_PACK_B32_F16_t16_e64 0, %440, 0, %441, 0, 0, implicit $mode, implicit $exec + %444.sub1:vreg_128 = V_PACK_B32_F16_t16_e64 0, %438, 0, %439, 0, 0, implicit $mode, implicit $exec + %444.sub0:vreg_128 = V_PACK_B32_F16_t16_e64 0, %436, 0, %437, 0, 0, implicit $mode, implicit $exec %445:vgpr_32 = V_ADD_U32_e64 -256, %421, 0, implicit $exec BUFFER_STORE_DWORDX4_OFFEN_exact %444, %445, %4, 0, 0, 0, 0, implicit $exec :: (dereferenceable store (s128), align 1, addrspace 7) DS_WRITE2ST64_B32_gfx9 %262, %219.sub0, %219.sub1, 0, 1, 0, implicit $exec :: (store (s32), addrspace 3) @@ -727,18 +727,18 @@ body: | DS_WRITE2ST64_B32_gfx9 %262, %219.sub6, %219.sub7, 6, 7, 0, implicit $exec :: (store (s32), addrspace 3) %446:vreg_128 = DS_READ_B128_gfx9 %264, 0, 0, implicit $exec :: (load (s128), addrspace 3) %447:vreg_128 = DS_READ_B128_gfx9 %264, 16, 0, implicit $exec :: (load (s128), addrspace 3) - %448:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %446.sub0, 0, 0, implicit $mode, implicit $exec - %449:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %446.sub1, 0, 0, implicit $mode, implicit $exec - %450:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %446.sub2, 0, 0, implicit $mode, implicit $exec - %451:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %446.sub3, 0, 0, implicit $mode, implicit $exec - %452:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %447.sub0, 0, 0, implicit $mode, implicit $exec - %453:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %447.sub1, 0, 0, implicit $mode, implicit $exec - %454:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %447.sub2, 0, 0, implicit $mode, implicit $exec - %455:vgpr_32 = V_CVT_F16_F32_fake16_e64 0, %447.sub3, 0, 0, implicit $mode, implicit $exec - undef %456.sub3:vreg_128 = V_PACK_B32_F16_e64 0, %454, 0, %455, 0, 0, implicit $mode, implicit $exec - %456.sub2:vreg_128 = V_PACK_B32_F16_e64 0, %452, 0, %453, 0, 0, implicit $mode, implicit $exec - %456.sub1:vreg_128 = V_PACK_B32_F16_e64 0, %450, 0, %451, 0, 0, implicit $mode, implicit $exec - %456.sub0:vreg_128 = V_PACK_B32_F16_e64 0, %448, 0, %449, 0, 0, implicit $mode, implicit $exec + %448:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %446.sub0, 0, 0, 0, implicit $mode, implicit $exec + %449:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %446.sub1, 0, 0, 0, implicit $mode, implicit $exec + %450:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %446.sub2, 0, 0, 0, implicit $mode, implicit $exec + %451:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %446.sub3, 0, 0, 0, implicit $mode, implicit $exec + %452:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %447.sub0, 0, 0, 0, implicit $mode, implicit $exec + %453:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %447.sub1, 0, 0, 0, implicit $mode, implicit $exec + %454:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %447.sub2, 0, 0, 0, implicit $mode, implicit $exec + %455:vgpr_16 = V_CVT_F16_F32_t16_e64 0, %447.sub3, 0, 0, 0, implicit $mode, implicit $exec + undef %456.sub3:vreg_128 = V_PACK_B32_F16_t16_e64 0, %454, 0, %455, 0, 0, implicit $mode, implicit $exec + %456.sub2:vreg_128 = V_PACK_B32_F16_t16_e64 0, %452, 0, %453, 0, 0, implicit $mode, implicit $exec + %456.sub1:vreg_128 = V_PACK_B32_F16_t16_e64 0, %450, 0, %451, 0, 0, implicit $mode, implicit $exec + %456.sub0:vreg_128 = V_PACK_B32_F16_t16_e64 0, %448, 0, %449, 0, 0, implicit $mode, implicit $exec %457:vgpr_32 = V_ADD_LSHL_U32_e64 %362, %312, 1, implicit $exec BUFFER_STORE_DWORDX4_OFFEN_exact %456, %457, %4, 0, 0, 0, 0, implicit $exec :: (dereferenceable store (s128), align 1, addrspace 7) S_ENDPGM 0 diff --git a/llvm/test/CodeGen/AMDGPU/shrink-fake16.mir b/llvm/test/CodeGen/AMDGPU/shrink-fake16.mir new file mode 100644 index 0000000000000..18cb086860314 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/shrink-fake16.mir @@ -0,0 +1,55 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=amdgpu11.00 -mattr=-real-true16 -run-pass=si-shrink-instructions -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX1100 %s +# RUN: llc -mtriple=amdgpu11.00 -mattr=-real-true16 -passes=si-shrink-instructions -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX1100 %s + +--- +name: 16bit_lo128_shrink +tracksRegLiveness: true +body: | + bb.0: + liveins: $vgpr127 + ; GFX1100-LABEL: name: 16bit_lo128_shrink + ; GFX1100: liveins: $vgpr127 + ; GFX1100-NEXT: {{ $}} + ; GFX1100-NEXT: V_CMP_EQ_U16_fake16_e32 0, $vgpr127, implicit-def $vcc_lo, implicit $exec, implicit $exec + $vcc_lo = V_CMP_EQ_U16_fake16_e64 0, $vgpr127, implicit-def $vcc, implicit $exec +... + +--- +name: 16bit_lo128_no_shrink +tracksRegLiveness: true +body: | + bb.0: + liveins: $vgpr128 + ; GFX1100-LABEL: name: 16bit_lo128_no_shrink + ; GFX1100: liveins: $vgpr128 + ; GFX1100-NEXT: {{ $}} + ; GFX1100-NEXT: $vcc_lo = V_CMP_EQ_U16_fake16_e64 0, $vgpr128, implicit-def $vcc_lo, implicit $exec + $vcc_lo = V_CMP_EQ_U16_fake16_e64 0, $vgpr128, implicit-def $vcc, implicit $exec +... + +--- +name: 32bit_lo128_shrink +tracksRegLiveness: true +body: | + bb.0: + liveins: $vgpr127 + ; GFX1100-LABEL: name: 32bit_lo128_shrink + ; GFX1100: liveins: $vgpr127 + ; GFX1100-NEXT: {{ $}} + ; GFX1100-NEXT: V_CMP_EQ_U16_fake16_e32 $vgpr127, $vgpr127, implicit-def $vcc_lo, implicit $exec + $vcc_lo = V_CMP_EQ_U16_fake16_e64 $vgpr127, $vgpr127, implicit $exec +... + +--- +name: 32bit_lo128_no_shrink +tracksRegLiveness: true +body: | + bb.0: + liveins: $vgpr128 + ; GFX1100-LABEL: name: 32bit_lo128_no_shrink + ; GFX1100: liveins: $vgpr128 + ; GFX1100-NEXT: {{ $}} + ; GFX1100-NEXT: $vcc_lo = V_CMP_EQ_U16_fake16_e64 $vgpr128, $vgpr128, implicit $exec + $vcc_lo = V_CMP_EQ_U16_fake16_e64 $vgpr128, $vgpr128, implicit $exec +... diff --git a/llvm/test/CodeGen/AMDGPU/shrink-true16.mir b/llvm/test/CodeGen/AMDGPU/shrink-true16.mir index 9db7969976615..a08c6eb1e290c 100644 --- a/llvm/test/CodeGen/AMDGPU/shrink-true16.mir +++ b/llvm/test/CodeGen/AMDGPU/shrink-true16.mir @@ -1,29 +1,53 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgpu11.00 -run-pass=si-shrink-instructions -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX1100 %s -# RUN: llc -mtriple=amdgpu11.00 -passes=si-shrink-instructions -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX1100 %s +# RUN: llc -march=amdgcn -mcpu=gfx1100 -mattr=+real-true16 %s -run-pass=si-shrink-instructions -verify-machineinstrs -o - | FileCheck -check-prefixes=GCN %s + + +# Should not shrink 16 bit instructions preRA +--- +name: preRA +tracksRegLiveness: true +body: | + bb.0: + + ; GCN-LABEL: name: preRA + ; GCN: [[DEF:%[0-9]+]]:vreg_128 = IMPLICIT_DEF + ; GCN-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 [[DEF]].sub1, implicit $exec + ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[DEF]].sub3 + ; GCN-NEXT: [[V_ADD_F16_t16_e64_:%[0-9]+]]:vgpr_16 = V_ADD_F16_t16_e64 0, [[V_MOV_B32_e32_]].hi16, 0, [[COPY]].lo16, 0, 0, 0, implicit $mode, implicit $exec + ; GCN-NEXT: S_ENDPGM 0, implicit [[V_ADD_F16_t16_e64_]] + %0:vreg_128 = IMPLICIT_DEF + %3:vgpr_32 = V_MOV_B32_e32 %0.sub1, implicit $exec + %4:vgpr_32 = COPY %0.sub3 + %5:vgpr_16 = V_ADD_F16_t16_e64 0, %3.hi16, 0, %4.lo16, 0, 0, 0, implicit $mode, implicit $exec + S_ENDPGM 0, implicit %5 + +... --- -name: 16bit_lo128_shrink +name: postRA tracksRegLiveness: true -body: | +body: | bb.0: - liveins: $vgpr127 - ; GFX1100-LABEL: name: 16bit_lo128_shrink - ; GFX1100: liveins: $vgpr127 - ; GFX1100-NEXT: {{ $}} - ; GFX1100-NEXT: V_CMP_EQ_U16_fake16_e32 0, $vgpr127, implicit-def $vcc_lo, implicit $exec, implicit $exec - $vcc_lo = V_CMP_EQ_U16_fake16_e64 0, $vgpr127, implicit-def $vcc, implicit $exec + ; GCN-LABEL: name: postRA + ; GCN: renamable $vgpr1 = V_MOV_B32_e32 undef $vgpr1, implicit $exec + ; GCN-NEXT: renamable $vgpr1_hi16 = V_ADD_F16_t16_e32 $vgpr1_hi16, undef $vgpr1_lo16, implicit $mode, implicit $exec + ; GCN-NEXT: S_ENDPGM 0, implicit killed renamable $vgpr1_hi16 + renamable $vgpr1 = V_MOV_B32_e32 undef $vgpr1, implicit $exec + renamable $vgpr1_hi16 = V_ADD_F16_t16_e64 0, $vgpr1_hi16, 0, undef $vgpr1_lo16, 0, 0, 0, implicit $mode, implicit $exec + S_ENDPGM 0, implicit killed renamable $vgpr1_hi16 ... +# Should not shrink 16 bit instructions if they use vgpr not addressable in 32bit encoding --- -name: 16bit_lo128_no_shrink +name: postRA_noShrink tracksRegLiveness: true -body: | +body: | bb.0: - liveins: $vgpr128 - ; GFX1100-LABEL: name: 16bit_lo128_no_shrink - ; GFX1100: liveins: $vgpr128 - ; GFX1100-NEXT: {{ $}} - ; GFX1100-NEXT: $vcc_lo = V_CMP_EQ_U16_fake16_e64 0, $vgpr128, implicit-def $vcc_lo, implicit $exec - $vcc_lo = V_CMP_EQ_U16_fake16_e64 0, $vgpr128, implicit-def $vcc, implicit $exec + ; GCN-LABEL: name: postRA_noShrink + ; GCN: renamable $vgpr1 = V_MOV_B32_e32 undef $vgpr1, implicit $exec + ; GCN-NEXT: renamable $vgpr1_hi16 = V_ADD_F16_t16_e64 0, $vgpr199_hi16, 0, undef $vgpr1_lo16, 0, 0, 0, implicit $mode, implicit $exec + ; GCN-NEXT: S_ENDPGM 0, implicit killed renamable $vgpr1_hi16 + renamable $vgpr1 = V_MOV_B32_e32 undef $vgpr1, implicit $exec + renamable $vgpr1_hi16 = V_ADD_F16_t16_e64 0, $vgpr199_hi16, 0, undef $vgpr1_lo16, 0, 0, 0, implicit $mode, implicit $exec + S_ENDPGM 0, implicit killed renamable $vgpr1_hi16 ... diff --git a/llvm/test/CodeGen/AMDGPU/v_swap_b16.mir b/llvm/test/CodeGen/AMDGPU/v_swap_b16.mir new file mode 100644 index 0000000000000..65d7cdc8dc874 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/v_swap_b16.mir @@ -0,0 +1,409 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6 +# RUN: llc -simplify-mir -march=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -run-pass=si-shrink-instructions -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s +# RUN: llc -simplify-mir -march=amdgcn -mcpu=gfx1200 -mattr=+real-true16 -run-pass=si-shrink-instructions -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s + +--- +name: swap_phys_condensed +tracksRegLiveness: true +body: | + bb.0: + liveins: $vgpr0_lo16, $vgpr1_hi16, $sgpr30_sgpr31 + ; GCN-LABEL: name: swap_phys_condensed + ; GCN: liveins: $vgpr0_lo16, $vgpr1_hi16, $sgpr30_sgpr31 + ; GCN-NEXT: {{ $}} + ; GCN-NEXT: $vgpr2_lo16 = V_MOV_B16_t16_e32 $vgpr0_lo16, implicit $exec + ; GCN-NEXT: $vgpr0_lo16, $vgpr1_hi16 = V_SWAP_B16 $vgpr1_hi16, $vgpr0_lo16, implicit $exec + ; GCN-NEXT: S_SETPC_B64_return $sgpr30_sgpr31, implicit $vgpr0_lo16, implicit $vgpr1_hi16 + $vgpr2_lo16 = V_MOV_B16_t16_e32 killed $vgpr0_lo16, implicit $exec + $vgpr0_lo16 = V_MOV_B16_t16_e32 killed $vgpr1_hi16, implicit $exec + $vgpr1_hi16 = V_MOV_B16_t16_e32 killed $vgpr2_lo16, implicit $exec + S_SETPC_B64_return $sgpr30_sgpr31, implicit $vgpr0_lo16, implicit $vgpr1_hi16 +... + + +--- +name: swap_phys_sparse +tracksRegLiveness: true +body: | + bb.0: + liveins: $vgpr0_lo16, $vgpr1_hi16, $vgpr4_lo16, $vgpr6_lo16, $sgpr30_sgpr31 + ; GCN-LABEL: name: swap_phys_sparse + ; GCN: liveins: $vgpr0_lo16, $vgpr1_hi16, $vgpr4_lo16, $vgpr6_lo16, $sgpr30_sgpr31 + ; GCN-NEXT: {{ $}} + ; GCN-NEXT: $vgpr2_lo16 = V_MOV_B16_t16_e32 $vgpr0_lo16, implicit $exec + ; GCN-NEXT: $vgpr3_hi16 = V_MOV_B16_t16_e32 killed $vgpr4_lo16, implicit $exec + ; GCN-NEXT: $vgpr5_hi16 = V_MOV_B16_t16_e32 killed $vgpr6_lo16, implicit $exec + ; GCN-NEXT: $vgpr0_lo16, $vgpr1_hi16 = V_SWAP_B16 $vgpr1_hi16, $vgpr0_lo16, implicit $exec + ; GCN-NEXT: S_SETPC_B64_return $sgpr30_sgpr31, implicit $vgpr0_lo16, implicit $vgpr1_hi16 + $vgpr2_lo16 = V_MOV_B16_t16_e32 killed $vgpr0_lo16, implicit $exec + $vgpr3_hi16 = V_MOV_B16_t16_e32 killed $vgpr4_lo16, implicit $exec + $vgpr0_lo16 = V_MOV_B16_t16_e32 killed $vgpr1_hi16, implicit $exec + $vgpr5_hi16 = V_MOV_B16_t16_e32 killed $vgpr6_lo16, implicit $exec + $vgpr1_hi16 = V_MOV_B16_t16_e32 killed $vgpr2_lo16, implicit $exec + S_SETPC_B64_return $sgpr30_sgpr31, implicit $vgpr0_lo16, implicit $vgpr1_hi16 +... + +--- +name: swap_phys_liveout +tracksRegLiveness: true +body: | + bb.0: + liveins: $vgpr0_lo16, $vgpr1_hi16, $sgpr30_sgpr31 + ; GCN-LABEL: name: swap_phys_liveout + ; GCN: liveins: $vgpr0_lo16, $vgpr1_hi16, $sgpr30_sgpr31 + ; GCN-NEXT: {{ $}} + ; GCN-NEXT: $vgpr2_lo16 = V_MOV_B16_t16_e32 $vgpr0_lo16, implicit $exec + ; GCN-NEXT: $vgpr0_lo16, $vgpr1_hi16 = V_SWAP_B16 $vgpr1_hi16, $vgpr0_lo16, implicit $exec + ; GCN-NEXT: S_SETPC_B64_return $sgpr30_sgpr31, implicit $vgpr0_lo16, implicit $vgpr1_hi16 + $vgpr2_lo16 = V_MOV_B16_t16_e32 killed $vgpr0_lo16, implicit $exec + $vgpr0_lo16 = V_MOV_B16_t16_e32 killed $vgpr1_hi16, implicit $exec + $vgpr1_hi16 = V_MOV_B16_t16_e32 killed $vgpr2_lo16, implicit $exec + S_SETPC_B64_return $sgpr30_sgpr31, implicit $vgpr0_lo16, implicit $vgpr1_hi16 +... + +--- +name: swap_phys_liveout_superreg +tracksRegLiveness: true +body: | + bb.0: + liveins: $vgpr0_lo16, $vgpr1_hi16, $sgpr30_sgpr31 + ; GCN-LABEL: name: swap_phys_liveout_superreg + ; GCN: liveins: $vgpr0_lo16, $vgpr1_hi16, $sgpr30_sgpr31 + ; GCN-NEXT: {{ $}} + ; GCN-NEXT: $vgpr2_lo16 = V_MOV_B16_t16_e32 $vgpr0_lo16, implicit $exec + ; GCN-NEXT: $vgpr0_lo16, $vgpr1_hi16 = V_SWAP_B16 $vgpr1_hi16, $vgpr0_lo16, implicit $exec + ; GCN-NEXT: S_SETPC_B64_return $sgpr30_sgpr31, implicit $vgpr0_lo16, implicit $vgpr1_hi16 + $vgpr2_lo16 = V_MOV_B16_t16_e32 killed $vgpr0_lo16, implicit $exec + $vgpr0_lo16 = V_MOV_B16_t16_e32 killed $vgpr1_hi16, implicit $exec + $vgpr1_hi16 = V_MOV_B16_t16_e32 killed $vgpr2_lo16, implicit $exec + S_SETPC_B64_return $sgpr30_sgpr31, implicit $vgpr0_lo16, implicit $vgpr1_hi16 +... + + +--- +name: swap_phys_overlap_x +tracksRegLiveness: true +body: | + bb.0: + liveins: $vgpr0_vgpr1, $vgpr3_vgpr4 + ; GCN-LABEL: name: swap_phys_overlap_x + ; GCN: liveins: $vgpr0_vgpr1, $vgpr3_vgpr4 + ; GCN-NEXT: {{ $}} + ; GCN-NEXT: $vgpr2_lo16 = V_MOV_B16_t16_e32 $vgpr0_lo16, implicit $exec + ; GCN-NEXT: $vgpr3_vgpr4 = V_ADD_F64_e64 0, $vgpr0_vgpr1, 0, $vgpr3_vgpr4, 0, 0, implicit $mode, implicit $exec + ; GCN-NEXT: $vgpr0_lo16, $vgpr1_hi16 = V_SWAP_B16 $vgpr1_hi16, $vgpr0_lo16, implicit $exec + $vgpr2_lo16 = V_MOV_B16_t16_e32 $vgpr0_lo16, implicit $exec + $vgpr3_vgpr4 = V_ADD_F64_e64 0, $vgpr0_vgpr1, 0, $vgpr3_vgpr4, 0, 0, implicit $mode, implicit $exec + $vgpr0_lo16 = V_MOV_B16_t16_e32 killed $vgpr1_hi16, implicit $exec + $vgpr1_hi16 = V_MOV_B16_t16_e32 killed $vgpr2_lo16, implicit $exec +... + +--- +name: swap_phys_clobber_y +tracksRegLiveness: true +body: | + bb.0: + liveins: $vgpr0_lo16, $vgpr1_hi16 + ; GCN-LABEL: name: swap_phys_clobber_y + ; GCN: liveins: $vgpr0_lo16, $vgpr1_hi16 + ; GCN-NEXT: {{ $}} + ; GCN-NEXT: $vgpr2_lo16 = V_MOV_B16_t16_e32 $vgpr0_lo16, implicit $exec + ; GCN-NEXT: $vgpr0_lo16 = V_MOV_B16_t16_e32 killed $vgpr1_hi16, implicit $exec + ; GCN-NEXT: $vgpr1_hi16 = V_MOV_B16_t16_e32 0, implicit $exec + ; GCN-NEXT: $vgpr1_hi16 = V_MOV_B16_t16_e32 killed $vgpr2_lo16, implicit $exec + ; GCN-NEXT: S_ENDPGM 0 + $vgpr2_lo16 = V_MOV_B16_t16_e32 $vgpr0_lo16, implicit $exec + $vgpr0_lo16 = V_MOV_B16_t16_e32 killed $vgpr1_hi16, implicit $exec + $vgpr1_hi16 = V_MOV_B16_t16_e32 0, implicit $exec + $vgpr1_hi16 = V_MOV_B16_t16_e32 killed $vgpr2_lo16, implicit $exec + S_ENDPGM 0 +... + +--- +name: swap_virt_copy_vgpr_16 +tracksRegLiveness: true +registers: + - { id: 0, class: vgpr_16 } + - { id: 1, class: vgpr_16 } + - { id: 2, class: vgpr_16 } +body: | + bb.0: + ; GCN-LABEL: name: swap_virt_copy_vgpr_16 + ; GCN: [[DEF:%[0-9]+]]:vgpr_16 = IMPLICIT_DEF + ; GCN-NEXT: [[DEF1:%[0-9]+]]:vgpr_16 = IMPLICIT_DEF + ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_16 = COPY [[DEF]] + ; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_16 = COPY [[DEF1]] + ; GCN-NEXT: [[DEF1:%[0-9]+]]:vgpr_16 = COPY [[COPY]] + %0 = IMPLICIT_DEF + %1 = IMPLICIT_DEF + %2 = COPY %0 + %0 = COPY %1 + %1 = COPY %2 +... + +--- +name: swap_exact_max_insns_apart +tracksRegLiveness: true +body: | + bb.0: + ; GCN-LABEL: name: swap_exact_max_insns_apart + ; GCN: $vgpr0_lo16 = IMPLICIT_DEF + ; GCN-NEXT: $vgpr1_hi16 = IMPLICIT_DEF + ; GCN-NEXT: $vgpr2_lo16 = COPY $vgpr0_lo16 + ; GCN-NEXT: $vgpr3_hi16 = IMPLICIT_DEF + ; GCN-NEXT: $vgpr4_lo16 = COPY $vgpr3_hi16 + ; GCN-NEXT: $vgpr3_hi16 = COPY $vgpr4_lo16 + ; GCN-NEXT: $vgpr4_lo16 = COPY $vgpr3_hi16 + ; GCN-NEXT: $vgpr3_hi16 = COPY $vgpr4_lo16 + ; GCN-NEXT: $vgpr4_lo16 = COPY $vgpr3_hi16 + ; GCN-NEXT: $vgpr3_hi16 = COPY $vgpr4_lo16 + ; GCN-NEXT: $vgpr4_lo16 = COPY $vgpr3_hi16 + ; GCN-NEXT: $vgpr3_hi16 = COPY $vgpr4_lo16 + ; GCN-NEXT: $vgpr4_lo16 = COPY $vgpr3_hi16 + ; GCN-NEXT: $vgpr3_hi16 = COPY $vgpr4_lo16 + ; GCN-NEXT: $vgpr4_lo16 = COPY $vgpr3_hi16 + ; GCN-NEXT: $vgpr3_hi16 = COPY $vgpr4_lo16 + ; GCN-NEXT: $vgpr4_lo16 = COPY $vgpr3_hi16 + ; GCN-NEXT: $vgpr0_lo16, $vgpr1_hi16 = V_SWAP_B16 $vgpr1_hi16, $vgpr0_lo16, implicit $exec + ; GCN-NEXT: S_ENDPGM 0 + $vgpr0_lo16 = IMPLICIT_DEF + $vgpr1_hi16 = IMPLICIT_DEF + $vgpr2_lo16 = COPY $vgpr0_lo16 + $vgpr3_hi16 = IMPLICIT_DEF + $vgpr4_lo16 = COPY $vgpr3_hi16 + $vgpr3_hi16 = COPY $vgpr4_lo16 + $vgpr4_lo16 = COPY $vgpr3_hi16 + $vgpr3_hi16 = COPY $vgpr4_lo16 + $vgpr4_lo16 = COPY $vgpr3_hi16 + $vgpr3_hi16 = COPY $vgpr4_lo16 + $vgpr4_lo16 = COPY $vgpr3_hi16 + $vgpr3_hi16 = COPY $vgpr4_lo16 + $vgpr4_lo16 = COPY $vgpr3_hi16 + $vgpr3_hi16 = COPY $vgpr4_lo16 + $vgpr4_lo16 = COPY $vgpr3_hi16 + $vgpr3_hi16 = COPY $vgpr4_lo16 + $vgpr4_lo16 = COPY $vgpr3_hi16 + $vgpr0_lo16 = COPY $vgpr1_hi16 + $vgpr1_hi16 = COPY $vgpr2_lo16 + S_ENDPGM 0 +... + +--- +name: swap_too_far +tracksRegLiveness: true +body: | + bb.0: + ; GCN-LABEL: name: swap_too_far + ; GCN: $vgpr0_lo16 = IMPLICIT_DEF + ; GCN-NEXT: $vgpr1_hi16 = IMPLICIT_DEF + ; GCN-NEXT: $vgpr2_lo16 = COPY $vgpr0_lo16 + ; GCN-NEXT: $vgpr3_hi16 = IMPLICIT_DEF + ; GCN-NEXT: $vgpr4_lo16 = COPY $vgpr3_hi16 + ; GCN-NEXT: $vgpr3_hi16 = COPY $vgpr4_lo16 + ; GCN-NEXT: $vgpr4_lo16 = COPY $vgpr3_hi16 + ; GCN-NEXT: $vgpr3_hi16 = COPY $vgpr4_lo16 + ; GCN-NEXT: $vgpr4_lo16 = COPY $vgpr3_hi16 + ; GCN-NEXT: $vgpr3_hi16 = COPY $vgpr4_lo16 + ; GCN-NEXT: $vgpr4_lo16 = COPY $vgpr3_hi16 + ; GCN-NEXT: $vgpr3_hi16 = COPY $vgpr4_lo16 + ; GCN-NEXT: $vgpr4_lo16 = COPY $vgpr3_hi16 + ; GCN-NEXT: $vgpr3_hi16 = COPY $vgpr4_lo16 + ; GCN-NEXT: $vgpr4_lo16 = COPY $vgpr3_hi16 + ; GCN-NEXT: $vgpr3_hi16 = COPY $vgpr4_lo16 + ; GCN-NEXT: $vgpr4_lo16 = COPY $vgpr3_hi16 + ; GCN-NEXT: $vgpr3_hi16 = COPY $vgpr4_lo16 + ; GCN-NEXT: $vgpr0_lo16 = COPY $vgpr1_hi16 + ; GCN-NEXT: $vgpr1_hi16 = COPY $vgpr2_lo16 + ; GCN-NEXT: S_ENDPGM 0 + $vgpr0_lo16 = IMPLICIT_DEF + $vgpr1_hi16 = IMPLICIT_DEF + $vgpr2_lo16 = COPY $vgpr0_lo16 + $vgpr3_hi16 = IMPLICIT_DEF + $vgpr4_lo16 = COPY $vgpr3_hi16 + $vgpr3_hi16 = COPY $vgpr4_lo16 + $vgpr4_lo16 = COPY $vgpr3_hi16 + $vgpr3_hi16 = COPY $vgpr4_lo16 + $vgpr4_lo16 = COPY $vgpr3_hi16 + $vgpr3_hi16 = COPY $vgpr4_lo16 + $vgpr4_lo16 = COPY $vgpr3_hi16 + $vgpr3_hi16 = COPY $vgpr4_lo16 + $vgpr4_lo16 = COPY $vgpr3_hi16 + $vgpr3_hi16 = COPY $vgpr4_lo16 + $vgpr4_lo16 = COPY $vgpr3_hi16 + $vgpr3_hi16 = COPY $vgpr4_lo16 + $vgpr4_lo16 = COPY $vgpr3_hi16 + $vgpr3_hi16 = COPY $vgpr4_lo16 + $vgpr0_lo16 = COPY $vgpr1_hi16 + $vgpr1_hi16 = COPY $vgpr2_lo16 + S_ENDPGM 0 +... + +--- +name: swap_liveness_error_mov +tracksRegLiveness: true +body: | + bb.0: + liveins: $vgpr5_hi16, $vgpr1_vgpr2 + ; GCN-LABEL: name: swap_liveness_error_mov + ; GCN: liveins: $vgpr5_hi16, $vgpr1_vgpr2 + ; GCN-NEXT: {{ $}} + ; GCN-NEXT: $vgpr6_lo16 = V_MOV_B16_t16_e32 $vgpr1_hi16, implicit $exec + ; GCN-NEXT: $vgpr1_hi16, $vgpr5_hi16 = V_SWAP_B16 $vgpr5_hi16, $vgpr1_hi16, implicit $exec + ; GCN-NEXT: $vgpr5_vgpr6 = IMPLICIT_DEF + ; GCN-NEXT: $vgpr6_lo16 = V_MOV_B16_t16_e32 $vgpr7_hi16, implicit $exec, implicit $vgpr6_vgpr7 + ; GCN-NEXT: $vgpr5_hi16 = V_MOV_B16_t16_e32 $vgpr6_lo16, implicit $exec + ; GCN-NEXT: S_ENDPGM 0 + $vgpr6_lo16 = V_MOV_B16_t16_e32 $vgpr1_hi16, implicit $exec, implicit killed $vgpr1_vgpr2 + $vgpr1_hi16 = V_MOV_B16_t16_e32 killed $vgpr5_hi16, implicit $exec + $vgpr5_hi16 = V_MOV_B16_t16_e32 $vgpr6_lo16, implicit $exec, implicit-def $vgpr5_vgpr6, implicit $vgpr6_vgpr7 + $vgpr6_lo16 = V_MOV_B16_t16_e32 $vgpr7_hi16, implicit $exec, implicit $vgpr6_vgpr7 + $vgpr5_hi16 = V_MOV_B16_t16_e32 $vgpr6_lo16, implicit $exec + S_ENDPGM 0 +... + +--- +name: swap_liveness_error_copy +tracksRegLiveness: true +body: | + bb.0: + liveins: $vgpr5_hi16, $vgpr1_vgpr2 + ; GCN-LABEL: name: swap_liveness_error_copy + ; GCN: liveins: $vgpr5_hi16, $vgpr1_vgpr2 + ; GCN-NEXT: {{ $}} + ; GCN-NEXT: $vgpr6_lo16 = COPY $vgpr1_hi16 + ; GCN-NEXT: $vgpr1_hi16, $vgpr5_hi16 = V_SWAP_B16 $vgpr5_hi16, $vgpr1_hi16, implicit $exec + ; GCN-NEXT: $vgpr5_vgpr6 = IMPLICIT_DEF + ; GCN-NEXT: $vgpr6_lo16 = COPY $vgpr7, implicit $vgpr6_vgpr7 + ; GCN-NEXT: $vgpr5_hi16 = COPY $vgpr6_lo16 + ; GCN-NEXT: S_ENDPGM 0 + $vgpr6_lo16 = COPY $vgpr1_hi16, implicit killed $vgpr1_vgpr2 + $vgpr1_hi16 = COPY killed $vgpr5_hi16 + $vgpr5_hi16 = COPY $vgpr6_lo16, implicit-def $vgpr5_vgpr6, implicit $vgpr6_vgpr7 + $vgpr6_lo16 = COPY $vgpr7, implicit $vgpr6_vgpr7 + $vgpr5_hi16 = COPY $vgpr6_lo16 + S_ENDPGM 0 +... + + +--- +name: swap_killed_t_early +tracksRegLiveness: true +body: | + bb.0: + liveins: $vgpr0_lo16, $vgpr1_hi16, $vgpr4_lo16, $vgpr6_lo16, $sgpr30_sgpr31 + ; GCN-LABEL: name: swap_killed_t_early + ; GCN: liveins: $vgpr0_lo16, $vgpr1_hi16, $vgpr4_lo16, $vgpr6_lo16, $sgpr30_sgpr31 + ; GCN-NEXT: {{ $}} + ; GCN-NEXT: $vgpr2_lo16 = V_MOV_B16_t16_e32 $vgpr0_lo16, implicit $exec + ; GCN-NEXT: $vgpr3_hi16 = V_MOV_B16_t16_e32 killed $vgpr4_lo16, implicit $exec, implicit killed $vgpr2_lo16 + ; GCN-NEXT: $vgpr5_hi16 = V_MOV_B16_t16_e32 killed $vgpr6_lo16, implicit $exec + ; GCN-NEXT: $vgpr0_lo16, $vgpr1_hi16 = V_SWAP_B16 $vgpr1_hi16, $vgpr0_lo16, implicit $exec + ; GCN-NEXT: S_SETPC_B64_return $sgpr30_sgpr31, implicit $vgpr0_lo16, implicit $vgpr1_hi16 + $vgpr2_lo16 = V_MOV_B16_t16_e32 killed $vgpr0_lo16, implicit $exec + $vgpr3_hi16 = V_MOV_B16_t16_e32 killed $vgpr4_lo16, implicit $exec, implicit killed $vgpr2_lo16 + $vgpr0_lo16 = V_MOV_B16_t16_e32 killed $vgpr1_hi16, implicit $exec + $vgpr5_hi16 = V_MOV_B16_t16_e32 killed $vgpr6_lo16, implicit $exec + $vgpr1_hi16 = V_MOV_B16_t16_e32 undef $vgpr2_lo16, implicit $exec + S_SETPC_B64_return $sgpr30_sgpr31, implicit $vgpr0_lo16, implicit $vgpr1_hi16 +... + + +--- +name: swap_killed_t_late +tracksRegLiveness: true +body: | + bb.0: + liveins: $vgpr0_lo16, $vgpr1_hi16, $vgpr4_lo16, $vgpr6_lo16, $sgpr30_sgpr31 + ; GCN-LABEL: name: swap_killed_t_late + ; GCN: liveins: $vgpr0_lo16, $vgpr1_hi16, $vgpr4_lo16, $vgpr6_lo16, $sgpr30_sgpr31 + ; GCN-NEXT: {{ $}} + ; GCN-NEXT: $vgpr2_lo16 = V_MOV_B16_t16_e32 $vgpr0_lo16, implicit $exec + ; GCN-NEXT: $vgpr3_hi16 = V_MOV_B16_t16_e32 killed $vgpr4_lo16, implicit $exec + ; GCN-NEXT: $vgpr5_hi16 = V_MOV_B16_t16_e32 killed $vgpr6_lo16, implicit $exec, implicit killed $vgpr2_lo16 + ; GCN-NEXT: $vgpr0_lo16, $vgpr1_hi16 = V_SWAP_B16 $vgpr1_hi16, $vgpr0_lo16, implicit $exec + ; GCN-NEXT: S_SETPC_B64_return $sgpr30_sgpr31, implicit $vgpr0_lo16, implicit $vgpr1_hi16 + $vgpr2_lo16 = V_MOV_B16_t16_e32 killed $vgpr0_lo16, implicit $exec + $vgpr3_hi16 = V_MOV_B16_t16_e32 killed $vgpr4_lo16, implicit $exec + $vgpr0_lo16 = V_MOV_B16_t16_e32 killed $vgpr1_hi16, implicit $exec + $vgpr5_hi16 = V_MOV_B16_t16_e32 killed $vgpr6_lo16, implicit $exec, implicit killed $vgpr2_lo16 + $vgpr1_hi16 = V_MOV_B16_t16_e32 undef $vgpr2_lo16, implicit $exec + S_SETPC_B64_return $sgpr30_sgpr31, implicit $vgpr0_lo16, implicit $vgpr1_hi16 +... + +--- +name: swap_killed_x +tracksRegLiveness: true +body: | + bb.0: + liveins: $vgpr0_lo16, $vgpr1_hi16, $vgpr4_lo16, $vgpr6_lo16, $sgpr30_sgpr31 + ; GCN-LABEL: name: swap_killed_x + ; GCN: liveins: $vgpr0_lo16, $vgpr1_hi16, $vgpr4_lo16, $vgpr6_lo16, $sgpr30_sgpr31 + ; GCN-NEXT: {{ $}} + ; GCN-NEXT: $vgpr2_lo16 = V_MOV_B16_t16_e32 $vgpr0_lo16, implicit $exec + ; GCN-NEXT: $vgpr3_hi16 = V_MOV_B16_t16_e32 killed $vgpr4_lo16, implicit $exec + ; GCN-NEXT: $vgpr0_lo16, $vgpr1_hi16 = V_SWAP_B16 $vgpr1_hi16, $vgpr0_lo16, implicit $exec + ; GCN-NEXT: $vgpr5_hi16 = V_MOV_B16_t16_e32 killed $vgpr6_lo16, implicit $exec, implicit killed $vgpr0_lo16 + ; GCN-NEXT: S_SETPC_B64_return $sgpr30_sgpr31, implicit $vgpr1_hi16 + $vgpr2_lo16 = V_MOV_B16_t16_e32 killed $vgpr0_lo16, implicit $exec + $vgpr3_hi16 = V_MOV_B16_t16_e32 killed $vgpr4_lo16, implicit $exec + $vgpr0_lo16 = V_MOV_B16_t16_e32 killed $vgpr1_hi16, implicit $exec + $vgpr5_hi16 = V_MOV_B16_t16_e32 killed $vgpr6_lo16, implicit $exec, implicit killed $vgpr0_lo16 + $vgpr1_hi16 = V_MOV_B16_t16_e32 killed $vgpr2_lo16, implicit $exec + S_SETPC_B64_return $sgpr30_sgpr31, implicit $vgpr1_hi16 +... + +--- +name: implicit_ops_mov_x_swap_b16 +tracksRegLiveness: true +body: | + bb.0: + liveins: $vgpr0_lo16, $vgpr1_hi16, $sgpr30_sgpr31 + ; GCN-LABEL: name: implicit_ops_mov_x_swap_b16 + ; GCN: liveins: $vgpr0_lo16, $vgpr1_hi16, $sgpr30_sgpr31 + ; GCN-NEXT: {{ $}} + ; GCN-NEXT: $vgpr3_hi16 = V_MOV_B16_t16_e32 $vgpr0_lo16, implicit $exec + ; GCN-NEXT: $vgpr0_lo16, $vgpr1_hi16 = V_SWAP_B16 $vgpr1_hi16, $vgpr0_lo16, implicit $exec, implicit $vgpr2_lo16, implicit killed $vgpr1_vgpr2 + ; GCN-NEXT: S_SETPC_B64_return $sgpr30_sgpr31, implicit $vgpr0_lo16, implicit $vgpr1_hi16 + $vgpr3_hi16 = V_MOV_B16_t16_e32 killed $vgpr0_lo16, implicit $exec + $vgpr0_lo16 = V_MOV_B16_t16_e32 $vgpr1_hi16, implicit $exec, implicit $vgpr2_lo16, implicit killed $vgpr1_vgpr2 + $vgpr1_hi16 = V_MOV_B16_t16_e32 killed $vgpr3_hi16, implicit $exec + S_SETPC_B64_return $sgpr30_sgpr31, implicit $vgpr0_lo16, implicit $vgpr1_hi16 +... + + +--- +name: implicit_ops_mov_t_swap_b16 +tracksRegLiveness: true +body: | + bb.0: + liveins: $vgpr0_lo16, $vgpr1_hi16, $sgpr30_sgpr31 + ; GCN-LABEL: name: implicit_ops_mov_t_swap_b16 + ; GCN: liveins: $vgpr0_lo16, $vgpr1_hi16, $sgpr30_sgpr31 + ; GCN-NEXT: {{ $}} + ; GCN-NEXT: $vgpr3_hi16 = V_MOV_B16_t16_e32 $vgpr0_lo16, implicit $exec, implicit $vgpr2_lo16, implicit killed $vgpr1_vgpr2, implicit-def $vgpr1_hi16 + ; GCN-NEXT: $vgpr0_lo16, $vgpr1_hi16 = V_SWAP_B16 $vgpr1_hi16, $vgpr0_lo16, implicit $exec + ; GCN-NEXT: S_SETPC_B64_return $sgpr30_sgpr31, implicit $vgpr0_lo16, implicit $vgpr1_hi16 + $vgpr3_hi16 = V_MOV_B16_t16_e32 killed $vgpr0_lo16, implicit $exec, implicit $vgpr2_lo16, implicit killed $vgpr1_vgpr2, implicit-def $vgpr1_hi16 + $vgpr0_lo16 = V_MOV_B16_t16_e32 $vgpr1_hi16, implicit $exec + $vgpr1_hi16 = V_MOV_B16_t16_e32 killed $vgpr3_hi16, implicit $exec + S_SETPC_B64_return $sgpr30_sgpr31, implicit $vgpr0_lo16, implicit $vgpr1_hi16 +... + +--- +name: implicit_ops_mov_y_swap_b16 +tracksRegLiveness: true +body: | + bb.0: + liveins: $vgpr0_lo16, $vgpr1_hi16, $vgpr2_lo16, $sgpr30_sgpr31 + ; GCN-LABEL: name: implicit_ops_mov_y_swap_b16 + ; GCN: liveins: $vgpr0_lo16, $vgpr1_hi16, $vgpr2_lo16, $sgpr30_sgpr31 + ; GCN-NEXT: {{ $}} + ; GCN-NEXT: $vgpr3_hi16 = V_MOV_B16_t16_e32 $vgpr0_lo16, implicit $exec + ; GCN-NEXT: $vgpr0_lo16, $vgpr1_hi16 = V_SWAP_B16 $vgpr1_hi16, $vgpr0_lo16, implicit $exec + ; GCN-NEXT: $vgpr0_vgpr1 = IMPLICIT_DEF + ; GCN-NEXT: S_SETPC_B64_return $sgpr30_sgpr31, implicit $vgpr0_lo16, implicit $vgpr1_hi16 + $vgpr3_hi16 = V_MOV_B16_t16_e32 killed $vgpr0_lo16, implicit $exec + $vgpr0_lo16 = V_MOV_B16_t16_e32 $vgpr1_hi16, implicit $exec + $vgpr1_hi16 = V_MOV_B16_t16_e32 killed $vgpr3_hi16, implicit $exec, implicit $vgpr2_lo16, implicit-def $vgpr0_vgpr1, implicit killed $vgpr3_hi16 + S_SETPC_B64_return $sgpr30_sgpr31, implicit $vgpr0_lo16, implicit $vgpr1_hi16 +... diff --git a/llvm/test/CodeGen/AMDGPU/waitcnt-vinterp-fake16.mir b/llvm/test/CodeGen/AMDGPU/waitcnt-vinterp-fake16.mir new file mode 100644 index 0000000000000..b002f42afe7c5 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/waitcnt-vinterp-fake16.mir @@ -0,0 +1,30 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=amdgpu11.00 -mattr=-real-true16 -verify-machineinstrs -run-pass si-insert-waitcnts -o - %s | FileCheck -check-prefix=GFX11 %s + +--- +name: waitcnt-vinterp +machineFunctionInfo: + isEntryFunction: true +body: | + bb.0: + liveins: $vgpr0 + ; GFX11-LABEL: name: waitcnt-vinterp + ; GFX11: liveins: $vgpr0 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: $vgpr1 = LDS_PARAM_LOAD 0, 0, 0, implicit $m0, implicit $exec + ; GFX11-NEXT: $vgpr2 = LDS_PARAM_LOAD 0, 1, 0, implicit $m0, implicit $exec + ; GFX11-NEXT: $vgpr3 = LDS_PARAM_LOAD 0, 2, 0, implicit $m0, implicit $exec + ; GFX11-NEXT: $vgpr4 = LDS_PARAM_LOAD 0, 3, 0, implicit $m0, implicit $exec + ; GFX11-NEXT: $vgpr5 = V_INTERP_P10_F16_F32_inreg_fake16 0, $vgpr1, 0, $vgpr0, 0, $vgpr1, 0, 0, 2, implicit $m0, implicit $exec, implicit $mode + ; GFX11-NEXT: $vgpr6 = V_INTERP_P10_F16_F32_inreg_fake16 0, $vgpr2, 0, $vgpr0, 0, $vgpr2, 0, 0, 2, implicit $m0, implicit $exec, implicit $mode + ; GFX11-NEXT: $vgpr7 = V_INTERP_P10_F16_F32_inreg_fake16 0, $vgpr3, 0, $vgpr0, 0, $vgpr3, 0, 0, 1, implicit $m0, implicit $exec, implicit $mode + ; GFX11-NEXT: $vgpr8 = V_INTERP_P10_F16_F32_inreg_fake16 0, $vgpr4, 0, $vgpr0, 0, $vgpr4, 0, 0, 0, implicit $m0, implicit $exec, implicit $mode + $vgpr1 = LDS_PARAM_LOAD 0, 0, 0, implicit $m0, implicit $exec + $vgpr2 = LDS_PARAM_LOAD 0, 1, 0, implicit $m0, implicit $exec + $vgpr3 = LDS_PARAM_LOAD 0, 2, 0, implicit $m0, implicit $exec + $vgpr4 = LDS_PARAM_LOAD 0, 3, 0, implicit $m0, implicit $exec + $vgpr5 = V_INTERP_P10_F16_F32_inreg_fake16 0, $vgpr1, 0, $vgpr0, 0, $vgpr1, 0, 0, 2, implicit $m0, implicit $exec, implicit $mode + $vgpr6 = V_INTERP_P10_F16_F32_inreg_fake16 0, $vgpr2, 0, $vgpr0, 0, $vgpr2, 0, 0, 2, implicit $m0, implicit $exec, implicit $mode + $vgpr7 = V_INTERP_P10_F16_F32_inreg_fake16 0, $vgpr3, 0, $vgpr0, 0, $vgpr3, 0, 0, 2, implicit $m0, implicit $exec, implicit $mode + $vgpr8 = V_INTERP_P10_F16_F32_inreg_fake16 0, $vgpr4, 0, $vgpr0, 0, $vgpr4, 0, 0, 2, implicit $m0, implicit $exec, implicit $mode +... diff --git a/llvm/test/CodeGen/AMDGPU/waitcnt-vinterp.mir b/llvm/test/CodeGen/AMDGPU/waitcnt-vinterp.mir index 41fe81f542c81..22ee92cd01ca6 100644 --- a/llvm/test/CodeGen/AMDGPU/waitcnt-vinterp.mir +++ b/llvm/test/CodeGen/AMDGPU/waitcnt-vinterp.mir @@ -2,29 +2,57 @@ # RUN: llc -mtriple=amdgpu11.00 -verify-machineinstrs -run-pass si-insert-waitcnts -o - %s | FileCheck -check-prefix=GFX11 %s --- -name: waitcnt-vinterp +name: waitcnt-vinterp-f16 machineFunctionInfo: isEntryFunction: true body: | bb.0: liveins: $vgpr0 - ; GFX11-LABEL: name: waitcnt-vinterp + ; GFX11-LABEL: name: waitcnt-vinterp-f16 ; GFX11: liveins: $vgpr0 ; GFX11-NEXT: {{ $}} ; GFX11-NEXT: $vgpr1 = LDS_PARAM_LOAD 0, 0, 0, implicit $m0, implicit $exec ; GFX11-NEXT: $vgpr2 = LDS_PARAM_LOAD 0, 1, 0, implicit $m0, implicit $exec ; GFX11-NEXT: $vgpr3 = LDS_PARAM_LOAD 0, 2, 0, implicit $m0, implicit $exec ; GFX11-NEXT: $vgpr4 = LDS_PARAM_LOAD 0, 3, 0, implicit $m0, implicit $exec - ; GFX11-NEXT: $vgpr5 = V_INTERP_P10_F16_F32_inreg_fake16 0, $vgpr1, 0, $vgpr0, 0, $vgpr1, 0, 0, 2, implicit $m0, implicit $exec, implicit $mode - ; GFX11-NEXT: $vgpr6 = V_INTERP_P10_F16_F32_inreg_fake16 0, $vgpr2, 0, $vgpr0, 0, $vgpr2, 0, 0, 2, implicit $m0, implicit $exec, implicit $mode - ; GFX11-NEXT: $vgpr7 = V_INTERP_P10_F16_F32_inreg_fake16 0, $vgpr3, 0, $vgpr0, 0, $vgpr3, 0, 0, 1, implicit $m0, implicit $exec, implicit $mode - ; GFX11-NEXT: $vgpr8 = V_INTERP_P10_F16_F32_inreg_fake16 0, $vgpr4, 0, $vgpr0, 0, $vgpr4, 0, 0, 0, implicit $m0, implicit $exec, implicit $mode + ; GFX11-NEXT: $vgpr5 = V_INTERP_P10_F16_F32_inreg_t16 0, $vgpr1_lo16, 0, $vgpr0, 0, $vgpr1_lo16, 0, 0, 2, implicit $m0, implicit $exec, implicit $mode + ; GFX11-NEXT: $vgpr6 = V_INTERP_P10_F16_F32_inreg_t16 0, $vgpr2_lo16, 0, $vgpr0, 0, $vgpr2_lo16, 0, 0, 2, implicit $m0, implicit $exec, implicit $mode + ; GFX11-NEXT: $vgpr7 = V_INTERP_P10_F16_F32_inreg_t16 0, $vgpr3_lo16, 0, $vgpr0, 0, $vgpr3_lo16, 0, 0, 1, implicit $m0, implicit $exec, implicit $mode + ; GFX11-NEXT: $vgpr8 = V_INTERP_P10_F16_F32_inreg_t16 0, $vgpr4_lo16, 0, $vgpr0, 0, $vgpr4_lo16, 0, 0, 0, implicit $m0, implicit $exec, implicit $mode $vgpr1 = LDS_PARAM_LOAD 0, 0, 0, implicit $m0, implicit $exec $vgpr2 = LDS_PARAM_LOAD 0, 1, 0, implicit $m0, implicit $exec $vgpr3 = LDS_PARAM_LOAD 0, 2, 0, implicit $m0, implicit $exec $vgpr4 = LDS_PARAM_LOAD 0, 3, 0, implicit $m0, implicit $exec - $vgpr5 = V_INTERP_P10_F16_F32_inreg_fake16 0, $vgpr1, 0, $vgpr0, 0, $vgpr1, 0, 0, 2, implicit $m0, implicit $exec, implicit $mode - $vgpr6 = V_INTERP_P10_F16_F32_inreg_fake16 0, $vgpr2, 0, $vgpr0, 0, $vgpr2, 0, 0, 2, implicit $m0, implicit $exec, implicit $mode - $vgpr7 = V_INTERP_P10_F16_F32_inreg_fake16 0, $vgpr3, 0, $vgpr0, 0, $vgpr3, 0, 0, 2, implicit $m0, implicit $exec, implicit $mode - $vgpr8 = V_INTERP_P10_F16_F32_inreg_fake16 0, $vgpr4, 0, $vgpr0, 0, $vgpr4, 0, 0, 2, implicit $m0, implicit $exec, implicit $mode + $vgpr5 = V_INTERP_P10_F16_F32_inreg_t16 0, $vgpr1_lo16, 0, $vgpr0, 0, $vgpr1_lo16, 0, 0, 2, implicit $m0, implicit $exec, implicit $mode + $vgpr6 = V_INTERP_P10_F16_F32_inreg_t16 0, $vgpr2_lo16, 0, $vgpr0, 0, $vgpr2_lo16, 0, 0, 2, implicit $m0, implicit $exec, implicit $mode + $vgpr7 = V_INTERP_P10_F16_F32_inreg_t16 0, $vgpr3_lo16, 0, $vgpr0, 0, $vgpr3_lo16, 0, 0, 2, implicit $m0, implicit $exec, implicit $mode + $vgpr8 = V_INTERP_P10_F16_F32_inreg_t16 0, $vgpr4_lo16, 0, $vgpr0, 0, $vgpr4_lo16, 0, 0, 2, implicit $m0, implicit $exec, implicit $mode +... + +--- +name: waitcnt-vinterp-f32 +machineFunctionInfo: + isEntryFunction: true +body: | + bb.0: + liveins: $vgpr0 + ; GFX11-LABEL: name: waitcnt-vinterp-f32 + ; GFX11: liveins: $vgpr0 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: $vgpr1 = LDS_PARAM_LOAD 0, 0, 0, implicit $m0, implicit $exec + ; GFX11-NEXT: $vgpr2 = LDS_PARAM_LOAD 0, 1, 0, implicit $m0, implicit $exec + ; GFX11-NEXT: $vgpr3 = LDS_PARAM_LOAD 0, 2, 0, implicit $m0, implicit $exec + ; GFX11-NEXT: $vgpr4 = LDS_PARAM_LOAD 0, 3, 0, implicit $m0, implicit $exec + ; GFX11-NEXT: $vgpr5 = V_INTERP_P10_F32_inreg 0, $vgpr1, 0, $vgpr0, 0, $vgpr1, 0, 2, implicit $m0, implicit $exec, implicit $mode + ; GFX11-NEXT: $vgpr6 = V_INTERP_P10_F32_inreg 0, $vgpr2, 0, $vgpr0, 0, $vgpr2, 0, 2, implicit $m0, implicit $exec, implicit $mode + ; GFX11-NEXT: $vgpr7 = V_INTERP_P10_F32_inreg 0, $vgpr3, 0, $vgpr0, 0, $vgpr3, 0, 1, implicit $m0, implicit $exec, implicit $mode + ; GFX11-NEXT: $vgpr8 = V_INTERP_P10_F32_inreg 0, $vgpr4, 0, $vgpr0, 0, $vgpr4, 0, 0, implicit $m0, implicit $exec, implicit $mode + $vgpr1 = LDS_PARAM_LOAD 0, 0, 0, implicit $m0, implicit $exec + $vgpr2 = LDS_PARAM_LOAD 0, 1, 0, implicit $m0, implicit $exec + $vgpr3 = LDS_PARAM_LOAD 0, 2, 0, implicit $m0, implicit $exec + $vgpr4 = LDS_PARAM_LOAD 0, 3, 0, implicit $m0, implicit $exec + $vgpr5 = V_INTERP_P10_F32_inreg 0, $vgpr1, 0, $vgpr0, 0, $vgpr1, 0, 2, implicit $m0, implicit $exec, implicit $mode + $vgpr6 = V_INTERP_P10_F32_inreg 0, $vgpr2, 0, $vgpr0, 0, $vgpr2, 0, 2, implicit $m0, implicit $exec, implicit $mode + $vgpr7 = V_INTERP_P10_F32_inreg 0, $vgpr3, 0, $vgpr0, 0, $vgpr3, 0, 2, implicit $m0, implicit $exec, implicit $mode + $vgpr8 = V_INTERP_P10_F32_inreg 0, $vgpr4, 0, $vgpr0, 0, $vgpr4, 0, 2, implicit $m0, implicit $exec, implicit $mode ... _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
