llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-backend-amdgpu Author: Petar Avramovic (petar-avramovic) <details> <summary>Changes</summary> Use LLT::integer in bit twiddling lowering for extract/insert vector element. --- Patch is 1.71 MiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/210094.diff 32 Files Affected: - (modified) llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp (+3-2) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/fmul.v2f16.ll (+16-14) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/fp-int-conversions.ll (+3-3) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i16.ll (+2733-4459) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i8.ll (+1631-4754) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir (+60-60) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-insert-vector-elt.mir (+23-23) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.dim.a16.ll (+990-990) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shuffle-vector.mir (+8-8) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shuffle-vector.s16.mir (+181-181) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll (+6-5) - (modified) llvm/test/CodeGen/AMDGPU/flat-saddr-load.ll (+110-174) - (modified) llvm/test/CodeGen/AMDGPU/flat-saddr-store.ll (+35-16) - (modified) llvm/test/CodeGen/AMDGPU/fptrunc.v2f16.no.fast.math.ll (+105-51) - (modified) llvm/test/CodeGen/AMDGPU/indirect-reg-read-imm-idx.ll (+35-5) - (modified) llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll (+952-402) - (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.f16.fp8.ll (+5-3) - (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.f16.ll (+18-14) - (modified) llvm/test/CodeGen/AMDGPU/load-atomic-flat.ll (+235-105) - (modified) llvm/test/CodeGen/AMDGPU/load-atomic-global.ll (+591-256) - (modified) llvm/test/CodeGen/AMDGPU/load-atomic-local.ll (+562-242) - (modified) llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll (+209-101) - (modified) llvm/test/CodeGen/AMDGPU/mad-mix.ll (+782-375) - (modified) llvm/test/CodeGen/AMDGPU/vector-reduce-add.ll (+101-43) - (modified) llvm/test/CodeGen/AMDGPU/vector-reduce-fadd.ll (+117-73) - (modified) llvm/test/CodeGen/AMDGPU/vector-reduce-fmul.ll (+117-73) - (modified) llvm/test/CodeGen/AMDGPU/vector-reduce-mul.ll (+5-15) - (modified) llvm/test/CodeGen/AMDGPU/vector-reduce-or.ll (+426-224) - (modified) llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll (+1001-423) - (modified) llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll (+1001-423) - (modified) llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll (+975-439) - (modified) llvm/test/CodeGen/AMDGPU/vector-reduce-umin.ll (+338-160) ``````````diff diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp index f08110bf0a4bc..73dbd32b88d4b 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp @@ -208,8 +208,9 @@ static LegalizeMutation bitcastToVectorElement32(unsigned TypeIdx) { const LLT Ty = Query.Types[TypeIdx]; unsigned Size = Ty.getSizeInBits(); assert(Size % 32 == 0); - return std::pair( - TypeIdx, LLT::scalarOrVector(ElementCount::getFixed(Size / 32), 32)); + return std::pair(TypeIdx, + LLT::scalarOrVector(ElementCount::getFixed(Size / 32), + LLT::integer(32))); }; } diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fmul.v2f16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fmul.v2f16.ll index fd5ebda9dbc34..7b87764c5ae1f 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fmul.v2f16.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fmul.v2f16.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -global-isel -mtriple=amdgpu9.00-amd-amdhsa < %s | FileCheck -check-prefix=GFX9 %s -; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgpu8.03-amd-amdhsa < %s | FileCheck -check-prefix=GFX8 %s +; RUN: llc -global-isel -mtriple=amdgpu8.03-amd-amdhsa < %s | FileCheck -check-prefix=GFX8 %s ; RUN: llc -global-isel -mtriple=amdgpu10.10-amd-amdhsa < %s | FileCheck -check-prefix=GFX10 %s ; RUN: llc -global-isel -mtriple=amdgpu11.00-amd-amdhsa -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefix=GFX10 %s @@ -155,23 +155,22 @@ define <2 x half> @fmul_v2_half_neg_hi(<2 x half> %a, <2 x half> %b) #0 { ; GFX9-LABEL: fmul_v2_half_neg_hi: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_pk_mul_f16 v0, v0, v1 neg_hi:[0,1] +; GFX9-NEXT: v_xor_b32_e32 v2, 0x80000000, v1 +; GFX9-NEXT: s_mov_b32 s4, 0xffff +; GFX9-NEXT: v_bfi_b32 v1, s4, v1, v2 +; GFX9-NEXT: v_pk_mul_f16 v0, v0, v1 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX8-LABEL: fmul_v2_half_neg_hi: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX8-NEXT: v_xor_b32_e32 v2, 0x80000000, v1 -; GFX8-NEXT: v_mul_f16_sdwa v2, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 -; GFX8-NEXT: v_mul_f16_e32 v0, v0, v1 -; GFX8-NEXT: v_or_b32_e32 v0, v0, v2 +; GFX8-NEXT: v_mul_f16_e32 v1, v0, v1 +; GFX8-NEXT: v_mul_f16_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 +; GFX8-NEXT: v_mov_b32_e32 v2, 16 +; GFX8-NEXT: v_lshlrev_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 +; GFX8-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; GFX8-NEXT: s_setpc_b64 s[30:31] -; -; GFX10-LABEL: fmul_v2_half_neg_hi: -; GFX10: ; %bb.0: -; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: v_pk_mul_f16 v0, v0, v1 neg_hi:[0,1] -; GFX10-NEXT: s_setpc_b64 s[30:31] %b1 = bitcast <2 x half> %b to float %b2 = fneg float %b1 %b3 = bitcast float %b2 to <2 x half> @@ -193,9 +192,12 @@ define <2 x half> @fmul_v2_half_neg_lo1(<2 x half> %a, <2 x half> %b) #0 { ; GFX8-LABEL: fmul_v2_half_neg_lo1: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX8-NEXT: v_mul_f16_sdwa v2, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD -; GFX8-NEXT: v_mul_f16_e32 v0, v0, v1 -; GFX8-NEXT: v_or_b32_e32 v0, v0, v2 +; GFX8-NEXT: v_xor_b32_e32 v2, 0x80000000, v1 +; GFX8-NEXT: v_mul_f16_e32 v1, v0, v1 +; GFX8-NEXT: v_mul_f16_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; GFX8-NEXT: v_mov_b32_e32 v2, 16 +; GFX8-NEXT: v_lshlrev_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 +; GFX8-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: fmul_v2_half_neg_lo1: diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fp-int-conversions.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fp-int-conversions.ll index 7317d24d3e1be..219563a079697 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fp-int-conversions.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fp-int-conversions.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --filter-out "s_wait" --filter-out "s_delay_alu" --filter-out "endpgm" --filter-out "store" --version 6 -; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgpu10.10 < %s | FileCheck %s --check-prefixes=GCN,FAKE16,PREGFX12,PREGFX12-FAKE16 -; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgpu11.00 -mattr=+real-true16 < %s | FileCheck %s --check-prefixes=GCN,PREGFX12,TRUE16 -; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgpu11.00 -mattr=-real-true16 < %s | FileCheck %s --check-prefixes=GCN,FAKE16,PREGFX12,PREGFX12-FAKE16 +; RUN: llc -global-isel -mtriple=amdgpu10.10 < %s | FileCheck %s --check-prefixes=GCN,FAKE16,PREGFX12,PREGFX12-FAKE16 +; RUN: llc -global-isel -mtriple=amdgpu11.00 -mattr=+real-true16 < %s | FileCheck %s --check-prefixes=GCN,PREGFX12,TRUE16 +; RUN: llc -global-isel -mtriple=amdgpu11.00 -mattr=-real-true16 < %s | FileCheck %s --check-prefixes=GCN,FAKE16,PREGFX12,PREGFX12-FAKE16 ; RUN: llc -global-isel -mtriple=amdgpu12.00 < %s | FileCheck %s --check-prefixes=GCN,FAKE16,GFX12 define amdgpu_ps void @s_fptoui_f16_to_i16(half inreg %x, ptr addrspace(1) %out) { diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i16.ll index 6d6d51a66bfa4..0f963ba85b73e 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i16.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i16.ll @@ -1,22 +1,23 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgpu9.00-mesa-mesa3d < %s | FileCheck --check-prefix=GFX9 %s -; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgpu8.03-mesa-mesa3d < %s | FileCheck --check-prefix=GFX8 %s -; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgpu7.01-mesa-mesa3d < %s | FileCheck --check-prefix=GFX7 %s -; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgpu10.10-mesa-mesa3d < %s | FileCheck --check-prefix=GFX10 %s -; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgpu11.00-mesa-mesa3d < %s | FileCheck --check-prefix=GFX11 %s +; RUN: llc -global-isel -mtriple=amdgpu9.00-mesa-mesa3d < %s | FileCheck --check-prefix=GFX9 %s +; RUN: llc -global-isel -mtriple=amdgpu8.03-mesa-mesa3d < %s | FileCheck --check-prefix=GFX8 %s +; RUN: llc -global-isel -mtriple=amdgpu7.01-mesa-mesa3d < %s | FileCheck --check-prefix=GFX7 %s +; RUN: llc -global-isel -mtriple=amdgpu10.10-mesa-mesa3d < %s | FileCheck --check-prefix=GFX10 %s +; RUN: llc -global-isel -mtriple=amdgpu11.00-mesa-mesa3d < %s | FileCheck --check-prefix=GFX11 %s define amdgpu_ps void @insertelement_s_v2i16_s_s(ptr addrspace(4) inreg %ptr, i16 inreg %val, i32 inreg %idx) { ; GFX9-LABEL: insertelement_s_v2i16_s_s: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_load_dword s0, s[2:3], 0x0 -; GFX9-NEXT: s_lshl_b32 s1, s5, 4 -; GFX9-NEXT: s_pack_ll_b32_b16 s2, s4, s4 +; GFX9-NEXT: s_and_b32 s1, s5, 1 +; GFX9-NEXT: s_lshl_b32 s1, s1, 4 +; GFX9-NEXT: s_and_b32 s2, s4, 0xffff +; GFX9-NEXT: s_lshl_b32 s2, s2, s1 ; GFX9-NEXT: s_lshl_b32 s1, 0xffff, s1 -; GFX9-NEXT: v_mov_b32_e32 v0, 0 ; GFX9-NEXT: s_waitcnt lgkmcnt(0) -; GFX9-NEXT: s_xor_b32 s2, s2, s0 -; GFX9-NEXT: s_and_b32 s1, s2, s1 -; GFX9-NEXT: s_xor_b32 s0, s1, s0 +; GFX9-NEXT: s_andn2_b32 s0, s0, s1 +; GFX9-NEXT: s_or_b32 s0, s0, s2 +; GFX9-NEXT: v_mov_b32_e32 v0, 0 ; GFX9-NEXT: v_mov_b32_e32 v1, 0 ; GFX9-NEXT: v_mov_b32_e32 v2, s0 ; GFX9-NEXT: global_store_dword v[0:1], v2, off @@ -25,15 +26,14 @@ define amdgpu_ps void @insertelement_s_v2i16_s_s(ptr addrspace(4) inreg %ptr, i1 ; GFX8-LABEL: insertelement_s_v2i16_s_s: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_load_dword s0, s[2:3], 0x0 -; GFX8-NEXT: s_and_b32 s1, 0xffff, s4 -; GFX8-NEXT: s_lshl_b32 s2, s1, 16 -; GFX8-NEXT: s_or_b32 s1, s1, s2 -; GFX8-NEXT: s_lshl_b32 s2, s5, 4 +; GFX8-NEXT: s_and_b32 s1, s5, 1 +; GFX8-NEXT: s_lshl_b32 s1, s1, 4 +; GFX8-NEXT: s_and_b32 s2, s4, 0xffff +; GFX8-NEXT: s_lshl_b32 s2, s2, s1 +; GFX8-NEXT: s_lshl_b32 s1, 0xffff, s1 ; GFX8-NEXT: s_waitcnt lgkmcnt(0) -; GFX8-NEXT: s_xor_b32 s1, s1, s0 -; GFX8-NEXT: s_lshl_b32 s2, 0xffff, s2 -; GFX8-NEXT: s_and_b32 s1, s1, s2 -; GFX8-NEXT: s_xor_b32 s0, s1, s0 +; GFX8-NEXT: s_andn2_b32 s0, s0, s1 +; GFX8-NEXT: s_or_b32 s0, s0, s2 ; GFX8-NEXT: v_mov_b32_e32 v0, 0 ; GFX8-NEXT: v_mov_b32_e32 v1, 0 ; GFX8-NEXT: v_mov_b32_e32 v2, s0 @@ -43,34 +43,34 @@ define amdgpu_ps void @insertelement_s_v2i16_s_s(ptr addrspace(4) inreg %ptr, i1 ; GFX7-LABEL: insertelement_s_v2i16_s_s: ; GFX7: ; %bb.0: ; GFX7-NEXT: s_load_dword s0, s[2:3], 0x0 -; GFX7-NEXT: s_lshl_b32 s1, s4, 16 +; GFX7-NEXT: s_and_b32 s1, s5, 1 +; GFX7-NEXT: s_lshl_b32 s1, s1, 4 ; GFX7-NEXT: s_and_b32 s2, s4, 0xffff -; GFX7-NEXT: s_or_b32 s1, s2, s1 -; GFX7-NEXT: s_lshl_b32 s2, s5, 4 +; GFX7-NEXT: s_lshl_b32 s2, s2, s1 +; GFX7-NEXT: s_lshl_b32 s1, 0xffff, s1 ; GFX7-NEXT: s_waitcnt lgkmcnt(0) -; GFX7-NEXT: s_xor_b32 s1, s1, s0 -; GFX7-NEXT: s_lshl_b32 s2, 0xffff, s2 -; GFX7-NEXT: s_and_b32 s1, s1, s2 -; GFX7-NEXT: s_xor_b32 s4, s1, s0 +; GFX7-NEXT: s_andn2_b32 s0, s0, s1 +; GFX7-NEXT: s_or_b32 s2, s0, s2 ; GFX7-NEXT: s_mov_b64 s[0:1], 0 -; GFX7-NEXT: s_mov_b32 s3, 0xf000 +; GFX7-NEXT: v_mov_b32_e32 v0, s2 ; GFX7-NEXT: s_mov_b32 s2, -1 -; GFX7-NEXT: v_mov_b32_e32 v0, s4 +; GFX7-NEXT: s_mov_b32 s3, 0xf000 ; GFX7-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; GFX7-NEXT: s_endpgm ; ; GFX10-LABEL: insertelement_s_v2i16_s_s: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_load_dword s0, s[2:3], 0x0 -; GFX10-NEXT: s_lshl_b32 s1, s5, 4 -; GFX10-NEXT: s_pack_ll_b32_b16 s2, s4, s4 -; GFX10-NEXT: s_lshl_b32 s1, 0xffff, s1 +; GFX10-NEXT: s_and_b32 s1, s5, 1 +; GFX10-NEXT: s_and_b32 s2, s4, 0xffff +; GFX10-NEXT: s_lshl_b32 s1, s1, 4 ; GFX10-NEXT: v_mov_b32_e32 v0, 0 +; GFX10-NEXT: s_lshl_b32 s3, 0xffff, s1 +; GFX10-NEXT: s_lshl_b32 s1, s2, s1 ; GFX10-NEXT: v_mov_b32_e32 v1, 0 ; GFX10-NEXT: s_waitcnt lgkmcnt(0) -; GFX10-NEXT: s_xor_b32 s2, s2, s0 -; GFX10-NEXT: s_and_b32 s1, s2, s1 -; GFX10-NEXT: s_xor_b32 s0, s1, s0 +; GFX10-NEXT: s_andn2_b32 s0, s0, s3 +; GFX10-NEXT: s_or_b32 s0, s0, s1 ; GFX10-NEXT: v_mov_b32_e32 v2, s0 ; GFX10-NEXT: global_store_dword v[0:1], v2, off ; GFX10-NEXT: s_endpgm @@ -78,16 +78,16 @@ define amdgpu_ps void @insertelement_s_v2i16_s_s(ptr addrspace(4) inreg %ptr, i1 ; GFX11-LABEL: insertelement_s_v2i16_s_s: ; GFX11: ; %bb.0: ; GFX11-NEXT: s_load_b32 s0, s[2:3], 0x0 -; GFX11-NEXT: s_lshl_b32 s1, s5, 4 -; GFX11-NEXT: s_pack_ll_b32_b16 s2, s4, s4 -; GFX11-NEXT: s_lshl_b32 s1, 0xffff, s1 +; GFX11-NEXT: s_and_b32 s1, s5, 1 +; GFX11-NEXT: s_and_b32 s2, s4, 0xffff +; GFX11-NEXT: s_lshl_b32 s1, s1, 4 ; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0 +; GFX11-NEXT: s_lshl_b32 s3, 0xffff, s1 +; GFX11-NEXT: s_lshl_b32 s1, s2, s1 ; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: s_xor_b32 s2, s2, s0 +; GFX11-NEXT: s_and_not1_b32 s0, s0, s3 ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) -; GFX11-NEXT: s_and_b32 s1, s2, s1 -; GFX11-NEXT: s_xor_b32 s0, s1, s0 -; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-NEXT: s_or_b32 s0, s0, s1 ; GFX11-NEXT: v_mov_b32_e32 v2, s0 ; GFX11-NEXT: global_store_b32 v[0:1], v2, off ; GFX11-NEXT: s_endpgm @@ -101,30 +101,33 @@ define amdgpu_ps void @insertelement_v_v2i16_s_s(ptr addrspace(1) %ptr, i16 inre ; GFX9-LABEL: insertelement_v_v2i16_s_s: ; GFX9: ; %bb.0: ; GFX9-NEXT: global_load_dword v2, v[0:1], off -; GFX9-NEXT: s_lshl_b32 s0, s3, 4 -; GFX9-NEXT: s_pack_ll_b32_b16 s1, s2, s2 +; GFX9-NEXT: s_and_b32 s0, s3, 1 +; GFX9-NEXT: s_lshl_b32 s0, s0, 4 +; GFX9-NEXT: s_and_b32 s1, s2, 0xffff +; GFX9-NEXT: s_lshl_b32 s1, s1, s0 ; GFX9-NEXT: s_lshl_b32 s0, 0xffff, s0 +; GFX9-NEXT: s_not_b32 s0, s0 ; GFX9-NEXT: v_mov_b32_e32 v3, s1 ; GFX9-NEXT: v_mov_b32_e32 v0, 0 ; GFX9-NEXT: v_mov_b32_e32 v1, 0 ; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_bfi_b32 v2, s0, v3, v2 +; GFX9-NEXT: v_and_or_b32 v2, v2, s0, v3 ; GFX9-NEXT: global_store_dword v[0:1], v2, off ; GFX9-NEXT: s_endpgm ; ; GFX8-LABEL: insertelement_v_v2i16_s_s: ; GFX8: ; %bb.0: -; GFX8-NEXT: flat_load_dword v2, v[0:1] -; GFX8-NEXT: s_and_b32 s0, 0xffff, s2 -; GFX8-NEXT: s_lshl_b32 s1, s0, 16 -; GFX8-NEXT: s_or_b32 s0, s0, s1 -; GFX8-NEXT: s_lshl_b32 s1, s3, 4 -; GFX8-NEXT: s_lshl_b32 s1, 0xffff, s1 -; GFX8-NEXT: v_mov_b32_e32 v3, s1 -; GFX8-NEXT: v_mov_b32_e32 v0, 0 +; GFX8-NEXT: flat_load_dword v0, v[0:1] +; GFX8-NEXT: s_and_b32 s0, s3, 1 +; GFX8-NEXT: s_and_b32 s1, s2, 0xffff +; GFX8-NEXT: s_lshl_b32 s0, s0, 4 +; GFX8-NEXT: s_lshl_b32 s1, s1, s0 +; GFX8-NEXT: s_lshl_b32 s0, 0xffff, s0 ; GFX8-NEXT: v_mov_b32_e32 v1, 0 ; GFX8-NEXT: s_waitcnt vmcnt(0) -; GFX8-NEXT: v_bfi_b32 v2, v3, s0, v2 +; GFX8-NEXT: v_bfi_b32 v2, s0, 0, v0 +; GFX8-NEXT: v_mov_b32_e32 v0, 0 +; GFX8-NEXT: v_or_b32_e32 v2, s1, v2 ; GFX8-NEXT: flat_store_dword v[0:1], v2 ; GFX8-NEXT: s_endpgm ; @@ -132,44 +135,49 @@ define amdgpu_ps void @insertelement_v_v2i16_s_s(ptr addrspace(1) %ptr, i16 inre ; GFX7: ; %bb.0: ; GFX7-NEXT: s_mov_b32 s6, 0 ; GFX7-NEXT: s_mov_b32 s7, 0xf000 -; GFX7-NEXT: s_mov_b32 s4, s6 -; GFX7-NEXT: s_mov_b32 s5, s6 +; GFX7-NEXT: s_mov_b64 s[4:5], 0 ; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[4:7], 0 addr64 -; GFX7-NEXT: s_lshl_b32 s0, s2, 16 +; GFX7-NEXT: s_and_b32 s0, s3, 1 ; GFX7-NEXT: s_and_b32 s1, s2, 0xffff -; GFX7-NEXT: s_lshl_b32 s2, s3, 4 -; GFX7-NEXT: s_or_b32 s0, s1, s0 -; GFX7-NEXT: s_lshl_b32 s1, 0xffff, s2 -; GFX7-NEXT: v_mov_b32_e32 v1, s1 +; GFX7-NEXT: s_lshl_b32 s0, s0, 4 +; GFX7-NEXT: s_lshl_b32 s1, s1, s0 +; GFX7-NEXT: s_lshl_b32 s0, 0xffff, s0 ; GFX7-NEXT: s_mov_b64 s[4:5], 0 ; GFX7-NEXT: s_mov_b32 s6, -1 ; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: v_bfi_b32 v0, v1, s0, v0 +; GFX7-NEXT: v_bfi_b32 v0, s0, 0, v0 +; GFX7-NEXT: v_or_b32_e32 v0, s1, v0 ; GFX7-NEXT: buffer_store_dword v0, off, s[4:7], 0 ; GFX7-NEXT: s_endpgm ; ; GFX10-LABEL: insertelement_v_v2i16_s_s: ; GFX10: ; %bb.0: ; GFX10-NEXT: global_load_dword v2, v[0:1], off -; GFX10-NEXT: s_lshl_b32 s0, s3, 4 -; GFX10-NEXT: s_pack_ll_b32_b16 s1, s2, s2 -; GFX10-NEXT: s_lshl_b32 s0, 0xffff, s0 +; GFX10-NEXT: s_and_b32 s0, s3, 1 +; GFX10-NEXT: s_and_b32 s1, s2, 0xffff +; GFX10-NEXT: s_lshl_b32 s0, s0, 4 ; GFX10-NEXT: v_mov_b32_e32 v0, 0 +; GFX10-NEXT: s_lshl_b32 s2, 0xffff, s0 +; GFX10-NEXT: s_lshl_b32 s0, s1, s0 +; GFX10-NEXT: s_not_b32 s1, s2 ; GFX10-NEXT: v_mov_b32_e32 v1, 0 ; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: v_bfi_b32 v2, s0, s1, v2 +; GFX10-NEXT: v_and_or_b32 v2, v2, s1, s0 ; GFX10-NEXT: global_store_dword v[0:1], v2, off ; GFX10-NEXT: s_endpgm ; ; GFX11-LABEL: insertelement_v_v2i16_s_s: ; GFX11: ; %bb.0: ; GFX11-NEXT: global_load_b32 v2, v[0:1], off -; GFX11-NEXT: s_lshl_b32 s0, s3, 4 -; GFX11-NEXT: s_pack_ll_b32_b16 s1, s2, s2 -; GFX11-NEXT: s_lshl_b32 s0, 0xffff, s0 +; GFX11-NEXT: s_and_b32 s0, s3, 1 +; GFX11-NEXT: s_and_b32 s1, s2, 0xffff +; GFX11-NEXT: s_lshl_b32 s0, s0, 4 ; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0 +; GFX11-NEXT: s_lshl_b32 s2, 0xffff, s0 +; GFX11-NEXT: s_lshl_b32 s0, s1, s0 +; GFX11-NEXT: s_not_b32 s1, s2 ; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: v_bfi_b32 v2, s0, s1, v2 +; GFX11-NEXT: v_and_or_b32 v2, v2, s1, s0 ; GFX11-NEXT: global_store_b32 v[0:1], v2, off ; GFX11-NEXT: s_endpgm %vec = load <2 x i16>, ptr addrspace(1 ) %ptr @@ -182,74 +190,79 @@ define amdgpu_ps void @insertelement_s_v2i16_v_s(ptr addrspace(4) inreg %ptr, i1 ; GFX9-LABEL: insertelement_s_v2i16_v_s: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_load_dword s0, s[2:3], 0x0 -; GFX9-NEXT: s_mov_b32 s1, 0x5040100 -; GFX9-NEXT: v_perm_b32 v2, v0, v0, s1 -; GFX9-NEXT: s_lshl_b32 s1, s4, 4 -; GFX9-NEXT: s_lshl_b32 s1, 0xffff, s1 -; GFX9-NEXT: v_mov_b32_e32 v3, s1 +; GFX9-NEXT: s_and_b32 s1, s4, 1 +; GFX9-NEXT: s_lshl_b32 s1, s1, 4 +; GFX9-NEXT: s_lshl_b32 s2, 0xffff, s1 +; GFX9-NEXT: v_and_b32_e32 v2, 0xffff, v0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: s_andn2_b32 s0, s0, s2 +; GFX9-NEXT: v_mov_b32_e32 v3, s0 ; GFX9-NEXT: v_mov_b32_e32 v0, 0 ; GFX9-NEXT: v_mov_b32_e32 v1, 0 -; GFX9-NEXT: s_waitcnt lgkmcnt(0) -; GFX9-NEXT: v_bfi_b32 v2, v3, v2, s0 +; GFX9-NEXT: v_lshl_or_b32 v2, v2, s1, v3 ; GFX9-NEXT: global_store_dword v[0:1], v2, off ; GFX9-NEXT: s_endpgm ; ; GFX8-LABEL: insertelement_s_v2i16_v_s: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_load_dword s0, s[2:3], 0x0 -; GFX8-NEXT: v_mov_b32_e32 v1, 16 -; GFX8-NEXT: s_lshl_b32 s1, s4, 4 -; GFX8-NEXT: v_lshlrev_b32_sdwa v1, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 +; GFX8-NEXT: s_and_b32 s1, s4, 1 +; GFX8-NEXT: s_lshl_b32 s1, s1, 4 +; GFX8-NEXT: v_mov_b32_e32 v1, s1 ; GFX8-NEXT: s_lshl_b32 s1, 0xffff, s1 -; GFX8-NEXT: v_or_b32_sdwa v2, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; GFX8-NEXT: v_mov_b32_e32 v3, s1 +; GFX8-NEXT: v_lshlrev_b32_sdwa v2, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: s_andn2_b32 s0, s0, s1 ; GFX8-NEXT: v_mov_b32_e32 v0, 0 ; GFX8-NEXT: v_mov_b32_e32 v1, 0 -; GFX8-NEXT: s_waitcnt lgkmcnt(0) -; GFX8-NEXT: v_bfi_b32 v2, v3, v2, s0 +; GFX8-NEXT: v_or_b32_e32 v2, s0, v2 ; GFX8-NEXT: flat_store_dword v[0:1], v2 ; GFX8-NEXT: s_endpgm ; ; GFX7-LABEL: insertelement_s_v2i16_v_s: ; GFX7: ; %bb.0: ; GFX7-NEXT: s_load_dword s0, s[2:3], 0x0 -; GFX7-NEXT: s_lshl_b32 s1, s4, 4 -; GFX7-NEXT: v_lshlrev_b32_e32 v1, 16, v0 +; GFX7-NEXT: s_and_b32 s1, s4, 1 +; GFX7-NEXT: s_lshl_b32 s1, s1, 4 ; GFX7-NEXT: v_and_b32_e32 v0, 0xffff, v0 +; GFX7-NEXT: v_lshlrev_b32_e32 v0, s1, v0 ; GFX7-NEXT: s_lshl_b32 s1, 0xffff, s1 -; GFX7-NEXT: v_or_b32_e32 v0, v0, v1 -; GFX7-NEXT: v_mov_b32_e32 v1, s1 ; GFX7-NEXT: s_waitcnt lgkmcnt(0) -; GFX7-NEXT: v_bfi_b32 v0, v1, v0, s0 +; GFX7-NEXT: s_andn2_b32 s0, s0, s1 +; GFX7-NEXT: v_or_b32_e32 v0, s0, v0 ; GFX7-NEXT: s_mov_b64 s[0:1], 0 -; GFX7-NEXT: s_mov_b32 s3, 0xf000 ; GFX7-NEXT: s_mov_b32 s2, -1 +; GFX7-NEXT: s_mov_b32 s3, 0xf000 ; GFX7-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; GFX7-NEXT: s_endpgm ; ; GFX10-LABEL: insertelement_s_v2i16_v_s: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_load_dword s0, s[2:3], 0x0 -; GFX10-NEXT: v_perm_b32 v2, v0, v0, 0x5040100 -; GFX10-NEXT: s_lshl_b32 s1, s4, 4 +; GFX10-NEXT: s_and_b32 s1, s4, 1 +; GFX10-NEXT: v_and_b32_e32 v2, 0xffff, v0 +; GFX10-NEXT: s_lshl_b32 s1, s1, 4 ; GFX10-NEXT: v_mov_b32_e32 v0, 0 -; GFX10-NEXT: s_lshl_b32 s1, 0xffff, s1 +; GFX10-NEXT: s_lshl_b32 s2, 0xffff, s1 ; GFX10-NEXT: v_mov_b32_e32 v1, 0 ; GFX10-NEXT: s_waitcnt lgkmcnt(0) -; GFX10-NEXT: v_bfi_b32 v2, s1, v2, s0 +; GFX10-NEXT: s_andn2_b32 s0, s0, s2 +; GFX10-NEXT: v_lshl_or_b32 v2, v2, s1, s0 ; GFX10-NEXT: global_store_dword v[0:1], v2, off ; GFX10-NEXT: s_endpgm ; ; GFX11-LABEL: insertelement_s_v2i16_v_s: ; GFX11: ; %bb.0: ; GFX11-NEXT: s_load_b32 s0, s[2:3], 0x0 -; GFX11-NEXT: v_mov_b16_e32 v2.l, v0.l -; GFX11-NEXT: v_mov_b16_e32... [truncated] `````````` </details> https://github.com/llvm/llvm-project/pull/210094 _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
