llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-llvm-globalisel Author: Petar Avramovic (petar-avramovic) <details> <summary>Changes</summary> --- Full diff: https://github.com/llvm/llvm-project/pull/210101.diff 2 Files Affected: - (modified) llvm/lib/Target/AMDGPU/AMDGPUPreLegalizerCombiner.cpp (+6-6) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/combine-short-clamp.ll (+26-46) ``````````diff diff --git a/llvm/lib/Target/AMDGPU/AMDGPUPreLegalizerCombiner.cpp b/llvm/lib/Target/AMDGPU/AMDGPUPreLegalizerCombiner.cpp index 67c0bdd35f367..b6b84981329ed 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUPreLegalizerCombiner.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUPreLegalizerCombiner.cpp @@ -172,9 +172,9 @@ void AMDGPUPreLegalizerCombinerImpl::applyClampI64ToI16( Register Src = MatchInfo.Origin; assert(MI.getMF()->getRegInfo().getType(Src) == LLT::scalar(64)); - const LLT S32 = LLT::scalar(32); + const LLT I32 = LLT::integer(32); - auto Unmerge = B.buildUnmerge(S32, Src); + auto Unmerge = B.buildUnmerge(I32, Src); assert(MI.getOpcode() != AMDGPU::G_AMDGPU_CVT_PK_I16_I32); @@ -185,13 +185,13 @@ void AMDGPUPreLegalizerCombinerImpl::applyClampI64ToI16( auto MinBoundary = std::min(MatchInfo.Cmp1, MatchInfo.Cmp2); auto MaxBoundary = std::max(MatchInfo.Cmp1, MatchInfo.Cmp2); - auto MinBoundaryDst = B.buildConstant(S32, MinBoundary); - auto MaxBoundaryDst = B.buildConstant(S32, MaxBoundary); + auto MinBoundaryDst = B.buildConstant(I32, MinBoundary); + auto MaxBoundaryDst = B.buildConstant(I32, MaxBoundary); - auto Bitcast = B.buildBitcast({S32}, CvtPk); + auto Bitcast = B.buildBitcast({I32}, CvtPk); auto Med3 = B.buildInstr( - AMDGPU::G_AMDGPU_SMED3, {S32}, + AMDGPU::G_AMDGPU_SMED3, {I32}, {MinBoundaryDst.getReg(0), Bitcast.getReg(0), MaxBoundaryDst.getReg(0)}, MI.getFlags()); diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-short-clamp.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-short-clamp.ll index d3a68603f2566..cd4eefa846e57 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-short-clamp.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-short-clamp.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 -; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgpu6.00-amd-amdhsa < %s | FileCheck --check-prefixes=GCN,GFX678 %s -; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgpu9.00-amd-amdhsa < %s | FileCheck --check-prefixes=GCN,GFX9 %s -; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgpu10.10 < %s | FileCheck --check-prefixes=GCN,GFX10 %s -; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgpu11.00 < %s | FileCheck --check-prefixes=GCN,GFX11 %s +; RUN: llc -global-isel -mtriple=amdgpu6.00-amd-amdhsa < %s | FileCheck --check-prefixes=GCN,GFX678 %s +; RUN: llc -global-isel -mtriple=amdgpu9.00-amd-amdhsa < %s | FileCheck --check-prefixes=GCN,GFX9 %s +; RUN: llc -global-isel -mtriple=amdgpu10.10 < %s | FileCheck --check-prefixes=GCN,GFX10 %s +; RUN: llc -global-isel -mtriple=amdgpu11.00 < %s | FileCheck --check-prefixes=GCN,GFX11 %s declare i64 @llvm.smax.i64(i64, i64) declare i64 @llvm.smin.i64(i64, i64) @@ -316,17 +316,12 @@ define i16 @clamp_i64_i16_uniform(i64 inreg %in) #0 { ; GFX678-LABEL: clamp_i64_i16_uniform: ; GFX678: ; %bb.0: ; %entry ; GFX678-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX678-NEXT: v_mov_b32_e32 v0, 0xffff8000 -; GFX678-NEXT: v_mov_b32_e32 v1, -1 -; GFX678-NEXT: v_cmp_gt_i64_e32 vcc, s[16:17], v[0:1] -; GFX678-NEXT: v_mov_b32_e32 v0, 0x7fff -; GFX678-NEXT: s_and_b64 s[4:5], vcc, exec -; GFX678-NEXT: s_cselect_b32 s5, s17, -1 -; GFX678-NEXT: v_mov_b32_e32 v1, 0 -; GFX678-NEXT: s_cselect_b32 s4, s16, 0xffff8000 -; GFX678-NEXT: v_cmp_lt_i64_e32 vcc, s[4:5], v[0:1] -; GFX678-NEXT: s_and_b64 s[6:7], vcc, exec -; GFX678-NEXT: s_cselect_b32 s4, s4, 0x7fff +; GFX678-NEXT: v_mov_b32_e32 v0, s17 +; GFX678-NEXT: v_cvt_pk_i16_i32_e32 v0, s16, v0 +; GFX678-NEXT: v_mov_b32_e32 v1, 0xffff8000 +; GFX678-NEXT: v_mov_b32_e32 v2, 0x7fff +; GFX678-NEXT: v_med3_i32 v0, v1, v0, v2 +; GFX678-NEXT: v_readfirstlane_b32 s4, v0 ; GFX678-NEXT: s_add_i32 s4, s4, s4 ; GFX678-NEXT: v_mov_b32_e32 v0, s4 ; GFX678-NEXT: s_setpc_b64 s[30:31] @@ -334,17 +329,12 @@ define i16 @clamp_i64_i16_uniform(i64 inreg %in) #0 { ; GFX9-LABEL: clamp_i64_i16_uniform: ; GFX9: ; %bb.0: ; %entry ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_mov_b32_e32 v0, 0xffff8000 -; GFX9-NEXT: v_mov_b32_e32 v1, -1 -; GFX9-NEXT: v_cmp_gt_i64_e32 vcc, s[16:17], v[0:1] -; GFX9-NEXT: v_mov_b32_e32 v0, 0x7fff -; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec -; GFX9-NEXT: s_cselect_b32 s5, s17, -1 -; GFX9-NEXT: v_mov_b32_e32 v1, 0 -; GFX9-NEXT: s_cselect_b32 s4, s16, 0xffff8000 -; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, s[4:5], v[0:1] -; GFX9-NEXT: s_and_b64 s[6:7], vcc, exec -; GFX9-NEXT: s_cselect_b32 s4, s4, 0x7fff +; GFX9-NEXT: v_mov_b32_e32 v0, s17 +; GFX9-NEXT: v_cvt_pk_i16_i32 v0, s16, v0 +; GFX9-NEXT: v_mov_b32_e32 v1, 0xffff8000 +; GFX9-NEXT: v_mov_b32_e32 v2, 0x7fff +; GFX9-NEXT: v_med3_i32 v0, v1, v0, v2 +; GFX9-NEXT: v_readfirstlane_b32 s4, v0 ; GFX9-NEXT: s_add_i32 s4, s4, s4 ; GFX9-NEXT: v_mov_b32_e32 v0, s4 ; GFX9-NEXT: s_setpc_b64 s[30:31] @@ -352,15 +342,10 @@ define i16 @clamp_i64_i16_uniform(i64 inreg %in) #0 { ; GFX10-LABEL: clamp_i64_i16_uniform: ; GFX10: ; %bb.0: ; %entry ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: s_movk_i32 s4, 0x8000 -; GFX10-NEXT: s_mov_b32 s5, -1 -; GFX10-NEXT: v_cmp_gt_i64_e64 s4, s[16:17], s[4:5] -; GFX10-NEXT: s_and_b32 s4, s4, exec_lo -; GFX10-NEXT: s_cselect_b32 s5, s17, -1 -; GFX10-NEXT: s_cselect_b32 s4, s16, 0xffff8000 -; GFX10-NEXT: v_cmp_gt_i64_e64 s5, 0x7fff, s[4:5] -; GFX10-NEXT: s_and_b32 s5, s5, exec_lo -; GFX10-NEXT: s_cselect_b32 s4, s4, 0x7fff +; GFX10-NEXT: v_cvt_pk_i16_i32 v0, s16, s17 +; GFX10-NEXT: v_mov_b32_e32 v1, 0x7fff +; GFX10-NEXT: v_med3_i32 v0, 0xffff8000, v0, v1 +; GFX10-NEXT: v_readfirstlane_b32 s4, v0 ; GFX10-NEXT: s_add_i32 s4, s4, s4 ; GFX10-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-NEXT: s_setpc_b64 s[30:31] @@ -368,18 +353,13 @@ define i16 @clamp_i64_i16_uniform(i64 inreg %in) #0 { ; GFX11-LABEL: clamp_i64_i16_uniform: ; GFX11: ; %bb.0: ; %entry ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: s_movk_i32 s2, 0x8000 -; GFX11-NEXT: s_mov_b32 s3, -1 -; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1) -; GFX11-NEXT: v_cmp_gt_i64_e64 s2, s[0:1], s[2:3] -; GFX11-NEXT: s_and_b32 s2, s2, exec_lo -; GFX11-NEXT: s_cselect_b32 s1, s1, -1 -; GFX11-NEXT: s_cselect_b32 s0, s0, 0xffff8000 -; GFX11-NEXT: v_cmp_gt_i64_e64 s1, 0x7fff, s[0:1] -; GFX11-NEXT: s_and_b32 s1, s1, exec_lo -; GFX11-NEXT: s_cselect_b32 s0, s0, 0x7fff -; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) +; GFX11-NEXT: v_cvt_pk_i16_i32 v0, s0, s1 +; GFX11-NEXT: v_mov_b32_e32 v1, 0x7fff +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-NEXT: v_med3_i32 v0, 0xffff8000, v0, v1 +; GFX11-NEXT: v_readfirstlane_b32 s0, v0 ; GFX11-NEXT: s_add_i32 s0, s0, s0 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-NEXT: s_setpc_b64 s[30:31] entry: `````````` </details> https://github.com/llvm/llvm-project/pull/210101 _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
