llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-backend-amdgpu @llvm/pr-subscribers-llvm-globalisel Author: Dhruva Chakrabarti (dhruvachak) <details> <summary>Changes</summary> https://github.com/llvm/llvm-project/pull/169616 introduced scheduling-strategy-specific GCNTrackers. This PR follows that template and enables GCNTrackers for the max-occupancy strategy. Depends on https://github.com/llvm/llvm-project/pull/184275. Assisted-by: Cursor/Claude Opus --- Patch is 17.29 MiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/210547.diff 138 Files Affected: - (modified) llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp (+5-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/add.vni16.ll (+105-105) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-fma-mul.ll (+4-4) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f64.ll (+75-78) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll (+283-283) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll (+233-233) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement-stack-lower.ll (+80-80) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll (+274-274) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/load-uniform-in-vgpr.ll (+26-27) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll (+150-150) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll (+138-138) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll (+174-174) - (modified) llvm/test/CodeGen/AMDGPU/a-v-flat-atomicrmw.ll (+87-93) - (modified) llvm/test/CodeGen/AMDGPU/a-v-global-atomicrmw.ll (+87-93) - (modified) llvm/test/CodeGen/AMDGPU/add.ll (+32-32) - (modified) llvm/test/CodeGen/AMDGPU/addrspacecast.ll (+12-12) - (modified) llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll (+69450-69023) - (modified) llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll (+95-97) - (modified) llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.224bit.ll (+43-43) - (modified) llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll (+3636-3610) - (modified) llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.288bit.ll (+192-192) - (modified) llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll (+1169-1145) - (modified) llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.352bit.ll (+229-229) - (modified) llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.384bit.ll (+481-469) - (modified) llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.448bit.ll (+554-522) - (modified) llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll (+12646-12737) - (modified) llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.576bit.ll (+1323-1289) - (modified) llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.640bit.ll (+1012-973) - (modified) llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.704bit.ll (+1339-1297) - (modified) llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.768bit.ll (+1620-1561) - (modified) llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll (+2030-1962) - (modified) llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll (+3099-2920) - (modified) llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll (+3688-3557) - (modified) llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll (+28-28) - (modified) llvm/test/CodeGen/AMDGPU/av-split-dead-valno-crash.ll (+26-28) - (modified) llvm/test/CodeGen/AMDGPU/bf16.ll (+908-919) - (modified) llvm/test/CodeGen/AMDGPU/buffer-fat-pointers-contents-legalization.ll (+36-36) - (modified) llvm/test/CodeGen/AMDGPU/buffer-fat-pointers-memcpy.ll (+36-36) - (modified) llvm/test/CodeGen/AMDGPU/call-argument-types.ll (+109-109) - (modified) llvm/test/CodeGen/AMDGPU/clmul.ll (+458-458) - (modified) llvm/test/CodeGen/AMDGPU/debug-value-scheduler-crash.mir (+21-21) - (modified) llvm/test/CodeGen/AMDGPU/div_i128.ll (+235-235) - (modified) llvm/test/CodeGen/AMDGPU/div_v2i128.ll (+605-608) - (modified) llvm/test/CodeGen/AMDGPU/ds_permute_a_v.ll (+74-74) - (modified) llvm/test/CodeGen/AMDGPU/extract-subvector.ll (+31-31) - (modified) llvm/test/CodeGen/AMDGPU/fceil64.ll (+307-308) - (modified) llvm/test/CodeGen/AMDGPU/fptoi.i128.ll (+62-62) - (modified) llvm/test/CodeGen/AMDGPU/freeze.ll (+95-88) - (modified) llvm/test/CodeGen/AMDGPU/function-args-inreg.ll (+7-7) - (modified) llvm/test/CodeGen/AMDGPU/function-args.ll (+43-43) - (modified) llvm/test/CodeGen/AMDGPU/function-returns.ll (+229-229) - (modified) llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll (+23-23) - (modified) llvm/test/CodeGen/AMDGPU/gfx-callable-return-types.ll (+331-159) - (modified) llvm/test/CodeGen/AMDGPU/half.ll (+233-231) - (modified) llvm/test/CodeGen/AMDGPU/high-RP-reschedule.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/identical-subrange-spill-infloop.ll (+53-89) - (modified) llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll (+344-347) - (modified) llvm/test/CodeGen/AMDGPU/indirect-call.ll (+14-14) - (modified) llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll (+5-6) - (modified) llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2bf16.ll (+112-112) - (modified) llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll (+138-138) - (modified) llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll (+117-117) - (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.exp.large.mir (+811-810) - (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.exp.small.mir (+355-358) - (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.ll (+295-295) - (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.single.2c.mir (+6-6) - (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.ll (+34-36) - (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.ll (+319-320) - (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tensor.load.store.ll (+88-180) - (modified) llvm/test/CodeGen/AMDGPU/llvm.exp.f64.ll (+656-632) - (modified) llvm/test/CodeGen/AMDGPU/llvm.exp10.f64.ll (+582-582) - (modified) llvm/test/CodeGen/AMDGPU/llvm.exp2.f64.ll (+352-352) - (modified) llvm/test/CodeGen/AMDGPU/llvm.fma.f16.ll (+6-6) - (modified) llvm/test/CodeGen/AMDGPU/llvm.maximum.f64.ll (+14-16) - (modified) llvm/test/CodeGen/AMDGPU/llvm.minimum.f64.ll (+14-16) - (modified) llvm/test/CodeGen/AMDGPU/llvm.round.f64.ll (+39-40) - (modified) llvm/test/CodeGen/AMDGPU/load-constant-i1.ll (+2075-1734) - (modified) llvm/test/CodeGen/AMDGPU/load-constant-i16.ll (+1478-1486) - (modified) llvm/test/CodeGen/AMDGPU/load-constant-i32.ll (+423-409) - (modified) llvm/test/CodeGen/AMDGPU/load-constant-i64.ll (+48-47) - (modified) llvm/test/CodeGen/AMDGPU/load-constant-i8.ll (+1194-1201) - (modified) llvm/test/CodeGen/AMDGPU/load-global-i16.ll (+1735-1815) - (modified) llvm/test/CodeGen/AMDGPU/load-global-i32.ll (+626-753) - (modified) llvm/test/CodeGen/AMDGPU/load-global-i8.ll (+1634-1660) - (modified) llvm/test/CodeGen/AMDGPU/load-local-i16.ll (+2677-2874) - (modified) llvm/test/CodeGen/AMDGPU/machine-scheduler-rematerialization-scoring.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats.mir (+251-251) - (modified) llvm/test/CodeGen/AMDGPU/memcpy-libcall.ll (+92-90) - (modified) llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll (+1214-1209) - (modified) llvm/test/CodeGen/AMDGPU/memset-param-combinations.ll (+7-11) - (modified) llvm/test/CodeGen/AMDGPU/mfma-cd-select.ll (+30-36) - (modified) llvm/test/CodeGen/AMDGPU/mfma-no-register-aliasing.ll (+20-20) - (modified) llvm/test/CodeGen/AMDGPU/mul.ll (+23-23) - (modified) llvm/test/CodeGen/AMDGPU/mul24-pass-ordering.ll (+8-8) - (modified) llvm/test/CodeGen/AMDGPU/packed-fp32.ll (+358-350) - (modified) llvm/test/CodeGen/AMDGPU/packed-fp64.ll (+78-80) - (modified) llvm/test/CodeGen/AMDGPU/packed-u64.ll (+74-76) - (modified) llvm/test/CodeGen/AMDGPU/pr51516.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/preserve-wwm-copy-dst-reg.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll (+104-103) - (modified) llvm/test/CodeGen/AMDGPU/rem_i128.ll (+199-199) - (modified) llvm/test/CodeGen/AMDGPU/rewrite-mfma-form-spill-cost-reset.ll (+31-31) - (modified) llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr.ll (+15-18) - (modified) llvm/test/CodeGen/AMDGPU/rsq.f64.ll (+110-108) - (modified) llvm/test/CodeGen/AMDGPU/sched-assert-dead-def-subreg-use-other-subreg.mir (+10-10) - (modified) llvm/test/CodeGen/AMDGPU/sched-handleMoveUp-subreg-def-across-subreg-def.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/sched_mfma_rewrite_copies.mir (+847-847) - (modified) llvm/test/CodeGen/AMDGPU/sched_mfma_rewrite_cost.mir (+62-62) - (modified) llvm/test/CodeGen/AMDGPU/sched_mfma_rewrite_diff_types.mir (+20-20) - (modified) llvm/test/CodeGen/AMDGPU/schedule-amdgpu-trackers.ll (+4-4) - (modified) llvm/test/CodeGen/AMDGPU/schedule-barrier.mir (+13-13) - (modified) llvm/test/CodeGen/AMDGPU/schedule-regpressure-ilp-metric-spills.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/schedule-relaxed-occupancy.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/scratch-simple.ll (+452-438) - (modified) llvm/test/CodeGen/AMDGPU/sdiv.ll (+210-210) - (modified) llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll (+7-7) - (modified) llvm/test/CodeGen/AMDGPU/sema-v-unsched-bundle.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/shift-i128.ll (+18-18) - (modified) llvm/test/CodeGen/AMDGPU/shl.ll (+11-11) - (modified) llvm/test/CodeGen/AMDGPU/shl.v2i64.ll (+274-274) - (modified) llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll (+459-459) - (modified) llvm/test/CodeGen/AMDGPU/shufflevector.v4i64.v4i64.ll (+119-129) - (modified) llvm/test/CodeGen/AMDGPU/shufflevector.v4p0.v4p0.ll (+119-129) - (modified) llvm/test/CodeGen/AMDGPU/sibling-call.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/spill-agpr.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask-phi-extend.ll (+3164-1104) - (modified) llvm/test/CodeGen/AMDGPU/sra.ll (+31-31) - (modified) llvm/test/CodeGen/AMDGPU/srem.ll (+72-72) - (modified) llvm/test/CodeGen/AMDGPU/srl.ll (+11-11) - (modified) llvm/test/CodeGen/AMDGPU/udiv.ll (+20-20) - (modified) llvm/test/CodeGen/AMDGPU/unstructured-cfg-def-use-issue.ll (+5-5) - (modified) llvm/test/CodeGen/AMDGPU/vector-reduce-mul.ll (+307-307) - (modified) llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll (+82-82) - (modified) llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll (+82-82) - (modified) llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll (+82-82) - (modified) llvm/test/CodeGen/AMDGPU/vector-reduce-umin.ll (+82-82) - (modified) llvm/test/CodeGen/AMDGPU/vgpr-mark-last-scratch-load.ll (+48-50) - (modified) llvm/test/CodeGen/AMDGPU/vni8-across-blocks.ll (+36-35) ``````````diff diff --git a/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp b/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp index 078a745ee9bae..41927a3d3fe3c 100644 --- a/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp +++ b/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp @@ -788,8 +788,12 @@ GCNMaxOccupancySchedStrategy::GCNMaxOccupancySchedStrategy( SchedStages.push_back(GCNSchedStageID::UnclusteredHighRPReschedule); SchedStages.push_back(GCNSchedStageID::ClusteredLowOccupancyReschedule); SchedStages.push_back(GCNSchedStageID::PreRARematerialize); - if (IsLegacyScheduler) + // Use more accurate GCN pressure trackers. + UseGCNTrackers = true; + if (IsLegacyScheduler) { GCNTrackersOverride = std::nullopt; + UseGCNTrackers = false; + } } GCNMaxILPSchedStrategy::GCNMaxILPSchedStrategy(const MachineSchedContext *C) diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/add.vni16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/add.vni16.ll index 18f96acb268fa..d5c077cfa93e7 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/add.vni16.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/add.vni16.ll @@ -370,62 +370,62 @@ define void @addv_7i16(ptr addrspace(1) %ptra, ptr addrspace(1) %ptrb, ptr addrs ; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; GFX8-NEXT: flat_load_ushort v17, v[6:7] ; GFX8-NEXT: flat_load_ushort v18, v[8:9] -; GFX8-NEXT: flat_load_ushort v19, v[10:11] -; GFX8-NEXT: flat_load_ushort v20, v[12:13] -; GFX8-NEXT: flat_load_ushort v21, v[14:15] -; GFX8-NEXT: flat_load_ushort v22, v[0:1] +; GFX8-NEXT: flat_load_ushort v10, v[10:11] +; GFX8-NEXT: flat_load_ushort v11, v[12:13] +; GFX8-NEXT: flat_load_ushort v12, v[14:15] +; GFX8-NEXT: flat_load_ushort v13, v[0:1] ; GFX8-NEXT: v_add_u32_e32 v0, vcc, 2, v2 ; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v3, vcc ; GFX8-NEXT: v_add_u32_e32 v6, vcc, 4, v2 ; GFX8-NEXT: v_addc_u32_e32 v7, vcc, 0, v3, vcc -; GFX8-NEXT: v_add_u32_e32 v8, vcc, 6, v2 +; GFX8-NEXT: flat_load_ushort v14, v[2:3] +; GFX8-NEXT: flat_load_ushort v15, v[0:1] +; GFX8-NEXT: flat_load_ushort v19, v[6:7] +; GFX8-NEXT: v_add_u32_e32 v0, vcc, 6, v2 +; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v3, vcc +; GFX8-NEXT: v_add_u32_e32 v6, vcc, 8, v2 +; GFX8-NEXT: v_addc_u32_e32 v7, vcc, 0, v3, vcc +; GFX8-NEXT: v_add_u32_e32 v8, vcc, 10, v2 ; GFX8-NEXT: v_addc_u32_e32 v9, vcc, 0, v3, vcc -; GFX8-NEXT: v_add_u32_e32 v10, vcc, 8, v2 -; GFX8-NEXT: v_addc_u32_e32 v11, vcc, 0, v3, vcc -; GFX8-NEXT: v_add_u32_e32 v12, vcc, 10, v2 -; GFX8-NEXT: v_addc_u32_e32 v13, vcc, 0, v3, vcc -; GFX8-NEXT: v_add_u32_e32 v14, vcc, 12, v2 -; GFX8-NEXT: v_addc_u32_e32 v15, vcc, 0, v3, vcc -; GFX8-NEXT: flat_load_ushort v2, v[2:3] -; GFX8-NEXT: flat_load_ushort v3, v[0:1] +; GFX8-NEXT: v_add_u32_e32 v2, vcc, 12, v2 +; GFX8-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc +; GFX8-NEXT: flat_load_ushort v20, v[0:1] ; GFX8-NEXT: flat_load_ushort v6, v[6:7] ; GFX8-NEXT: flat_load_ushort v7, v[8:9] -; GFX8-NEXT: flat_load_ushort v8, v[10:11] -; GFX8-NEXT: flat_load_ushort v9, v[12:13] -; GFX8-NEXT: flat_load_ushort v10, v[14:15] +; GFX8-NEXT: flat_load_ushort v2, v[2:3] ; GFX8-NEXT: v_add_u32_e32 v0, vcc, 2, v4 ; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v5, vcc ; GFX8-NEXT: s_waitcnt vmcnt(6) -; GFX8-NEXT: v_add_u16_e32 v2, v16, v2 +; GFX8-NEXT: v_add_u16_e32 v3, v16, v14 ; GFX8-NEXT: s_waitcnt vmcnt(5) -; GFX8-NEXT: v_add_u16_e32 v3, v17, v3 -; GFX8-NEXT: flat_store_short v[4:5], v2 -; GFX8-NEXT: flat_store_short v[0:1], v3 +; GFX8-NEXT: v_add_u16_e32 v8, v17, v15 +; GFX8-NEXT: flat_store_short v[4:5], v3 +; GFX8-NEXT: flat_store_short v[0:1], v8 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, 4, v4 ; GFX8-NEXT: s_waitcnt vmcnt(6) -; GFX8-NEXT: v_add_u16_e32 v6, v18, v6 +; GFX8-NEXT: v_add_u16_e32 v9, v18, v19 ; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v5, vcc -; GFX8-NEXT: flat_store_short v[0:1], v6 +; GFX8-NEXT: flat_store_short v[0:1], v9 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, 6, v4 -; GFX8-NEXT: s_waitcnt vmcnt(6) -; GFX8-NEXT: v_add_u16_e32 v7, v19, v7 ; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v5, vcc -; GFX8-NEXT: flat_store_short v[0:1], v7 +; GFX8-NEXT: s_waitcnt vmcnt(6) +; GFX8-NEXT: v_add_u16_e32 v10, v10, v20 +; GFX8-NEXT: flat_store_short v[0:1], v10 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, 8, v4 ; GFX8-NEXT: s_waitcnt vmcnt(6) -; GFX8-NEXT: v_add_u16_e32 v8, v20, v8 +; GFX8-NEXT: v_add_u16_e32 v6, v11, v6 ; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v5, vcc -; GFX8-NEXT: flat_store_short v[0:1], v8 +; GFX8-NEXT: flat_store_short v[0:1], v6 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, 10, v4 ; GFX8-NEXT: s_waitcnt vmcnt(6) -; GFX8-NEXT: v_add_u16_e32 v9, v21, v9 +; GFX8-NEXT: v_add_u16_e32 v7, v12, v7 ; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v5, vcc -; GFX8-NEXT: flat_store_short v[0:1], v9 +; GFX8-NEXT: flat_store_short v[0:1], v7 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, 12, v4 ; GFX8-NEXT: s_waitcnt vmcnt(6) -; GFX8-NEXT: v_add_u16_e32 v10, v22, v10 +; GFX8-NEXT: v_add_u16_e32 v2, v13, v2 ; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v5, vcc -; GFX8-NEXT: flat_store_short v[0:1], v10 +; GFX8-NEXT: flat_store_short v[0:1], v2 ; GFX8-NEXT: s_waitcnt vmcnt(0) ; GFX8-NEXT: s_setpc_b64 s[30:31] ; @@ -532,29 +532,29 @@ define void @add_v9i16(ptr addrspace(1) %ptra, ptr addrspace(1) %ptrb, ptr addrs ; GFX8-NEXT: flat_load_dwordx4 v[10:13], v[2:3] ; GFX8-NEXT: v_add_u32_e32 v0, vcc, 16, v0 ; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc -; GFX8-NEXT: flat_load_ushort v14, v[0:1] +; GFX8-NEXT: flat_load_ushort v16, v[0:1] ; GFX8-NEXT: v_add_u32_e32 v0, vcc, 16, v2 ; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v3, vcc ; GFX8-NEXT: flat_load_ushort v0, v[0:1] +; GFX8-NEXT: v_add_u32_e32 v14, vcc, 16, v4 +; GFX8-NEXT: v_addc_u32_e32 v15, vcc, 0, v5, vcc ; GFX8-NEXT: s_waitcnt vmcnt(2) ; GFX8-NEXT: v_add_u16_e32 v1, v6, v10 ; GFX8-NEXT: v_add_u16_sdwa v2, v6, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 ; GFX8-NEXT: v_add_u16_e32 v3, v7, v11 -; GFX8-NEXT: v_add_u16_sdwa v10, v7, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 -; GFX8-NEXT: v_add_u16_e32 v11, v8, v12 +; GFX8-NEXT: v_add_u16_sdwa v6, v7, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 +; GFX8-NEXT: v_add_u16_e32 v7, v8, v12 ; GFX8-NEXT: v_add_u16_sdwa v8, v8, v12 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 -; GFX8-NEXT: v_add_u16_e32 v12, v9, v13 +; GFX8-NEXT: v_add_u16_e32 v10, v9, v13 ; GFX8-NEXT: v_add_u16_sdwa v9, v9, v13 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 -; GFX8-NEXT: v_add_u32_e32 v6, vcc, 16, v4 ; GFX8-NEXT: s_waitcnt vmcnt(0) -; GFX8-NEXT: v_add_u16_e32 v13, v14, v0 +; GFX8-NEXT: v_add_u16_e32 v11, v16, v0 ; GFX8-NEXT: v_or_b32_e32 v0, v1, v2 -; GFX8-NEXT: v_or_b32_e32 v1, v3, v10 -; GFX8-NEXT: v_or_b32_e32 v2, v11, v8 -; GFX8-NEXT: v_or_b32_e32 v3, v12, v9 -; GFX8-NEXT: v_addc_u32_e32 v7, vcc, 0, v5, vcc +; GFX8-NEXT: v_or_b32_e32 v1, v3, v6 +; GFX8-NEXT: v_or_b32_e32 v2, v7, v8 +; GFX8-NEXT: v_or_b32_e32 v3, v10, v9 ; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3] -; GFX8-NEXT: flat_store_short v[6:7], v13 +; GFX8-NEXT: flat_store_short v[14:15], v11 ; GFX8-NEXT: s_waitcnt vmcnt(0) ; GFX8-NEXT: s_setpc_b64 s[30:31] ; @@ -685,55 +685,55 @@ define void @add_v11i16(ptr addrspace(1) %ptra, ptr addrspace(1) %ptrb, ptr addr ; GFX8-LABEL: add_v11i16: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_add_u32_e32 v14, vcc, 16, v0 +; GFX8-NEXT: v_addc_u32_e32 v15, vcc, 0, v1, vcc +; GFX8-NEXT: v_add_u32_e32 v16, vcc, 18, v0 +; GFX8-NEXT: v_addc_u32_e32 v17, vcc, 0, v1, vcc ; GFX8-NEXT: flat_load_dwordx4 v[6:9], v[0:1] -; GFX8-NEXT: flat_load_dwordx4 v[10:13], v[2:3] -; GFX8-NEXT: v_add_u32_e32 v14, vcc, 16, v2 -; GFX8-NEXT: v_addc_u32_e32 v15, vcc, 0, v3, vcc -; GFX8-NEXT: v_add_u32_e32 v16, vcc, 18, v2 -; GFX8-NEXT: v_addc_u32_e32 v17, vcc, 0, v3, vcc -; GFX8-NEXT: v_add_u32_e32 v2, vcc, 20, v2 -; GFX8-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc -; GFX8-NEXT: flat_load_ushort v14, v[14:15] -; GFX8-NEXT: flat_load_ushort v15, v[16:17] -; GFX8-NEXT: flat_load_ushort v16, v[2:3] -; GFX8-NEXT: v_add_u32_e32 v2, vcc, 16, v0 -; GFX8-NEXT: v_addc_u32_e32 v3, vcc, 0, v1, vcc -; GFX8-NEXT: s_waitcnt vmcnt(3) -; GFX8-NEXT: v_add_u16_e32 v17, v6, v10 -; GFX8-NEXT: v_add_u16_sdwa v10, v6, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 -; GFX8-NEXT: v_add_u32_e32 v6, vcc, 18, v0 -; GFX8-NEXT: v_add_u16_e32 v18, v7, v11 -; GFX8-NEXT: v_add_u16_sdwa v11, v7, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 -; GFX8-NEXT: v_addc_u32_e32 v7, vcc, 0, v1, vcc ; GFX8-NEXT: v_add_u32_e32 v0, vcc, 20, v0 -; GFX8-NEXT: flat_load_ushort v2, v[2:3] -; GFX8-NEXT: flat_load_ushort v3, v[6:7] ; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc -; GFX8-NEXT: flat_load_ushort v21, v[0:1] -; GFX8-NEXT: v_add_u32_e32 v6, vcc, 16, v4 -; GFX8-NEXT: v_addc_u32_e32 v7, vcc, 0, v5, vcc -; GFX8-NEXT: v_add_u16_e32 v19, v8, v12 +; GFX8-NEXT: flat_load_dwordx4 v[10:13], v[2:3] +; GFX8-NEXT: flat_load_ushort v18, v[14:15] +; GFX8-NEXT: flat_load_ushort v16, v[16:17] +; GFX8-NEXT: flat_load_ushort v17, v[0:1] +; GFX8-NEXT: v_add_u32_e32 v0, vcc, 16, v2 +; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v3, vcc +; GFX8-NEXT: v_add_u32_e32 v14, vcc, 18, v2 +; GFX8-NEXT: v_addc_u32_e32 v15, vcc, 0, v3, vcc +; GFX8-NEXT: flat_load_ushort v19, v[0:1] +; GFX8-NEXT: flat_load_ushort v20, v[14:15] +; GFX8-NEXT: v_add_u32_e32 v0, vcc, 20, v2 +; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v3, vcc +; GFX8-NEXT: flat_load_ushort v0, v[0:1] +; GFX8-NEXT: v_add_u32_e32 v14, vcc, 16, v4 +; GFX8-NEXT: v_addc_u32_e32 v15, vcc, 0, v5, vcc +; GFX8-NEXT: s_waitcnt vmcnt(6) +; GFX8-NEXT: v_add_u16_e32 v1, v6, v10 +; GFX8-NEXT: v_add_u16_sdwa v2, v6, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 +; GFX8-NEXT: v_add_u32_e32 v6, vcc, 18, v4 +; GFX8-NEXT: v_add_u16_e32 v3, v7, v11 +; GFX8-NEXT: v_add_u16_sdwa v10, v7, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 +; GFX8-NEXT: v_add_u16_e32 v11, v8, v12 ; GFX8-NEXT: v_add_u16_sdwa v12, v8, v12 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 -; GFX8-NEXT: v_add_u32_e32 v8, vcc, 18, v4 -; GFX8-NEXT: v_add_u16_e32 v20, v9, v13 +; GFX8-NEXT: v_add_u16_e32 v21, v9, v13 ; GFX8-NEXT: v_add_u16_sdwa v13, v9, v13 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 -; GFX8-NEXT: v_addc_u32_e32 v9, vcc, 0, v5, vcc -; GFX8-NEXT: v_or_b32_e32 v0, v17, v10 -; GFX8-NEXT: v_or_b32_e32 v1, v18, v11 -; GFX8-NEXT: v_add_u32_e32 v10, vcc, 20, v4 -; GFX8-NEXT: v_addc_u32_e32 v11, vcc, 0, v5, vcc +; GFX8-NEXT: v_addc_u32_e32 v7, vcc, 0, v5, vcc +; GFX8-NEXT: v_add_u32_e32 v8, vcc, 20, v4 ; GFX8-NEXT: s_waitcnt vmcnt(2) -; GFX8-NEXT: v_add_u16_e32 v14, v2, v14 +; GFX8-NEXT: v_add_u16_e32 v18, v18, v19 ; GFX8-NEXT: s_waitcnt vmcnt(1) -; GFX8-NEXT: v_add_u16_e32 v15, v3, v15 -; GFX8-NEXT: v_or_b32_e32 v2, v19, v12 -; GFX8-NEXT: v_or_b32_e32 v3, v20, v13 +; GFX8-NEXT: v_add_u16_e32 v16, v16, v20 +; GFX8-NEXT: v_addc_u32_e32 v9, vcc, 0, v5, vcc ; GFX8-NEXT: s_waitcnt vmcnt(0) -; GFX8-NEXT: v_add_u16_e32 v16, v21, v16 +; GFX8-NEXT: v_add_u16_e32 v17, v17, v0 +; GFX8-NEXT: v_or_b32_e32 v0, v1, v2 +; GFX8-NEXT: v_or_b32_e32 v1, v3, v10 +; GFX8-NEXT: v_or_b32_e32 v2, v11, v12 +; GFX8-NEXT: v_or_b32_e32 v3, v21, v13 ; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3] -; GFX8-NEXT: flat_store_short v[6:7], v14 -; GFX8-NEXT: flat_store_short v[8:9], v15 -; GFX8-NEXT: flat_store_short v[10:11], v16 +; GFX8-NEXT: flat_store_short v[14:15], v18 +; GFX8-NEXT: flat_store_short v[6:7], v16 +; GFX8-NEXT: flat_store_short v[8:9], v17 ; GFX8-NEXT: s_waitcnt vmcnt(0) ; GFX8-NEXT: s_setpc_b64 s[30:31] ; @@ -825,34 +825,34 @@ define void @add_v12i16(ptr addrspace(1) %ptra, ptr addrspace(1) %ptrb, ptr addr ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX8-NEXT: flat_load_dwordx4 v[6:9], v[0:1] ; GFX8-NEXT: flat_load_dwordx4 v[10:13], v[2:3] -; GFX8-NEXT: v_add_u32_e32 v2, vcc, 16, v2 -; GFX8-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc ; GFX8-NEXT: v_add_u32_e32 v0, vcc, 16, v0 ; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc -; GFX8-NEXT: flat_load_dwordx2 v[14:15], v[2:3] -; GFX8-NEXT: s_waitcnt vmcnt(1) -; GFX8-NEXT: v_add_u16_e32 v2, v6, v10 -; GFX8-NEXT: v_add_u16_sdwa v3, v6, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 -; GFX8-NEXT: v_add_u16_e32 v10, v7, v11 -; GFX8-NEXT: v_add_u16_sdwa v11, v7, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 -; GFX8-NEXT: flat_load_dwordx2 v[6:7], v[0:1] -; GFX8-NEXT: v_add_u16_e32 v16, v8, v12 -; GFX8-NEXT: v_add_u16_sdwa v8, v8, v12 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 -; GFX8-NEXT: v_add_u16_e32 v12, v9, v13 +; GFX8-NEXT: flat_load_dwordx2 v[14:15], v[0:1] +; GFX8-NEXT: v_add_u32_e32 v0, vcc, 16, v2 +; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v3, vcc +; GFX8-NEXT: flat_load_dwordx2 v[16:17], v[0:1] +; GFX8-NEXT: s_waitcnt vmcnt(2) +; GFX8-NEXT: v_add_u16_e32 v0, v6, v10 +; GFX8-NEXT: v_add_u16_sdwa v1, v6, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 +; GFX8-NEXT: v_add_u16_e32 v2, v7, v11 +; GFX8-NEXT: v_add_u16_sdwa v3, v7, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 +; GFX8-NEXT: v_add_u16_e32 v6, v8, v12 +; GFX8-NEXT: v_add_u16_sdwa v7, v8, v12 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 +; GFX8-NEXT: v_add_u16_e32 v8, v9, v13 ; GFX8-NEXT: v_add_u16_sdwa v9, v9, v13 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 -; GFX8-NEXT: v_or_b32_e32 v0, v2, v3 -; GFX8-NEXT: v_or_b32_e32 v1, v10, v11 -; GFX8-NEXT: v_or_b32_e32 v2, v16, v8 -; GFX8-NEXT: v_or_b32_e32 v3, v12, v9 +; GFX8-NEXT: v_or_b32_e32 v0, v0, v1 +; GFX8-NEXT: v_or_b32_e32 v1, v2, v3 +; GFX8-NEXT: v_or_b32_e32 v2, v6, v7 +; GFX8-NEXT: v_or_b32_e32 v3, v8, v9 +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: v_add_u16_e32 v6, v14, v16 +; GFX8-NEXT: v_add_u16_sdwa v7, v14, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 +; GFX8-NEXT: v_add_u16_e32 v8, v15, v17 +; GFX8-NEXT: v_add_u16_sdwa v9, v15, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 ; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3] -; GFX8-NEXT: s_waitcnt vmcnt(1) -; GFX8-NEXT: v_add_u16_e32 v8, v6, v14 -; GFX8-NEXT: v_add_u16_sdwa v6, v6, v14 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 -; GFX8-NEXT: v_add_u16_e32 v9, v7, v15 -; GFX8-NEXT: v_add_u16_sdwa v7, v7, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 +; GFX8-NEXT: v_or_b32_e32 v6, v6, v7 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, 16, v4 -; GFX8-NEXT: v_or_b32_e32 v6, v8, v6 -; GFX8-NEXT: v_or_b32_e32 v7, v9, v7 +; GFX8-NEXT: v_or_b32_e32 v7, v8, v9 ; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v5, vcc ; GFX8-NEXT: flat_store_dwordx2 v[0:1], v[6:7] ; GFX8-NEXT: s_waitcnt vmcnt(0) diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-fma-mul.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-fma-mul.ll index c575bc4e5e129..33f1fe6b60a81 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-fma-mul.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-fma-mul.ll @@ -751,8 +751,8 @@ define <4 x double> @test_f64_add_mul(<4 x double> %a, <4 x double> %b, <4 x dou ; GFX9-CONTRACT-NEXT: v_fma_f64 v[2:3], v[2:3], v[10:11], v[18:19] ; GFX9-CONTRACT-NEXT: s_waitcnt vmcnt(0) ; GFX9-CONTRACT-NEXT: v_fma_f64 v[20:21], v[20:21], v[28:29], v[24:25] -; GFX9-CONTRACT-NEXT: buffer_load_dword v31, off, s[0:3], s32 ; GFX9-CONTRACT-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:28 +; GFX9-CONTRACT-NEXT: buffer_load_dword v31, off, s[0:3], s32 ; GFX9-CONTRACT-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:32 ; GFX9-CONTRACT-NEXT: v_fma_f64 v[4:5], v[4:5], v[12:13], v[20:21] ; GFX9-CONTRACT-NEXT: s_waitcnt vmcnt(0) @@ -777,8 +777,8 @@ define <4 x double> @test_f64_add_mul(<4 x double> %a, <4 x double> %b, <4 x dou ; GFX9-DENORM-NEXT: v_fma_f64 v[2:3], v[2:3], v[10:11], v[18:19] ; GFX9-DENORM-NEXT: s_waitcnt vmcnt(0) ; GFX9-DENORM-NEXT: v_fma_f64 v[20:21], v[20:21], v[28:29], v[24:25] -; GFX9-DENORM-NEXT: buffer_load_dword v31, off, s[0:3], s32 ; GFX9-DENORM-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:28 +; GFX9-DENORM-NEXT: buffer_load_dword v31, off, s[0:3], s32 ; GFX9-DENORM-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:32 ; GFX9-DENORM-NEXT: v_fma_f64 v[4:5], v[4:5], v[12:13], v[20:21] ; GFX9-DENORM-NEXT: s_waitcnt vmcnt(0) @@ -922,8 +922,8 @@ define <4 x double> @test_f64_add_mul_rhs(<4 x double> %a, <4 x double> %b, <4 x ; GFX9-CONTRACT-NEXT: v_fma_f64 v[2:3], v[2:3], v[10:11], v[18:19] ; GFX9-CONTRACT-NEXT: s_waitcnt vmcnt(0) ; GFX9-CONTRACT-NEXT: v_fma_f64 v[20:21], v[20:21], v[28:29], v[24:25] -; GFX9-CONTRACT-NEXT: buffer_load_dword v31, off, s[0:3], s32 ; GFX9-CONTRACT-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:28 +; GFX9-CONTRACT-NEXT: buffer_load_dword v31, off, s[0:3], s32 ; GFX9-CONTRACT-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:32 ; GFX9-CONTRACT-NEXT: v_fma_f64 v[4:5], v[4:5], v[12:13], v[20:21] ; GFX9-CONTRACT-NEXT: s_waitcnt vmcnt(0) @@ -948,8 +948,8 @@ define <4 x double> @test_f64_add_mul_rhs(<4 x double> %a, <4 x double> %b, <4 x ; GFX9-DENORM-NEXT: v_fma_f64 v[2:3], v[2:3], v[10:11], v[18:19] ; GFX9-DENORM-NEXT: s_waitcnt vmcnt(0) ; GFX9-DENORM-NEXT: v_fma_f64 v[20:21], v[20:21], v[28:29], v[24:25] -; GFX9-DENORM-NEXT: buffer_load_dword v31, off, s[0:3], s32 ; GFX9-DENORM-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:28 +; GFX9-DENORM-NEXT: buffer_load_dword v31, off, s[0:3], s32 ; GFX9-DENORM-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:32 ; GFX9-DENORM-NEXT: v_fma_f64 v[4:5], v[4:5], v[12:13], v[20:21] ; GFX9-DENORM-NEXT: s_waitcnt vmcnt(0) diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f64.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f64.ll index 958dd4cce4424..52df703747c87 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f64.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f64.ll @@ -757,9 +757,9 @@ define <2 x double> @v_fdiv_v2f64(<2 x double> %a, <2 x double> %b) { ; GFX6-NEXT: v_fma_f64 v[16:17], -v[12:13], v[14:15], 1.0 ; GFX6-NEXT: v_fma_f64 v[14:15], v[14:15], v[16:17], v[14:15] ; GFX6-NEXT: v_mul_f64 v[16:17], v[18:19], v[10:11] -; GFX6-NEXT: v_fma_f64 v[18:19], -v[8:9], v[16:17], v[18:19] +; GFX6-NEXT: v_fma_f64 v[20:21], -v[8:9], v[16:17], v[18:19] ; GFX6-NEXT: v_fma_f64 v[8:9], -v[12:13], v[14:15], 1.0 -; GFX6-NEXT: v_div_fmas_f64 v[10:11], v[18:19], v[10:11], v[16:17] +; GFX6-NEXT: v_div_fmas_f64 v[10:11], v[20:21], v[10:11], v[16:17] ; GFX6-NEXT: v_fma_f64 v[8:9], v[14:15], v[8:9], v[14:15] ; GFX6-NEXT: v_div_scale_f64 v[14:15], s[6:7], v[2:3], v[6:7], v[2:3] ; GFX6-NEXT: v_div_fixup_f64 v[0:1], v[10:11], v[4:5], v[0:1] @@ -990,9 +990,9 @@ define <2 x double> @v_fdiv_v2f64_ulp25(<2 x double> %a, <2 x double> %b) { ; GFX6-NEXT: v_fma_f64 v[16:17], -v[12:13], v[14:15], 1.0 ; GFX6-NEXT: v_fma_f64 v[14:15], v[14:15], v[16:17], v[14:15] ; GFX6-NEXT: v_mul_f64 v[16:17], v[18:19], v[10:11] -; GFX6-NEXT: v_fma_f64 v[18:19], -v[8:9], v[16:17], v[18:19] +; GFX6-NEXT: v_fma_f64 v[20:21], -v[8:9], v[16:17], v[18:19] ; GFX6-NEXT: v_fma_f64 v[8:9], -v[12:13], v[14:15], 1.0 -; GFX6-NEXT: v_div_fmas_f64 v[10:11]... [truncated] `````````` </details> https://github.com/llvm/llvm-project/pull/210547 _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
