https://github.com/petar-avramovic updated https://github.com/llvm/llvm-project/pull/210098
>From b53a2f4815899a6bfb992838a7fed9c0b068d1e3 Mon Sep 17 00:00:00 2001 From: Petar Avramovic <[email protected]> Date: Thu, 16 Jul 2026 18:11:39 +0200 Subject: [PATCH] AMDGPU/GlobalISel: Use integers for read-any-lane split type --- .../Target/AMDGPU/AMDGPUGlobalISelUtils.cpp | 2 +- .../AMDGPU/GlobalISel/regbankselect-call.ll | 16 +- .../AMDGPU/GlobalISel/regbankselect-fpext.mir | 8 +- .../AMDGPU/GlobalISel/regbankselect-load.mir | 212 ++++++++--------- .../GlobalISel/regbankselect-salu-float.mir | 24 +- .../regbankselect-waterfall-call.mir | 32 +-- llvm/test/CodeGen/AMDGPU/indirect-call.ll | 48 ++-- .../AMDGPU/llvm.amdgcn.inverse.ballot.i64.ll | 18 +- .../CodeGen/AMDGPU/llvm.amdgcn.quadmask.ll | 2 +- .../AMDGPU/llvm.amdgcn.s.prefetch.data.ll | 50 ++-- .../AMDGPU/llvm.amdgcn.s.prefetch.inst.ll | 222 ++++++++++++------ llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wqm.ll | 2 +- 12 files changed, 364 insertions(+), 272 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/AMDGPUGlobalISelUtils.cpp b/llvm/lib/Target/AMDGPU/AMDGPUGlobalISelUtils.cpp index f36935d8c0e8f..9dce9df2ad99f 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUGlobalISelUtils.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUGlobalISelUtils.cpp @@ -114,7 +114,7 @@ static LLT getReadAnyLaneSplitTy(LLT Ty) { } // Large scalars and 64-bit pointers - return LLT::scalar(32); + return LLT::integer(32); } template <typename ReadLaneFnTy> diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-call.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-call.ll index 906b291cb73ac..b9afd0dbdb7d7 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-call.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-call.ll @@ -35,10 +35,10 @@ define amdgpu_ps void @test_divergent_indirect_call_p0(ptr %fptr) { ; CHECK-NEXT: bb.2: ; CHECK-NEXT: successors: %bb.3(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[MV]](p0) - ; CHECK-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[UV]](s32) - ; CHECK-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:sgpr(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[UV1]](s32) - ; CHECK-NEXT: [[MV1:%[0-9]+]]:sgpr(p0) = G_MERGE_VALUES [[INTRINSIC_CONVERGENT]](s32), [[INTRINSIC_CONVERGENT1]](s32) + ; CHECK-NEXT: [[UV:%[0-9]+]]:vgpr(i32), [[UV1:%[0-9]+]]:vgpr(i32) = G_UNMERGE_VALUES [[MV]](p0) + ; CHECK-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[UV]](i32) + ; CHECK-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[UV1]](i32) + ; CHECK-NEXT: [[MV1:%[0-9]+]]:sgpr(p0) = G_MERGE_VALUES [[INTRINSIC_CONVERGENT]](i32), [[INTRINSIC_CONVERGENT1]](i32) ; CHECK-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[MV1]](p0), [[MV]] ; CHECK-NEXT: [[INTRINSIC_CONVERGENT2:%[0-9]+]]:sreg_64_xexec(i64) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.ballot), [[ICMP]](s1) ; CHECK-NEXT: [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[INTRINSIC_CONVERGENT2]](i64), implicit-def $exec, implicit-def $scc, implicit $exec @@ -81,10 +81,10 @@ define amdgpu_ps i32 @test_divergent_indirect_call_p0_with_args(ptr %fptr, i32 % ; CHECK-NEXT: bb.2: ; CHECK-NEXT: successors: %bb.3(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[MV]](p0) - ; CHECK-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[UV]](s32) - ; CHECK-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:sgpr(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[UV1]](s32) - ; CHECK-NEXT: [[MV1:%[0-9]+]]:sgpr(p0) = G_MERGE_VALUES [[INTRINSIC_CONVERGENT]](s32), [[INTRINSIC_CONVERGENT1]](s32) + ; CHECK-NEXT: [[UV:%[0-9]+]]:vgpr(i32), [[UV1:%[0-9]+]]:vgpr(i32) = G_UNMERGE_VALUES [[MV]](p0) + ; CHECK-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[UV]](i32) + ; CHECK-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[UV1]](i32) + ; CHECK-NEXT: [[MV1:%[0-9]+]]:sgpr(p0) = G_MERGE_VALUES [[INTRINSIC_CONVERGENT]](i32), [[INTRINSIC_CONVERGENT1]](i32) ; CHECK-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[MV1]](p0), [[MV]] ; CHECK-NEXT: [[INTRINSIC_CONVERGENT2:%[0-9]+]]:sreg_64_xexec(i64) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.ballot), [[ICMP]](s1) ; CHECK-NEXT: [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[INTRINSIC_CONVERGENT2]](i64), implicit-def $exec, implicit-def $scc, implicit $exec diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fpext.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fpext.mir index f855f0d88a7db..9c621513365ad 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fpext.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fpext.mir @@ -15,10 +15,10 @@ body: | ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32) ; CHECK-NEXT: [[FPEXT:%[0-9]+]]:vgpr(s64) = G_FPEXT [[COPY1]](s32) - ; CHECK-NEXT: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[FPEXT]](s64) - ; CHECK-NEXT: [[AMDGPU_READANYLANE:%[0-9]+]]:sgpr(s32) = G_AMDGPU_READANYLANE [[UV]] - ; CHECK-NEXT: [[AMDGPU_READANYLANE1:%[0-9]+]]:sgpr(s32) = G_AMDGPU_READANYLANE [[UV1]] - ; CHECK-NEXT: [[MV:%[0-9]+]]:sgpr(s64) = G_MERGE_VALUES [[AMDGPU_READANYLANE]](s32), [[AMDGPU_READANYLANE1]](s32) + ; CHECK-NEXT: [[UV:%[0-9]+]]:vgpr(i32), [[UV1:%[0-9]+]]:vgpr(i32) = G_UNMERGE_VALUES [[FPEXT]](s64) + ; CHECK-NEXT: [[AMDGPU_READANYLANE:%[0-9]+]]:sgpr(i32) = G_AMDGPU_READANYLANE [[UV]] + ; CHECK-NEXT: [[AMDGPU_READANYLANE1:%[0-9]+]]:sgpr(i32) = G_AMDGPU_READANYLANE [[UV1]] + ; CHECK-NEXT: [[MV:%[0-9]+]]:sgpr(s64) = G_MERGE_VALUES [[AMDGPU_READANYLANE]](i32), [[AMDGPU_READANYLANE1]](i32) %0:_(s32) = COPY $sgpr0 %1:_(s64) = G_FPEXT %0 ... diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir index 19acdc799bce8..e017b62c85dd7 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir @@ -157,22 +157,22 @@ body: | ; GCN-NEXT: [[LOAD1:%[0-9]+]]:vgpr(<2 x s64>) = G_LOAD [[PTR_ADD]](p1) :: (load (<2 x s64>) from %ir.global.not.uniform.v4i64 + 16, basealign 32, addrspace 1) ; GCN-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<4 x s64>) = G_CONCAT_VECTORS [[LOAD]](<2 x s64>), [[LOAD1]](<2 x s64>) ; GCN-NEXT: [[UV:%[0-9]+]]:vgpr(s64), [[UV1:%[0-9]+]]:vgpr(s64), [[UV2:%[0-9]+]]:vgpr(s64), [[UV3:%[0-9]+]]:vgpr(s64) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<4 x s64>) - ; GCN-NEXT: [[UV4:%[0-9]+]]:vgpr(s32), [[UV5:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[UV]](s64) - ; GCN-NEXT: [[AMDGPU_READANYLANE:%[0-9]+]]:sgpr(s32) = G_AMDGPU_READANYLANE [[UV4]] - ; GCN-NEXT: [[AMDGPU_READANYLANE1:%[0-9]+]]:sgpr(s32) = G_AMDGPU_READANYLANE [[UV5]] - ; GCN-NEXT: [[MV:%[0-9]+]]:sgpr(s64) = G_MERGE_VALUES [[AMDGPU_READANYLANE]](s32), [[AMDGPU_READANYLANE1]](s32) - ; GCN-NEXT: [[UV6:%[0-9]+]]:vgpr(s32), [[UV7:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[UV1]](s64) - ; GCN-NEXT: [[AMDGPU_READANYLANE2:%[0-9]+]]:sgpr(s32) = G_AMDGPU_READANYLANE [[UV6]] - ; GCN-NEXT: [[AMDGPU_READANYLANE3:%[0-9]+]]:sgpr(s32) = G_AMDGPU_READANYLANE [[UV7]] - ; GCN-NEXT: [[MV1:%[0-9]+]]:sgpr(s64) = G_MERGE_VALUES [[AMDGPU_READANYLANE2]](s32), [[AMDGPU_READANYLANE3]](s32) - ; GCN-NEXT: [[UV8:%[0-9]+]]:vgpr(s32), [[UV9:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[UV2]](s64) - ; GCN-NEXT: [[AMDGPU_READANYLANE4:%[0-9]+]]:sgpr(s32) = G_AMDGPU_READANYLANE [[UV8]] - ; GCN-NEXT: [[AMDGPU_READANYLANE5:%[0-9]+]]:sgpr(s32) = G_AMDGPU_READANYLANE [[UV9]] - ; GCN-NEXT: [[MV2:%[0-9]+]]:sgpr(s64) = G_MERGE_VALUES [[AMDGPU_READANYLANE4]](s32), [[AMDGPU_READANYLANE5]](s32) - ; GCN-NEXT: [[UV10:%[0-9]+]]:vgpr(s32), [[UV11:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[UV3]](s64) - ; GCN-NEXT: [[AMDGPU_READANYLANE6:%[0-9]+]]:sgpr(s32) = G_AMDGPU_READANYLANE [[UV10]] - ; GCN-NEXT: [[AMDGPU_READANYLANE7:%[0-9]+]]:sgpr(s32) = G_AMDGPU_READANYLANE [[UV11]] - ; GCN-NEXT: [[MV3:%[0-9]+]]:sgpr(s64) = G_MERGE_VALUES [[AMDGPU_READANYLANE6]](s32), [[AMDGPU_READANYLANE7]](s32) + ; GCN-NEXT: [[UV4:%[0-9]+]]:vgpr(i32), [[UV5:%[0-9]+]]:vgpr(i32) = G_UNMERGE_VALUES [[UV]](s64) + ; GCN-NEXT: [[AMDGPU_READANYLANE:%[0-9]+]]:sgpr(i32) = G_AMDGPU_READANYLANE [[UV4]] + ; GCN-NEXT: [[AMDGPU_READANYLANE1:%[0-9]+]]:sgpr(i32) = G_AMDGPU_READANYLANE [[UV5]] + ; GCN-NEXT: [[MV:%[0-9]+]]:sgpr(s64) = G_MERGE_VALUES [[AMDGPU_READANYLANE]](i32), [[AMDGPU_READANYLANE1]](i32) + ; GCN-NEXT: [[UV6:%[0-9]+]]:vgpr(i32), [[UV7:%[0-9]+]]:vgpr(i32) = G_UNMERGE_VALUES [[UV1]](s64) + ; GCN-NEXT: [[AMDGPU_READANYLANE2:%[0-9]+]]:sgpr(i32) = G_AMDGPU_READANYLANE [[UV6]] + ; GCN-NEXT: [[AMDGPU_READANYLANE3:%[0-9]+]]:sgpr(i32) = G_AMDGPU_READANYLANE [[UV7]] + ; GCN-NEXT: [[MV1:%[0-9]+]]:sgpr(s64) = G_MERGE_VALUES [[AMDGPU_READANYLANE2]](i32), [[AMDGPU_READANYLANE3]](i32) + ; GCN-NEXT: [[UV8:%[0-9]+]]:vgpr(i32), [[UV9:%[0-9]+]]:vgpr(i32) = G_UNMERGE_VALUES [[UV2]](s64) + ; GCN-NEXT: [[AMDGPU_READANYLANE4:%[0-9]+]]:sgpr(i32) = G_AMDGPU_READANYLANE [[UV8]] + ; GCN-NEXT: [[AMDGPU_READANYLANE5:%[0-9]+]]:sgpr(i32) = G_AMDGPU_READANYLANE [[UV9]] + ; GCN-NEXT: [[MV2:%[0-9]+]]:sgpr(s64) = G_MERGE_VALUES [[AMDGPU_READANYLANE4]](i32), [[AMDGPU_READANYLANE5]](i32) + ; GCN-NEXT: [[UV10:%[0-9]+]]:vgpr(i32), [[UV11:%[0-9]+]]:vgpr(i32) = G_UNMERGE_VALUES [[UV3]](s64) + ; GCN-NEXT: [[AMDGPU_READANYLANE6:%[0-9]+]]:sgpr(i32) = G_AMDGPU_READANYLANE [[UV10]] + ; GCN-NEXT: [[AMDGPU_READANYLANE7:%[0-9]+]]:sgpr(i32) = G_AMDGPU_READANYLANE [[UV11]] + ; GCN-NEXT: [[MV3:%[0-9]+]]:sgpr(s64) = G_MERGE_VALUES [[AMDGPU_READANYLANE6]](i32), [[AMDGPU_READANYLANE7]](i32) ; GCN-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s64>) = G_BUILD_VECTOR [[MV]](s64), [[MV1]](s64), [[MV2]](s64), [[MV3]](s64) %0:_(p1) = COPY $sgpr0_sgpr1 %1:_(<4 x s64>) = G_LOAD %0 :: (load (<4 x s64>) from %ir.global.not.uniform.v4i64) @@ -247,38 +247,38 @@ body: | ; GCN-NEXT: [[LOAD3:%[0-9]+]]:vgpr(<2 x s64>) = G_LOAD [[PTR_ADD2]](p1) :: (load (<2 x s64>) from %ir.global.not.uniform.v8i64 + 48, basealign 64, addrspace 1) ; GCN-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<8 x s64>) = G_CONCAT_VECTORS [[LOAD]](<2 x s64>), [[LOAD1]](<2 x s64>), [[LOAD2]](<2 x s64>), [[LOAD3]](<2 x s64>) ; GCN-NEXT: [[UV:%[0-9]+]]:vgpr(s64), [[UV1:%[0-9]+]]:vgpr(s64), [[UV2:%[0-9]+]]:vgpr(s64), [[UV3:%[0-9]+]]:vgpr(s64), [[UV4:%[0-9]+]]:vgpr(s64), [[UV5:%[0-9]+]]:vgpr(s64), [[UV6:%[0-9]+]]:vgpr(s64), [[UV7:%[0-9]+]]:vgpr(s64) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<8 x s64>) - ; GCN-NEXT: [[UV8:%[0-9]+]]:vgpr(s32), [[UV9:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[UV]](s64) - ; GCN-NEXT: [[AMDGPU_READANYLANE:%[0-9]+]]:sgpr(s32) = G_AMDGPU_READANYLANE [[UV8]] - ; GCN-NEXT: [[AMDGPU_READANYLANE1:%[0-9]+]]:sgpr(s32) = G_AMDGPU_READANYLANE [[UV9]] - ; GCN-NEXT: [[MV:%[0-9]+]]:sgpr(s64) = G_MERGE_VALUES [[AMDGPU_READANYLANE]](s32), [[AMDGPU_READANYLANE1]](s32) - ; GCN-NEXT: [[UV10:%[0-9]+]]:vgpr(s32), [[UV11:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[UV1]](s64) - ; GCN-NEXT: [[AMDGPU_READANYLANE2:%[0-9]+]]:sgpr(s32) = G_AMDGPU_READANYLANE [[UV10]] - ; GCN-NEXT: [[AMDGPU_READANYLANE3:%[0-9]+]]:sgpr(s32) = G_AMDGPU_READANYLANE [[UV11]] - ; GCN-NEXT: [[MV1:%[0-9]+]]:sgpr(s64) = G_MERGE_VALUES [[AMDGPU_READANYLANE2]](s32), [[AMDGPU_READANYLANE3]](s32) - ; GCN-NEXT: [[UV12:%[0-9]+]]:vgpr(s32), [[UV13:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[UV2]](s64) - ; GCN-NEXT: [[AMDGPU_READANYLANE4:%[0-9]+]]:sgpr(s32) = G_AMDGPU_READANYLANE [[UV12]] - ; GCN-NEXT: [[AMDGPU_READANYLANE5:%[0-9]+]]:sgpr(s32) = G_AMDGPU_READANYLANE [[UV13]] - ; GCN-NEXT: [[MV2:%[0-9]+]]:sgpr(s64) = G_MERGE_VALUES [[AMDGPU_READANYLANE4]](s32), [[AMDGPU_READANYLANE5]](s32) - ; GCN-NEXT: [[UV14:%[0-9]+]]:vgpr(s32), [[UV15:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[UV3]](s64) - ; GCN-NEXT: [[AMDGPU_READANYLANE6:%[0-9]+]]:sgpr(s32) = G_AMDGPU_READANYLANE [[UV14]] - ; GCN-NEXT: [[AMDGPU_READANYLANE7:%[0-9]+]]:sgpr(s32) = G_AMDGPU_READANYLANE [[UV15]] - ; GCN-NEXT: [[MV3:%[0-9]+]]:sgpr(s64) = G_MERGE_VALUES [[AMDGPU_READANYLANE6]](s32), [[AMDGPU_READANYLANE7]](s32) - ; GCN-NEXT: [[UV16:%[0-9]+]]:vgpr(s32), [[UV17:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[UV4]](s64) - ; GCN-NEXT: [[AMDGPU_READANYLANE8:%[0-9]+]]:sgpr(s32) = G_AMDGPU_READANYLANE [[UV16]] - ; GCN-NEXT: [[AMDGPU_READANYLANE9:%[0-9]+]]:sgpr(s32) = G_AMDGPU_READANYLANE [[UV17]] - ; GCN-NEXT: [[MV4:%[0-9]+]]:sgpr(s64) = G_MERGE_VALUES [[AMDGPU_READANYLANE8]](s32), [[AMDGPU_READANYLANE9]](s32) - ; GCN-NEXT: [[UV18:%[0-9]+]]:vgpr(s32), [[UV19:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[UV5]](s64) - ; GCN-NEXT: [[AMDGPU_READANYLANE10:%[0-9]+]]:sgpr(s32) = G_AMDGPU_READANYLANE [[UV18]] - ; GCN-NEXT: [[AMDGPU_READANYLANE11:%[0-9]+]]:sgpr(s32) = G_AMDGPU_READANYLANE [[UV19]] - ; GCN-NEXT: [[MV5:%[0-9]+]]:sgpr(s64) = G_MERGE_VALUES [[AMDGPU_READANYLANE10]](s32), [[AMDGPU_READANYLANE11]](s32) - ; GCN-NEXT: [[UV20:%[0-9]+]]:vgpr(s32), [[UV21:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[UV6]](s64) - ; GCN-NEXT: [[AMDGPU_READANYLANE12:%[0-9]+]]:sgpr(s32) = G_AMDGPU_READANYLANE [[UV20]] - ; GCN-NEXT: [[AMDGPU_READANYLANE13:%[0-9]+]]:sgpr(s32) = G_AMDGPU_READANYLANE [[UV21]] - ; GCN-NEXT: [[MV6:%[0-9]+]]:sgpr(s64) = G_MERGE_VALUES [[AMDGPU_READANYLANE12]](s32), [[AMDGPU_READANYLANE13]](s32) - ; GCN-NEXT: [[UV22:%[0-9]+]]:vgpr(s32), [[UV23:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[UV7]](s64) - ; GCN-NEXT: [[AMDGPU_READANYLANE14:%[0-9]+]]:sgpr(s32) = G_AMDGPU_READANYLANE [[UV22]] - ; GCN-NEXT: [[AMDGPU_READANYLANE15:%[0-9]+]]:sgpr(s32) = G_AMDGPU_READANYLANE [[UV23]] - ; GCN-NEXT: [[MV7:%[0-9]+]]:sgpr(s64) = G_MERGE_VALUES [[AMDGPU_READANYLANE14]](s32), [[AMDGPU_READANYLANE15]](s32) + ; GCN-NEXT: [[UV8:%[0-9]+]]:vgpr(i32), [[UV9:%[0-9]+]]:vgpr(i32) = G_UNMERGE_VALUES [[UV]](s64) + ; GCN-NEXT: [[AMDGPU_READANYLANE:%[0-9]+]]:sgpr(i32) = G_AMDGPU_READANYLANE [[UV8]] + ; GCN-NEXT: [[AMDGPU_READANYLANE1:%[0-9]+]]:sgpr(i32) = G_AMDGPU_READANYLANE [[UV9]] + ; GCN-NEXT: [[MV:%[0-9]+]]:sgpr(s64) = G_MERGE_VALUES [[AMDGPU_READANYLANE]](i32), [[AMDGPU_READANYLANE1]](i32) + ; GCN-NEXT: [[UV10:%[0-9]+]]:vgpr(i32), [[UV11:%[0-9]+]]:vgpr(i32) = G_UNMERGE_VALUES [[UV1]](s64) + ; GCN-NEXT: [[AMDGPU_READANYLANE2:%[0-9]+]]:sgpr(i32) = G_AMDGPU_READANYLANE [[UV10]] + ; GCN-NEXT: [[AMDGPU_READANYLANE3:%[0-9]+]]:sgpr(i32) = G_AMDGPU_READANYLANE [[UV11]] + ; GCN-NEXT: [[MV1:%[0-9]+]]:sgpr(s64) = G_MERGE_VALUES [[AMDGPU_READANYLANE2]](i32), [[AMDGPU_READANYLANE3]](i32) + ; GCN-NEXT: [[UV12:%[0-9]+]]:vgpr(i32), [[UV13:%[0-9]+]]:vgpr(i32) = G_UNMERGE_VALUES [[UV2]](s64) + ; GCN-NEXT: [[AMDGPU_READANYLANE4:%[0-9]+]]:sgpr(i32) = G_AMDGPU_READANYLANE [[UV12]] + ; GCN-NEXT: [[AMDGPU_READANYLANE5:%[0-9]+]]:sgpr(i32) = G_AMDGPU_READANYLANE [[UV13]] + ; GCN-NEXT: [[MV2:%[0-9]+]]:sgpr(s64) = G_MERGE_VALUES [[AMDGPU_READANYLANE4]](i32), [[AMDGPU_READANYLANE5]](i32) + ; GCN-NEXT: [[UV14:%[0-9]+]]:vgpr(i32), [[UV15:%[0-9]+]]:vgpr(i32) = G_UNMERGE_VALUES [[UV3]](s64) + ; GCN-NEXT: [[AMDGPU_READANYLANE6:%[0-9]+]]:sgpr(i32) = G_AMDGPU_READANYLANE [[UV14]] + ; GCN-NEXT: [[AMDGPU_READANYLANE7:%[0-9]+]]:sgpr(i32) = G_AMDGPU_READANYLANE [[UV15]] + ; GCN-NEXT: [[MV3:%[0-9]+]]:sgpr(s64) = G_MERGE_VALUES [[AMDGPU_READANYLANE6]](i32), [[AMDGPU_READANYLANE7]](i32) + ; GCN-NEXT: [[UV16:%[0-9]+]]:vgpr(i32), [[UV17:%[0-9]+]]:vgpr(i32) = G_UNMERGE_VALUES [[UV4]](s64) + ; GCN-NEXT: [[AMDGPU_READANYLANE8:%[0-9]+]]:sgpr(i32) = G_AMDGPU_READANYLANE [[UV16]] + ; GCN-NEXT: [[AMDGPU_READANYLANE9:%[0-9]+]]:sgpr(i32) = G_AMDGPU_READANYLANE [[UV17]] + ; GCN-NEXT: [[MV4:%[0-9]+]]:sgpr(s64) = G_MERGE_VALUES [[AMDGPU_READANYLANE8]](i32), [[AMDGPU_READANYLANE9]](i32) + ; GCN-NEXT: [[UV18:%[0-9]+]]:vgpr(i32), [[UV19:%[0-9]+]]:vgpr(i32) = G_UNMERGE_VALUES [[UV5]](s64) + ; GCN-NEXT: [[AMDGPU_READANYLANE10:%[0-9]+]]:sgpr(i32) = G_AMDGPU_READANYLANE [[UV18]] + ; GCN-NEXT: [[AMDGPU_READANYLANE11:%[0-9]+]]:sgpr(i32) = G_AMDGPU_READANYLANE [[UV19]] + ; GCN-NEXT: [[MV5:%[0-9]+]]:sgpr(s64) = G_MERGE_VALUES [[AMDGPU_READANYLANE10]](i32), [[AMDGPU_READANYLANE11]](i32) + ; GCN-NEXT: [[UV20:%[0-9]+]]:vgpr(i32), [[UV21:%[0-9]+]]:vgpr(i32) = G_UNMERGE_VALUES [[UV6]](s64) + ; GCN-NEXT: [[AMDGPU_READANYLANE12:%[0-9]+]]:sgpr(i32) = G_AMDGPU_READANYLANE [[UV20]] + ; GCN-NEXT: [[AMDGPU_READANYLANE13:%[0-9]+]]:sgpr(i32) = G_AMDGPU_READANYLANE [[UV21]] + ; GCN-NEXT: [[MV6:%[0-9]+]]:sgpr(s64) = G_MERGE_VALUES [[AMDGPU_READANYLANE12]](i32), [[AMDGPU_READANYLANE13]](i32) + ; GCN-NEXT: [[UV22:%[0-9]+]]:vgpr(i32), [[UV23:%[0-9]+]]:vgpr(i32) = G_UNMERGE_VALUES [[UV7]](s64) + ; GCN-NEXT: [[AMDGPU_READANYLANE14:%[0-9]+]]:sgpr(i32) = G_AMDGPU_READANYLANE [[UV22]] + ; GCN-NEXT: [[AMDGPU_READANYLANE15:%[0-9]+]]:sgpr(i32) = G_AMDGPU_READANYLANE [[UV23]] + ; GCN-NEXT: [[MV7:%[0-9]+]]:sgpr(s64) = G_MERGE_VALUES [[AMDGPU_READANYLANE14]](i32), [[AMDGPU_READANYLANE15]](i32) ; GCN-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<8 x s64>) = G_BUILD_VECTOR [[MV]](s64), [[MV1]](s64), [[MV2]](s64), [[MV3]](s64), [[MV4]](s64), [[MV5]](s64), [[MV6]](s64), [[MV7]](s64) %0:_(p1) = COPY $sgpr0_sgpr1 %1:_(<8 x s64>) = G_LOAD %0 :: (load (<8 x s64>) from %ir.global.not.uniform.v8i64) @@ -400,16 +400,16 @@ body: | ; GCN-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p4) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](i64) ; GCN-NEXT: [[LOAD1:%[0-9]+]]:vgpr(i128) = G_LOAD [[PTR_ADD]](p4) :: (load (i128) from %ir.constant.not.uniform + 16, basealign 32, addrspace 4) ; GCN-NEXT: [[MV:%[0-9]+]]:vgpr(s256) = G_MERGE_VALUES [[LOAD]](i128), [[LOAD1]](i128) - ; GCN-NEXT: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32), [[UV2:%[0-9]+]]:vgpr(s32), [[UV3:%[0-9]+]]:vgpr(s32), [[UV4:%[0-9]+]]:vgpr(s32), [[UV5:%[0-9]+]]:vgpr(s32), [[UV6:%[0-9]+]]:vgpr(s32), [[UV7:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[MV]](s256) - ; GCN-NEXT: [[AMDGPU_READANYLANE:%[0-9]+]]:sgpr(s32) = G_AMDGPU_READANYLANE [[UV]] - ; GCN-NEXT: [[AMDGPU_READANYLANE1:%[0-9]+]]:sgpr(s32) = G_AMDGPU_READANYLANE [[UV1]] - ; GCN-NEXT: [[AMDGPU_READANYLANE2:%[0-9]+]]:sgpr(s32) = G_AMDGPU_READANYLANE [[UV2]] - ; GCN-NEXT: [[AMDGPU_READANYLANE3:%[0-9]+]]:sgpr(s32) = G_AMDGPU_READANYLANE [[UV3]] - ; GCN-NEXT: [[AMDGPU_READANYLANE4:%[0-9]+]]:sgpr(s32) = G_AMDGPU_READANYLANE [[UV4]] - ; GCN-NEXT: [[AMDGPU_READANYLANE5:%[0-9]+]]:sgpr(s32) = G_AMDGPU_READANYLANE [[UV5]] - ; GCN-NEXT: [[AMDGPU_READANYLANE6:%[0-9]+]]:sgpr(s32) = G_AMDGPU_READANYLANE [[UV6]] - ; GCN-NEXT: [[AMDGPU_READANYLANE7:%[0-9]+]]:sgpr(s32) = G_AMDGPU_READANYLANE [[UV7]] - ; GCN-NEXT: [[MV1:%[0-9]+]]:sgpr(s256) = G_MERGE_VALUES [[AMDGPU_READANYLANE]](s32), [[AMDGPU_READANYLANE1]](s32), [[AMDGPU_READANYLANE2]](s32), [[AMDGPU_READANYLANE3]](s32), [[AMDGPU_READANYLANE4]](s32), [[AMDGPU_READANYLANE5]](s32), [[AMDGPU_READANYLANE6]](s32), [[AMDGPU_READANYLANE7]](s32) + ; GCN-NEXT: [[UV:%[0-9]+]]:vgpr(i32), [[UV1:%[0-9]+]]:vgpr(i32), [[UV2:%[0-9]+]]:vgpr(i32), [[UV3:%[0-9]+]]:vgpr(i32), [[UV4:%[0-9]+]]:vgpr(i32), [[UV5:%[0-9]+]]:vgpr(i32), [[UV6:%[0-9]+]]:vgpr(i32), [[UV7:%[0-9]+]]:vgpr(i32) = G_UNMERGE_VALUES [[MV]](s256) + ; GCN-NEXT: [[AMDGPU_READANYLANE:%[0-9]+]]:sgpr(i32) = G_AMDGPU_READANYLANE [[UV]] + ; GCN-NEXT: [[AMDGPU_READANYLANE1:%[0-9]+]]:sgpr(i32) = G_AMDGPU_READANYLANE [[UV1]] + ; GCN-NEXT: [[AMDGPU_READANYLANE2:%[0-9]+]]:sgpr(i32) = G_AMDGPU_READANYLANE [[UV2]] + ; GCN-NEXT: [[AMDGPU_READANYLANE3:%[0-9]+]]:sgpr(i32) = G_AMDGPU_READANYLANE [[UV3]] + ; GCN-NEXT: [[AMDGPU_READANYLANE4:%[0-9]+]]:sgpr(i32) = G_AMDGPU_READANYLANE [[UV4]] + ; GCN-NEXT: [[AMDGPU_READANYLANE5:%[0-9]+]]:sgpr(i32) = G_AMDGPU_READANYLANE [[UV5]] + ; GCN-NEXT: [[AMDGPU_READANYLANE6:%[0-9]+]]:sgpr(i32) = G_AMDGPU_READANYLANE [[UV6]] + ; GCN-NEXT: [[AMDGPU_READANYLANE7:%[0-9]+]]:sgpr(i32) = G_AMDGPU_READANYLANE [[UV7]] + ; GCN-NEXT: [[MV1:%[0-9]+]]:sgpr(s256) = G_MERGE_VALUES [[AMDGPU_READANYLANE]](i32), [[AMDGPU_READANYLANE1]](i32), [[AMDGPU_READANYLANE2]](i32), [[AMDGPU_READANYLANE3]](i32), [[AMDGPU_READANYLANE4]](i32), [[AMDGPU_READANYLANE5]](i32), [[AMDGPU_READANYLANE6]](i32), [[AMDGPU_READANYLANE7]](i32) %0:_(p4) = COPY $sgpr0_sgpr1 %1:_(s256) = G_LOAD %0 :: (load (s256) from %ir.constant.not.uniform) ... @@ -464,22 +464,22 @@ body: | ; GCN-NEXT: [[LOAD1:%[0-9]+]]:vgpr(<2 x s64>) = G_LOAD [[PTR_ADD]](p4) :: (load (<2 x s64>) from %ir.constant.not.uniform.v4i64 + 16, basealign 32, addrspace 4) ; GCN-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<4 x s64>) = G_CONCAT_VECTORS [[LOAD]](<2 x s64>), [[LOAD1]](<2 x s64>) ; GCN-NEXT: [[UV:%[0-9]+]]:vgpr(s64), [[UV1:%[0-9]+]]:vgpr(s64), [[UV2:%[0-9]+]]:vgpr(s64), [[UV3:%[0-9]+]]:vgpr(s64) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<4 x s64>) - ; GCN-NEXT: [[UV4:%[0-9]+]]:vgpr(s32), [[UV5:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[UV]](s64) - ; GCN-NEXT: [[AMDGPU_READANYLANE:%[0-9]+]]:sgpr(s32) = G_AMDGPU_READANYLANE [[UV4]] - ; GCN-NEXT: [[AMDGPU_READANYLANE1:%[0-9]+]]:sgpr(s32) = G_AMDGPU_READANYLANE [[UV5]] - ; GCN-NEXT: [[MV:%[0-9]+]]:sgpr(s64) = G_MERGE_VALUES [[AMDGPU_READANYLANE]](s32), [[AMDGPU_READANYLANE1]](s32) - ; GCN-NEXT: [[UV6:%[0-9]+]]:vgpr(s32), [[UV7:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[UV1]](s64) - ; GCN-NEXT: [[AMDGPU_READANYLANE2:%[0-9]+]]:sgpr(s32) = G_AMDGPU_READANYLANE [[UV6]] - ; GCN-NEXT: [[AMDGPU_READANYLANE3:%[0-9]+]]:sgpr(s32) = G_AMDGPU_READANYLANE [[UV7]] - ; GCN-NEXT: [[MV1:%[0-9]+]]:sgpr(s64) = G_MERGE_VALUES [[AMDGPU_READANYLANE2]](s32), [[AMDGPU_READANYLANE3]](s32) - ; GCN-NEXT: [[UV8:%[0-9]+]]:vgpr(s32), [[UV9:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[UV2]](s64) - ; GCN-NEXT: [[AMDGPU_READANYLANE4:%[0-9]+]]:sgpr(s32) = G_AMDGPU_READANYLANE [[UV8]] - ; GCN-NEXT: [[AMDGPU_READANYLANE5:%[0-9]+]]:sgpr(s32) = G_AMDGPU_READANYLANE [[UV9]] - ; GCN-NEXT: [[MV2:%[0-9]+]]:sgpr(s64) = G_MERGE_VALUES [[AMDGPU_READANYLANE4]](s32), [[AMDGPU_READANYLANE5]](s32) - ; GCN-NEXT: [[UV10:%[0-9]+]]:vgpr(s32), [[UV11:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[UV3]](s64) - ; GCN-NEXT: [[AMDGPU_READANYLANE6:%[0-9]+]]:sgpr(s32) = G_AMDGPU_READANYLANE [[UV10]] - ; GCN-NEXT: [[AMDGPU_READANYLANE7:%[0-9]+]]:sgpr(s32) = G_AMDGPU_READANYLANE [[UV11]] - ; GCN-NEXT: [[MV3:%[0-9]+]]:sgpr(s64) = G_MERGE_VALUES [[AMDGPU_READANYLANE6]](s32), [[AMDGPU_READANYLANE7]](s32) + ; GCN-NEXT: [[UV4:%[0-9]+]]:vgpr(i32), [[UV5:%[0-9]+]]:vgpr(i32) = G_UNMERGE_VALUES [[UV]](s64) + ; GCN-NEXT: [[AMDGPU_READANYLANE:%[0-9]+]]:sgpr(i32) = G_AMDGPU_READANYLANE [[UV4]] + ; GCN-NEXT: [[AMDGPU_READANYLANE1:%[0-9]+]]:sgpr(i32) = G_AMDGPU_READANYLANE [[UV5]] + ; GCN-NEXT: [[MV:%[0-9]+]]:sgpr(s64) = G_MERGE_VALUES [[AMDGPU_READANYLANE]](i32), [[AMDGPU_READANYLANE1]](i32) + ; GCN-NEXT: [[UV6:%[0-9]+]]:vgpr(i32), [[UV7:%[0-9]+]]:vgpr(i32) = G_UNMERGE_VALUES [[UV1]](s64) + ; GCN-NEXT: [[AMDGPU_READANYLANE2:%[0-9]+]]:sgpr(i32) = G_AMDGPU_READANYLANE [[UV6]] + ; GCN-NEXT: [[AMDGPU_READANYLANE3:%[0-9]+]]:sgpr(i32) = G_AMDGPU_READANYLANE [[UV7]] + ; GCN-NEXT: [[MV1:%[0-9]+]]:sgpr(s64) = G_MERGE_VALUES [[AMDGPU_READANYLANE2]](i32), [[AMDGPU_READANYLANE3]](i32) + ; GCN-NEXT: [[UV8:%[0-9]+]]:vgpr(i32), [[UV9:%[0-9]+]]:vgpr(i32) = G_UNMERGE_VALUES [[UV2]](s64) + ; GCN-NEXT: [[AMDGPU_READANYLANE4:%[0-9]+]]:sgpr(i32) = G_AMDGPU_READANYLANE [[UV8]] + ; GCN-NEXT: [[AMDGPU_READANYLANE5:%[0-9]+]]:sgpr(i32) = G_AMDGPU_READANYLANE [[UV9]] + ; GCN-NEXT: [[MV2:%[0-9]+]]:sgpr(s64) = G_MERGE_VALUES [[AMDGPU_READANYLANE4]](i32), [[AMDGPU_READANYLANE5]](i32) + ; GCN-NEXT: [[UV10:%[0-9]+]]:vgpr(i32), [[UV11:%[0-9]+]]:vgpr(i32) = G_UNMERGE_VALUES [[UV3]](s64) + ; GCN-NEXT: [[AMDGPU_READANYLANE6:%[0-9]+]]:sgpr(i32) = G_AMDGPU_READANYLANE [[UV10]] + ; GCN-NEXT: [[AMDGPU_READANYLANE7:%[0-9]+]]:sgpr(i32) = G_AMDGPU_READANYLANE [[UV11]] + ; GCN-NEXT: [[MV3:%[0-9]+]]:sgpr(s64) = G_MERGE_VALUES [[AMDGPU_READANYLANE6]](i32), [[AMDGPU_READANYLANE7]](i32) ; GCN-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s64>) = G_BUILD_VECTOR [[MV]](s64), [[MV1]](s64), [[MV2]](s64), [[MV3]](s64) %0:_(p4) = COPY $sgpr0_sgpr1 %1:_(<4 x s64>) = G_LOAD %0 :: (load (<4 x s64>) from %ir.constant.not.uniform.v4i64) @@ -554,38 +554,38 @@ body: | ; GCN-NEXT: [[LOAD3:%[0-9]+]]:vgpr(<2 x s64>) = G_LOAD [[PTR_ADD2]](p4) :: (load (<2 x s64>) from %ir.constant.not.uniform.v8i64 + 48, basealign 64, addrspace 4) ; GCN-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<8 x s64>) = G_CONCAT_VECTORS [[LOAD]](<2 x s64>), [[LOAD1]](<2 x s64>), [[LOAD2]](<2 x s64>), [[LOAD3]](<2 x s64>) ; GCN-NEXT: [[UV:%[0-9]+]]:vgpr(s64), [[UV1:%[0-9]+]]:vgpr(s64), [[UV2:%[0-9]+]]:vgpr(s64), [[UV3:%[0-9]+]]:vgpr(s64), [[UV4:%[0-9]+]]:vgpr(s64), [[UV5:%[0-9]+]]:vgpr(s64), [[UV6:%[0-9]+]]:vgpr(s64), [[UV7:%[0-9]+]]:vgpr(s64) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<8 x s64>) - ; GCN-NEXT: [[UV8:%[0-9]+]]:vgpr(s32), [[UV9:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[UV]](s64) - ; GCN-NEXT: [[AMDGPU_READANYLANE:%[0-9]+]]:sgpr(s32) = G_AMDGPU_READANYLANE [[UV8]] - ; GCN-NEXT: [[AMDGPU_READANYLANE1:%[0-9]+]]:sgpr(s32) = G_AMDGPU_READANYLANE [[UV9]] - ; GCN-NEXT: [[MV:%[0-9]+]]:sgpr(s64) = G_MERGE_VALUES [[AMDGPU_READANYLANE]](s32), [[AMDGPU_READANYLANE1]](s32) - ; GCN-NEXT: [[UV10:%[0-9]+]]:vgpr(s32), [[UV11:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[UV1]](s64) - ; GCN-NEXT: [[AMDGPU_READANYLANE2:%[0-9]+]]:sgpr(s32) = G_AMDGPU_READANYLANE [[UV10]] - ; GCN-NEXT: [[AMDGPU_READANYLANE3:%[0-9]+]]:sgpr(s32) = G_AMDGPU_READANYLANE [[UV11]] - ; GCN-NEXT: [[MV1:%[0-9]+]]:sgpr(s64) = G_MERGE_VALUES [[AMDGPU_READANYLANE2]](s32), [[AMDGPU_READANYLANE3]](s32) - ; GCN-NEXT: [[UV12:%[0-9]+]]:vgpr(s32), [[UV13:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[UV2]](s64) - ; GCN-NEXT: [[AMDGPU_READANYLANE4:%[0-9]+]]:sgpr(s32) = G_AMDGPU_READANYLANE [[UV12]] - ; GCN-NEXT: [[AMDGPU_READANYLANE5:%[0-9]+]]:sgpr(s32) = G_AMDGPU_READANYLANE [[UV13]] - ; GCN-NEXT: [[MV2:%[0-9]+]]:sgpr(s64) = G_MERGE_VALUES [[AMDGPU_READANYLANE4]](s32), [[AMDGPU_READANYLANE5]](s32) - ; GCN-NEXT: [[UV14:%[0-9]+]]:vgpr(s32), [[UV15:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[UV3]](s64) - ; GCN-NEXT: [[AMDGPU_READANYLANE6:%[0-9]+]]:sgpr(s32) = G_AMDGPU_READANYLANE [[UV14]] - ; GCN-NEXT: [[AMDGPU_READANYLANE7:%[0-9]+]]:sgpr(s32) = G_AMDGPU_READANYLANE [[UV15]] - ; GCN-NEXT: [[MV3:%[0-9]+]]:sgpr(s64) = G_MERGE_VALUES [[AMDGPU_READANYLANE6]](s32), [[AMDGPU_READANYLANE7]](s32) - ; GCN-NEXT: [[UV16:%[0-9]+]]:vgpr(s32), [[UV17:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[UV4]](s64) - ; GCN-NEXT: [[AMDGPU_READANYLANE8:%[0-9]+]]:sgpr(s32) = G_AMDGPU_READANYLANE [[UV16]] - ; GCN-NEXT: [[AMDGPU_READANYLANE9:%[0-9]+]]:sgpr(s32) = G_AMDGPU_READANYLANE [[UV17]] - ; GCN-NEXT: [[MV4:%[0-9]+]]:sgpr(s64) = G_MERGE_VALUES [[AMDGPU_READANYLANE8]](s32), [[AMDGPU_READANYLANE9]](s32) - ; GCN-NEXT: [[UV18:%[0-9]+]]:vgpr(s32), [[UV19:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[UV5]](s64) - ; GCN-NEXT: [[AMDGPU_READANYLANE10:%[0-9]+]]:sgpr(s32) = G_AMDGPU_READANYLANE [[UV18]] - ; GCN-NEXT: [[AMDGPU_READANYLANE11:%[0-9]+]]:sgpr(s32) = G_AMDGPU_READANYLANE [[UV19]] - ; GCN-NEXT: [[MV5:%[0-9]+]]:sgpr(s64) = G_MERGE_VALUES [[AMDGPU_READANYLANE10]](s32), [[AMDGPU_READANYLANE11]](s32) - ; GCN-NEXT: [[UV20:%[0-9]+]]:vgpr(s32), [[UV21:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[UV6]](s64) - ; GCN-NEXT: [[AMDGPU_READANYLANE12:%[0-9]+]]:sgpr(s32) = G_AMDGPU_READANYLANE [[UV20]] - ; GCN-NEXT: [[AMDGPU_READANYLANE13:%[0-9]+]]:sgpr(s32) = G_AMDGPU_READANYLANE [[UV21]] - ; GCN-NEXT: [[MV6:%[0-9]+]]:sgpr(s64) = G_MERGE_VALUES [[AMDGPU_READANYLANE12]](s32), [[AMDGPU_READANYLANE13]](s32) - ; GCN-NEXT: [[UV22:%[0-9]+]]:vgpr(s32), [[UV23:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[UV7]](s64) - ; GCN-NEXT: [[AMDGPU_READANYLANE14:%[0-9]+]]:sgpr(s32) = G_AMDGPU_READANYLANE [[UV22]] - ; GCN-NEXT: [[AMDGPU_READANYLANE15:%[0-9]+]]:sgpr(s32) = G_AMDGPU_READANYLANE [[UV23]] - ; GCN-NEXT: [[MV7:%[0-9]+]]:sgpr(s64) = G_MERGE_VALUES [[AMDGPU_READANYLANE14]](s32), [[AMDGPU_READANYLANE15]](s32) + ; GCN-NEXT: [[UV8:%[0-9]+]]:vgpr(i32), [[UV9:%[0-9]+]]:vgpr(i32) = G_UNMERGE_VALUES [[UV]](s64) + ; GCN-NEXT: [[AMDGPU_READANYLANE:%[0-9]+]]:sgpr(i32) = G_AMDGPU_READANYLANE [[UV8]] + ; GCN-NEXT: [[AMDGPU_READANYLANE1:%[0-9]+]]:sgpr(i32) = G_AMDGPU_READANYLANE [[UV9]] + ; GCN-NEXT: [[MV:%[0-9]+]]:sgpr(s64) = G_MERGE_VALUES [[AMDGPU_READANYLANE]](i32), [[AMDGPU_READANYLANE1]](i32) + ; GCN-NEXT: [[UV10:%[0-9]+]]:vgpr(i32), [[UV11:%[0-9]+]]:vgpr(i32) = G_UNMERGE_VALUES [[UV1]](s64) + ; GCN-NEXT: [[AMDGPU_READANYLANE2:%[0-9]+]]:sgpr(i32) = G_AMDGPU_READANYLANE [[UV10]] + ; GCN-NEXT: [[AMDGPU_READANYLANE3:%[0-9]+]]:sgpr(i32) = G_AMDGPU_READANYLANE [[UV11]] + ; GCN-NEXT: [[MV1:%[0-9]+]]:sgpr(s64) = G_MERGE_VALUES [[AMDGPU_READANYLANE2]](i32), [[AMDGPU_READANYLANE3]](i32) + ; GCN-NEXT: [[UV12:%[0-9]+]]:vgpr(i32), [[UV13:%[0-9]+]]:vgpr(i32) = G_UNMERGE_VALUES [[UV2]](s64) + ; GCN-NEXT: [[AMDGPU_READANYLANE4:%[0-9]+]]:sgpr(i32) = G_AMDGPU_READANYLANE [[UV12]] + ; GCN-NEXT: [[AMDGPU_READANYLANE5:%[0-9]+]]:sgpr(i32) = G_AMDGPU_READANYLANE [[UV13]] + ; GCN-NEXT: [[MV2:%[0-9]+]]:sgpr(s64) = G_MERGE_VALUES [[AMDGPU_READANYLANE4]](i32), [[AMDGPU_READANYLANE5]](i32) + ; GCN-NEXT: [[UV14:%[0-9]+]]:vgpr(i32), [[UV15:%[0-9]+]]:vgpr(i32) = G_UNMERGE_VALUES [[UV3]](s64) + ; GCN-NEXT: [[AMDGPU_READANYLANE6:%[0-9]+]]:sgpr(i32) = G_AMDGPU_READANYLANE [[UV14]] + ; GCN-NEXT: [[AMDGPU_READANYLANE7:%[0-9]+]]:sgpr(i32) = G_AMDGPU_READANYLANE [[UV15]] + ; GCN-NEXT: [[MV3:%[0-9]+]]:sgpr(s64) = G_MERGE_VALUES [[AMDGPU_READANYLANE6]](i32), [[AMDGPU_READANYLANE7]](i32) + ; GCN-NEXT: [[UV16:%[0-9]+]]:vgpr(i32), [[UV17:%[0-9]+]]:vgpr(i32) = G_UNMERGE_VALUES [[UV4]](s64) + ; GCN-NEXT: [[AMDGPU_READANYLANE8:%[0-9]+]]:sgpr(i32) = G_AMDGPU_READANYLANE [[UV16]] + ; GCN-NEXT: [[AMDGPU_READANYLANE9:%[0-9]+]]:sgpr(i32) = G_AMDGPU_READANYLANE [[UV17]] + ; GCN-NEXT: [[MV4:%[0-9]+]]:sgpr(s64) = G_MERGE_VALUES [[AMDGPU_READANYLANE8]](i32), [[AMDGPU_READANYLANE9]](i32) + ; GCN-NEXT: [[UV18:%[0-9]+]]:vgpr(i32), [[UV19:%[0-9]+]]:vgpr(i32) = G_UNMERGE_VALUES [[UV5]](s64) + ; GCN-NEXT: [[AMDGPU_READANYLANE10:%[0-9]+]]:sgpr(i32) = G_AMDGPU_READANYLANE [[UV18]] + ; GCN-NEXT: [[AMDGPU_READANYLANE11:%[0-9]+]]:sgpr(i32) = G_AMDGPU_READANYLANE [[UV19]] + ; GCN-NEXT: [[MV5:%[0-9]+]]:sgpr(s64) = G_MERGE_VALUES [[AMDGPU_READANYLANE10]](i32), [[AMDGPU_READANYLANE11]](i32) + ; GCN-NEXT: [[UV20:%[0-9]+]]:vgpr(i32), [[UV21:%[0-9]+]]:vgpr(i32) = G_UNMERGE_VALUES [[UV6]](s64) + ; GCN-NEXT: [[AMDGPU_READANYLANE12:%[0-9]+]]:sgpr(i32) = G_AMDGPU_READANYLANE [[UV20]] + ; GCN-NEXT: [[AMDGPU_READANYLANE13:%[0-9]+]]:sgpr(i32) = G_AMDGPU_READANYLANE [[UV21]] + ; GCN-NEXT: [[MV6:%[0-9]+]]:sgpr(s64) = G_MERGE_VALUES [[AMDGPU_READANYLANE12]](i32), [[AMDGPU_READANYLANE13]](i32) + ; GCN-NEXT: [[UV22:%[0-9]+]]:vgpr(i32), [[UV23:%[0-9]+]]:vgpr(i32) = G_UNMERGE_VALUES [[UV7]](s64) + ; GCN-NEXT: [[AMDGPU_READANYLANE14:%[0-9]+]]:sgpr(i32) = G_AMDGPU_READANYLANE [[UV22]] + ; GCN-NEXT: [[AMDGPU_READANYLANE15:%[0-9]+]]:sgpr(i32) = G_AMDGPU_READANYLANE [[UV23]] + ; GCN-NEXT: [[MV7:%[0-9]+]]:sgpr(s64) = G_MERGE_VALUES [[AMDGPU_READANYLANE14]](i32), [[AMDGPU_READANYLANE15]](i32) ; GCN-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<8 x s64>) = G_BUILD_VECTOR [[MV]](s64), [[MV1]](s64), [[MV2]](s64), [[MV3]](s64), [[MV4]](s64), [[MV5]](s64), [[MV6]](s64), [[MV7]](s64) %0:_(p4) = COPY $sgpr0_sgpr1 %1:_(<8 x s64>) = G_LOAD %0 :: (load (<8 x s64>) from %ir.constant.not.uniform.v8i64) diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-salu-float.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-salu-float.mir index b77dc7092c8a2..2ccb566fd85f6 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-salu-float.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-salu-float.mir @@ -164,10 +164,10 @@ body: | ; GFX1150-NEXT: [[COPY2:%[0-9]+]]:vgpr(s64) = COPY [[COPY]](s64) ; GFX1150-NEXT: [[COPY3:%[0-9]+]]:vgpr(s64) = COPY [[COPY1]](s64) ; GFX1150-NEXT: [[FADD:%[0-9]+]]:vgpr(s64) = G_FADD [[COPY2]], [[COPY3]] - ; GFX1150-NEXT: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[FADD]](s64) - ; GFX1150-NEXT: [[AMDGPU_READANYLANE:%[0-9]+]]:sgpr(s32) = G_AMDGPU_READANYLANE [[UV]] - ; GFX1150-NEXT: [[AMDGPU_READANYLANE1:%[0-9]+]]:sgpr(s32) = G_AMDGPU_READANYLANE [[UV1]] - ; GFX1150-NEXT: [[MV:%[0-9]+]]:sgpr(s64) = G_MERGE_VALUES [[AMDGPU_READANYLANE]](s32), [[AMDGPU_READANYLANE1]](s32) + ; GFX1150-NEXT: [[UV:%[0-9]+]]:vgpr(i32), [[UV1:%[0-9]+]]:vgpr(i32) = G_UNMERGE_VALUES [[FADD]](s64) + ; GFX1150-NEXT: [[AMDGPU_READANYLANE:%[0-9]+]]:sgpr(i32) = G_AMDGPU_READANYLANE [[UV]] + ; GFX1150-NEXT: [[AMDGPU_READANYLANE1:%[0-9]+]]:sgpr(i32) = G_AMDGPU_READANYLANE [[UV1]] + ; GFX1150-NEXT: [[MV:%[0-9]+]]:sgpr(s64) = G_MERGE_VALUES [[AMDGPU_READANYLANE]](i32), [[AMDGPU_READANYLANE1]](i32) %0:_(s64) = COPY $sgpr0_sgpr1 %1:_(s64) = COPY $sgpr2_sgpr3 %2:_(s64) = G_FADD %0, %1 @@ -266,10 +266,10 @@ body: | ; GFX1150-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 ; GFX1150-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32) ; GFX1150-NEXT: [[SITOFP:%[0-9]+]]:vgpr(s64) = G_SITOFP [[COPY1]](s32) - ; GFX1150-NEXT: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[SITOFP]](s64) - ; GFX1150-NEXT: [[AMDGPU_READANYLANE:%[0-9]+]]:sgpr(s32) = G_AMDGPU_READANYLANE [[UV]] - ; GFX1150-NEXT: [[AMDGPU_READANYLANE1:%[0-9]+]]:sgpr(s32) = G_AMDGPU_READANYLANE [[UV1]] - ; GFX1150-NEXT: [[MV:%[0-9]+]]:sgpr(s64) = G_MERGE_VALUES [[AMDGPU_READANYLANE]](s32), [[AMDGPU_READANYLANE1]](s32) + ; GFX1150-NEXT: [[UV:%[0-9]+]]:vgpr(i32), [[UV1:%[0-9]+]]:vgpr(i32) = G_UNMERGE_VALUES [[SITOFP]](s64) + ; GFX1150-NEXT: [[AMDGPU_READANYLANE:%[0-9]+]]:sgpr(i32) = G_AMDGPU_READANYLANE [[UV]] + ; GFX1150-NEXT: [[AMDGPU_READANYLANE1:%[0-9]+]]:sgpr(i32) = G_AMDGPU_READANYLANE [[UV1]] + ; GFX1150-NEXT: [[MV:%[0-9]+]]:sgpr(s64) = G_MERGE_VALUES [[AMDGPU_READANYLANE]](i32), [[AMDGPU_READANYLANE1]](i32) %0:_(s32) = COPY $sgpr0 %1:_(s64) = G_SITOFP %0(s32) ... @@ -327,10 +327,10 @@ body: | ; GFX1150-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 ; GFX1150-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32) ; GFX1150-NEXT: [[FPEXT:%[0-9]+]]:vgpr(s64) = G_FPEXT [[COPY1]](s32) - ; GFX1150-NEXT: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[FPEXT]](s64) - ; GFX1150-NEXT: [[AMDGPU_READANYLANE:%[0-9]+]]:sgpr(s32) = G_AMDGPU_READANYLANE [[UV]] - ; GFX1150-NEXT: [[AMDGPU_READANYLANE1:%[0-9]+]]:sgpr(s32) = G_AMDGPU_READANYLANE [[UV1]] - ; GFX1150-NEXT: [[MV:%[0-9]+]]:sgpr(s64) = G_MERGE_VALUES [[AMDGPU_READANYLANE]](s32), [[AMDGPU_READANYLANE1]](s32) + ; GFX1150-NEXT: [[UV:%[0-9]+]]:vgpr(i32), [[UV1:%[0-9]+]]:vgpr(i32) = G_UNMERGE_VALUES [[FPEXT]](s64) + ; GFX1150-NEXT: [[AMDGPU_READANYLANE:%[0-9]+]]:sgpr(i32) = G_AMDGPU_READANYLANE [[UV]] + ; GFX1150-NEXT: [[AMDGPU_READANYLANE1:%[0-9]+]]:sgpr(i32) = G_AMDGPU_READANYLANE [[UV1]] + ; GFX1150-NEXT: [[MV:%[0-9]+]]:sgpr(s64) = G_MERGE_VALUES [[AMDGPU_READANYLANE]](i32), [[AMDGPU_READANYLANE1]](i32) %0:_(s32) = COPY $sgpr0 %1:_(s64) = G_FPEXT %0(s32) diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-waterfall-call.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-waterfall-call.mir index 82e2101d3b638..135fb6e444c33 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-waterfall-call.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-waterfall-call.mir @@ -18,10 +18,10 @@ body: | ; CHECK-NEXT: .1: ; CHECK-NEXT: successors: %bb.2(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES %func_ptr(p0) - ; CHECK-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[UV]](s32) - ; CHECK-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:sgpr(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[UV1]](s32) - ; CHECK-NEXT: [[MV:%[0-9]+]]:sgpr(p0) = G_MERGE_VALUES [[INTRINSIC_CONVERGENT]](s32), [[INTRINSIC_CONVERGENT1]](s32) + ; CHECK-NEXT: [[UV:%[0-9]+]]:vgpr(i32), [[UV1:%[0-9]+]]:vgpr(i32) = G_UNMERGE_VALUES %func_ptr(p0) + ; CHECK-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[UV]](i32) + ; CHECK-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[UV1]](i32) + ; CHECK-NEXT: [[MV:%[0-9]+]]:sgpr(p0) = G_MERGE_VALUES [[INTRINSIC_CONVERGENT]](i32), [[INTRINSIC_CONVERGENT1]](i32) ; CHECK-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[MV]](p0), %func_ptr ; CHECK-NEXT: [[INTRINSIC_CONVERGENT2:%[0-9]+]]:sreg_64_xexec(i64) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.ballot), [[ICMP]](s1) ; CHECK-NEXT: [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[INTRINSIC_CONVERGENT2]](i64), implicit-def $exec, implicit-def $scc, implicit $exec @@ -71,10 +71,10 @@ body: | ; CHECK-NEXT: .1: ; CHECK-NEXT: successors: %bb.2(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES %func_ptr(p4) - ; CHECK-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[UV]](s32) - ; CHECK-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:sgpr(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[UV1]](s32) - ; CHECK-NEXT: [[MV:%[0-9]+]]:sgpr(p4) = G_MERGE_VALUES [[INTRINSIC_CONVERGENT]](s32), [[INTRINSIC_CONVERGENT1]](s32) + ; CHECK-NEXT: [[UV:%[0-9]+]]:vgpr(i32), [[UV1:%[0-9]+]]:vgpr(i32) = G_UNMERGE_VALUES %func_ptr(p4) + ; CHECK-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[UV]](i32) + ; CHECK-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[UV1]](i32) + ; CHECK-NEXT: [[MV:%[0-9]+]]:sgpr(p4) = G_MERGE_VALUES [[INTRINSIC_CONVERGENT]](i32), [[INTRINSIC_CONVERGENT1]](i32) ; CHECK-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[MV]](p4), %func_ptr ; CHECK-NEXT: [[INTRINSIC_CONVERGENT2:%[0-9]+]]:sreg_64_xexec(i64) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.ballot), [[ICMP]](s1) ; CHECK-NEXT: [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[INTRINSIC_CONVERGENT2]](i64), implicit-def $exec, implicit-def $scc, implicit $exec @@ -124,10 +124,10 @@ body: | ; CHECK-NEXT: .1: ; CHECK-NEXT: successors: %bb.2(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES %func_ptr(p0) - ; CHECK-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[UV]](s32) - ; CHECK-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:sgpr(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[UV1]](s32) - ; CHECK-NEXT: [[MV:%[0-9]+]]:sgpr(p0) = G_MERGE_VALUES [[INTRINSIC_CONVERGENT]](s32), [[INTRINSIC_CONVERGENT1]](s32) + ; CHECK-NEXT: [[UV:%[0-9]+]]:vgpr(i32), [[UV1:%[0-9]+]]:vgpr(i32) = G_UNMERGE_VALUES %func_ptr(p0) + ; CHECK-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[UV]](i32) + ; CHECK-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[UV1]](i32) + ; CHECK-NEXT: [[MV:%[0-9]+]]:sgpr(p0) = G_MERGE_VALUES [[INTRINSIC_CONVERGENT]](i32), [[INTRINSIC_CONVERGENT1]](i32) ; CHECK-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[MV]](p0), %func_ptr ; CHECK-NEXT: [[INTRINSIC_CONVERGENT2:%[0-9]+]]:sreg_64_xexec(i64) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.ballot), [[ICMP]](s1) ; CHECK-NEXT: [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[INTRINSIC_CONVERGENT2]](i64), implicit-def $exec, implicit-def $scc, implicit $exec @@ -177,10 +177,10 @@ body: | ; CHECK-NEXT: .1: ; CHECK-NEXT: successors: %bb.2(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES %func_ptr(p4) - ; CHECK-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[UV]](s32) - ; CHECK-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:sgpr(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[UV1]](s32) - ; CHECK-NEXT: [[MV:%[0-9]+]]:sgpr(p4) = G_MERGE_VALUES [[INTRINSIC_CONVERGENT]](s32), [[INTRINSIC_CONVERGENT1]](s32) + ; CHECK-NEXT: [[UV:%[0-9]+]]:vgpr(i32), [[UV1:%[0-9]+]]:vgpr(i32) = G_UNMERGE_VALUES %func_ptr(p4) + ; CHECK-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[UV]](i32) + ; CHECK-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[UV1]](i32) + ; CHECK-NEXT: [[MV:%[0-9]+]]:sgpr(p4) = G_MERGE_VALUES [[INTRINSIC_CONVERGENT]](i32), [[INTRINSIC_CONVERGENT1]](i32) ; CHECK-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[MV]](p4), %func_ptr ; CHECK-NEXT: [[INTRINSIC_CONVERGENT2:%[0-9]+]]:sreg_64_xexec(i64) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.ballot), [[ICMP]](s1) ; CHECK-NEXT: [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[INTRINSIC_CONVERGENT2]](i64), implicit-def $exec, implicit-def $scc, implicit $exec diff --git a/llvm/test/CodeGen/AMDGPU/indirect-call.ll b/llvm/test/CodeGen/AMDGPU/indirect-call.ll index 1dbc21136362d..acc3a8598557d 100644 --- a/llvm/test/CodeGen/AMDGPU/indirect-call.ll +++ b/llvm/test/CodeGen/AMDGPU/indirect-call.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=amdgpu7.00-amd-amdhsa < %s | FileCheck -check-prefix=GCN %s -; RUN: llc -mtriple=amdgpu7.00-amd-amdhsa -global-isel -global-isel-abort=2 < %s | FileCheck -check-prefix=GISEL %s +; RUN: llc -mtriple=amdgpu7.00-amd-amdhsa -global-isel < %s | FileCheck -check-prefix=GISEL %s @gv.fptr0 = external hidden unnamed_addr addrspace(4) constant ptr, align 4 @gv.fptr1 = external hidden unnamed_addr addrspace(4) constant ptr, align 4 @@ -253,7 +253,7 @@ define void @test_indirect_call_vgpr_ptr(ptr %fptr) #0 { ; GISEL-NEXT: s_mov_b32 s14, s51 ; GISEL-NEXT: s_mov_b32 s15, s50 ; GISEL-NEXT: s_swappc_b64 s[30:31], s[16:17] -; GISEL-NEXT: ; implicit-def: $vgpr0_vgpr1 +; GISEL-NEXT: ; implicit-def: $vgpr0 ; GISEL-NEXT: ; implicit-def: $vgpr31 ; GISEL-NEXT: s_xor_b64 exec, exec, s[64:65] ; GISEL-NEXT: s_cbranch_execnz .LBB2_1 @@ -414,12 +414,12 @@ define void @test_indirect_call_vgpr_ptr_arg(ptr %fptr) #0 { ; GISEL-NEXT: s_mov_b64 s[38:39], s[6:7] ; GISEL-NEXT: s_mov_b64 s[48:49], s[4:5] ; GISEL-NEXT: s_mov_b64 s[54:55], exec -; GISEL-NEXT: v_mov_b32_e32 v2, 0x7b ; GISEL-NEXT: .LBB3_1: ; =>This Inner Loop Header: Depth=1 ; GISEL-NEXT: v_readfirstlane_b32 s16, v0 ; GISEL-NEXT: v_readfirstlane_b32 s17, v1 ; GISEL-NEXT: v_cmp_eq_u64_e32 vcc, s[16:17], v[0:1] ; GISEL-NEXT: s_and_saveexec_b64 s[64:65], vcc +; GISEL-NEXT: v_mov_b32_e32 v0, 0x7b ; GISEL-NEXT: s_mov_b64 s[4:5], s[48:49] ; GISEL-NEXT: s_mov_b64 s[6:7], s[38:39] ; GISEL-NEXT: s_mov_b64 s[8:9], s[36:37] @@ -428,11 +428,9 @@ define void @test_indirect_call_vgpr_ptr_arg(ptr %fptr) #0 { ; GISEL-NEXT: s_mov_b32 s13, s52 ; GISEL-NEXT: s_mov_b32 s14, s51 ; GISEL-NEXT: s_mov_b32 s15, s50 -; GISEL-NEXT: v_mov_b32_e32 v0, v2 ; GISEL-NEXT: s_swappc_b64 s[30:31], s[16:17] -; GISEL-NEXT: ; implicit-def: $vgpr0_vgpr1 +; GISEL-NEXT: ; implicit-def: $vgpr0 ; GISEL-NEXT: ; implicit-def: $vgpr31 -; GISEL-NEXT: ; implicit-def: $vgpr2 ; GISEL-NEXT: s_xor_b64 exec, exec, s[64:65] ; GISEL-NEXT: s_cbranch_execnz .LBB3_1 ; GISEL-NEXT: ; %bb.2: @@ -605,15 +603,15 @@ define i32 @test_indirect_call_vgpr_ptr_ret(ptr %fptr) #0 { ; GISEL-NEXT: s_mov_b32 s14, s51 ; GISEL-NEXT: s_mov_b32 s15, s50 ; GISEL-NEXT: s_swappc_b64 s[30:31], s[16:17] -; GISEL-NEXT: v_mov_b32_e32 v2, v0 -; GISEL-NEXT: ; implicit-def: $vgpr0_vgpr1 +; GISEL-NEXT: v_mov_b32_e32 v1, v0 +; GISEL-NEXT: ; implicit-def: $vgpr0 ; GISEL-NEXT: ; implicit-def: $vgpr31 ; GISEL-NEXT: s_xor_b64 exec, exec, s[64:65] ; GISEL-NEXT: s_cbranch_execnz .LBB4_1 ; GISEL-NEXT: ; %bb.2: ; GISEL-NEXT: s_mov_b64 exec, s[54:55] ; GISEL-NEXT: v_readlane_b32 s30, v40, 16 -; GISEL-NEXT: v_add_i32_e32 v0, vcc, 1, v2 +; GISEL-NEXT: v_add_i32_e32 v0, vcc, 1, v1 ; GISEL-NEXT: v_readlane_b32 s31, v40, 17 ; GISEL-NEXT: v_readlane_b32 s65, v40, 15 ; GISEL-NEXT: v_readlane_b32 s64, v40, 14 @@ -779,7 +777,7 @@ define void @test_indirect_call_vgpr_ptr_in_branch(ptr %fptr, i1 %cond) #0 { ; GISEL-NEXT: s_mov_b64 s[36:37], s[8:9] ; GISEL-NEXT: s_mov_b64 s[38:39], s[6:7] ; GISEL-NEXT: s_mov_b64 s[48:49], s[4:5] -; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 1, v2 +; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 ; GISEL-NEXT: s_and_saveexec_b64 s[54:55], vcc ; GISEL-NEXT: s_cbranch_execz .LBB5_4 ; GISEL-NEXT: ; %bb.1: ; %bb1 @@ -798,7 +796,7 @@ define void @test_indirect_call_vgpr_ptr_in_branch(ptr %fptr, i1 %cond) #0 { ; GISEL-NEXT: s_mov_b32 s14, s51 ; GISEL-NEXT: s_mov_b32 s15, s50 ; GISEL-NEXT: s_swappc_b64 s[30:31], s[16:17] -; GISEL-NEXT: ; implicit-def: $vgpr0_vgpr1 +; GISEL-NEXT: ; implicit-def: $vgpr0 ; GISEL-NEXT: ; implicit-def: $vgpr31 ; GISEL-NEXT: s_xor_b64 exec, exec, s[66:67] ; GISEL-NEXT: s_cbranch_execnz .LBB5_2 @@ -934,15 +932,17 @@ define void @test_indirect_call_vgpr_ptr_inreg_arg(ptr %fptr) #0 { ; GISEL-NEXT: v_writelane_b32 v40, s30, 14 ; GISEL-NEXT: v_writelane_b32 v40, s31, 15 ; GISEL-NEXT: s_mov_b64 s[6:7], exec +; GISEL-NEXT: v_mov_b32_e32 v2, 0x7b ; GISEL-NEXT: .LBB6_1: ; =>This Inner Loop Header: Depth=1 -; GISEL-NEXT: v_readfirstlane_b32 s8, v0 -; GISEL-NEXT: v_readfirstlane_b32 s9, v1 -; GISEL-NEXT: v_cmp_eq_u64_e32 vcc, s[8:9], v[0:1] -; GISEL-NEXT: s_and_saveexec_b64 s[10:11], vcc -; GISEL-NEXT: s_movk_i32 s4, 0x7b -; GISEL-NEXT: s_swappc_b64 s[30:31], s[8:9] -; GISEL-NEXT: ; implicit-def: $vgpr0_vgpr1 -; GISEL-NEXT: s_xor_b64 exec, exec, s[10:11] +; GISEL-NEXT: v_readfirstlane_b32 s10, v0 +; GISEL-NEXT: v_readfirstlane_b32 s11, v1 +; GISEL-NEXT: v_cmp_eq_u64_e32 vcc, s[10:11], v[0:1] +; GISEL-NEXT: s_and_saveexec_b64 s[8:9], vcc +; GISEL-NEXT: v_readfirstlane_b32 s4, v2 +; GISEL-NEXT: s_swappc_b64 s[30:31], s[10:11] +; GISEL-NEXT: ; implicit-def: $vgpr0 +; GISEL-NEXT: ; implicit-def: $vgpr2 +; GISEL-NEXT: s_xor_b64 exec, exec, s[8:9] ; GISEL-NEXT: s_cbranch_execnz .LBB6_1 ; GISEL-NEXT: ; %bb.2: ; GISEL-NEXT: s_mov_b64 exec, s[6:7] @@ -1075,7 +1075,7 @@ define i32 @test_indirect_call_vgpr_ptr_arg_and_reuse(i32 %i, ptr %fptr) #0 { ; GISEL-NEXT: s_and_saveexec_b64 s[8:9], vcc ; GISEL-NEXT: v_mov_b32_e32 v0, v40 ; GISEL-NEXT: s_swappc_b64 s[30:31], s[6:7] -; GISEL-NEXT: ; implicit-def: $vgpr1_vgpr2 +; GISEL-NEXT: ; implicit-def: $vgpr1 ; GISEL-NEXT: s_xor_b64 exec, exec, s[8:9] ; GISEL-NEXT: s_cbranch_execnz .LBB7_1 ; GISEL-NEXT: ; %bb.2: @@ -1210,15 +1210,15 @@ define i32 @test_indirect_call_vgpr_ptr_arg_and_return(i32 %i, ptr %fptr) #0 { ; GISEL-NEXT: v_cmp_eq_u64_e32 vcc, s[8:9], v[1:2] ; GISEL-NEXT: s_and_saveexec_b64 s[6:7], vcc ; GISEL-NEXT: s_swappc_b64 s[30:31], s[8:9] -; GISEL-NEXT: v_mov_b32_e32 v3, v0 -; GISEL-NEXT: ; implicit-def: $vgpr1_vgpr2 +; GISEL-NEXT: v_mov_b32_e32 v2, v0 +; GISEL-NEXT: ; implicit-def: $vgpr1 ; GISEL-NEXT: ; implicit-def: $vgpr0 ; GISEL-NEXT: s_xor_b64 exec, exec, s[6:7] ; GISEL-NEXT: s_cbranch_execnz .LBB8_1 ; GISEL-NEXT: ; %bb.2: ; GISEL-NEXT: s_mov_b64 exec, s[4:5] ; GISEL-NEXT: v_readlane_b32 s30, v40, 14 -; GISEL-NEXT: v_mov_b32_e32 v0, v3 +; GISEL-NEXT: v_mov_b32_e32 v0, v2 ; GISEL-NEXT: v_readlane_b32 s31, v40, 15 ; GISEL-NEXT: v_readlane_b32 s55, v40, 13 ; GISEL-NEXT: v_readlane_b32 s54, v40, 12 @@ -1340,7 +1340,7 @@ define void @test_indirect_tail_call_vgpr_ptr(ptr %fptr) #0 { ; GISEL-NEXT: v_cmp_eq_u64_e32 vcc, s[6:7], v[0:1] ; GISEL-NEXT: s_and_saveexec_b64 s[8:9], vcc ; GISEL-NEXT: s_swappc_b64 s[30:31], s[6:7] -; GISEL-NEXT: ; implicit-def: $vgpr0_vgpr1 +; GISEL-NEXT: ; implicit-def: $vgpr0 ; GISEL-NEXT: s_xor_b64 exec, exec, s[8:9] ; GISEL-NEXT: s_cbranch_execnz .LBB9_1 ; GISEL-NEXT: ; %bb.2: diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.inverse.ballot.i64.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.inverse.ballot.i64.ll index a240d81ce1199..52befb254b9d3 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.inverse.ballot.i64.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.inverse.ballot.i64.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 -; RUN: llc -mtriple=amdgpu11.00 -amdgpu-enable-delay-alu=0 -mattr=+wavefrontsize64 -global-isel=1 -global-isel-abort=2 < %s | FileCheck -check-prefix=GISEL_W64 %s +; RUN: llc -mtriple=amdgpu11.00 -amdgpu-enable-delay-alu=0 -mattr=+wavefrontsize64 -global-isel=1 < %s | FileCheck -check-prefix=GISEL_W64 %s ; RUN: llc -mtriple=amdgpu11.00 -amdgpu-enable-delay-alu=0 -mattr=+wavefrontsize64 -global-isel=0 < %s | FileCheck -check-prefix=SDAG_W64 %s -; RUN: llc -mtriple=amdgpu11.00 -amdgpu-enable-delay-alu=0 -mattr=+wavefrontsize32 -global-isel=1 -global-isel-abort=2 < %s | FileCheck -check-prefix=GISEL_W32 %s +; RUN: llc -mtriple=amdgpu11.00 -amdgpu-enable-delay-alu=0 -mattr=+wavefrontsize32 -global-isel=1 < %s | FileCheck -check-prefix=GISEL_W32 %s ; RUN: llc -mtriple=amdgpu11.00 -amdgpu-enable-delay-alu=0 -mattr=+wavefrontsize32 -global-isel=0 < %s | FileCheck -check-prefix=SDAG_W32 %s declare i1 @llvm.amdgcn.inverse.ballot.i64(i64) @@ -142,10 +142,9 @@ define amdgpu_cs void @vgpr_inverse_ballot(i64 %input, ptr addrspace(1) %out) { ; GISEL_W64: ; %bb.0: ; %entry ; GISEL_W64-NEXT: v_readfirstlane_b32 s0, v0 ; GISEL_W64-NEXT: v_readfirstlane_b32 s1, v1 -; GISEL_W64-NEXT: s_mov_b32 s2, 0 -; GISEL_W64-NEXT: v_mov_b32_e32 v1, s2 -; GISEL_W64-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1] -; GISEL_W64-NEXT: global_store_b64 v[2:3], v[0:1], off +; GISEL_W64-NEXT: v_mov_b32_e32 v5, 0 +; GISEL_W64-NEXT: v_cndmask_b32_e64 v4, 0, 1, s[0:1] +; GISEL_W64-NEXT: global_store_b64 v[2:3], v[4:5], off ; GISEL_W64-NEXT: s_endpgm ; ; SDAG_W64-LABEL: vgpr_inverse_ballot: @@ -160,10 +159,9 @@ define amdgpu_cs void @vgpr_inverse_ballot(i64 %input, ptr addrspace(1) %out) { ; ; GISEL_W32-LABEL: vgpr_inverse_ballot: ; GISEL_W32: ; %bb.0: ; %entry -; GISEL_W32-NEXT: v_readfirstlane_b32 s1, v0 -; GISEL_W32-NEXT: s_mov_b32 s0, 0 -; GISEL_W32-NEXT: v_mov_b32_e32 v1, s0 -; GISEL_W32-NEXT: v_cndmask_b32_e64 v0, 0, 1, s1 +; GISEL_W32-NEXT: v_readfirstlane_b32 s0, v0 +; GISEL_W32-NEXT: v_mov_b32_e32 v1, 0 +; GISEL_W32-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 ; GISEL_W32-NEXT: global_store_b64 v[2:3], v[0:1], off ; GISEL_W32-NEXT: s_endpgm ; diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.quadmask.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.quadmask.ll index 4ee54027ee7cb..36227b25842ee 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.quadmask.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.quadmask.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 -; RUN: llc -mtriple=amdgpu11.00 -amdgpu-enable-delay-alu=0 -global-isel=1 -global-isel-abort=2 < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL %s +; RUN: llc -mtriple=amdgpu11.00 -amdgpu-enable-delay-alu=0 -global-isel=1 < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL %s ; RUN: llc -mtriple=amdgpu11.00 -amdgpu-enable-delay-alu=0 -global-isel=0 < %s | FileCheck -check-prefixes=GFX11,GFX11-SDAG %s declare i32 @llvm.amdgcn.s.quadmask.i32(i32) diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.prefetch.data.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.prefetch.data.ll index 0f3f411cb5744..35d8bff26ab12 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.prefetch.data.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.prefetch.data.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 ; RUN: llc -global-isel=0 -mtriple=amdgpu12.00 < %s | FileCheck --check-prefixes=GCN,SDAG %s -; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgpu12.00 < %s | FileCheck --check-prefixes=GCN,GISEL %s +; RUN: llc -global-isel=1 -mtriple=amdgpu12.00 < %s | FileCheck --check-prefixes=GCN,GISEL %s define amdgpu_ps void @prefetch_data_sgpr_base_sgpr_len(ptr addrspace(4) inreg %ptr, i32 inreg %len) { ; GCN-LABEL: prefetch_data_sgpr_base_sgpr_len: @@ -57,12 +57,23 @@ entry: } define amdgpu_ps void @prefetch_data_vgpr_imm_base_sgpr_len(ptr addrspace(4) %ptr, i32 inreg %len) { -; GCN-LABEL: prefetch_data_vgpr_imm_base_sgpr_len: -; GCN: ; %bb.0: ; %entry -; GCN-NEXT: v_readfirstlane_b32 s2, v0 -; GCN-NEXT: v_readfirstlane_b32 s3, v1 -; GCN-NEXT: s_prefetch_data s[2:3], 0x200, s0, 0 -; GCN-NEXT: s_endpgm +; SDAG-LABEL: prefetch_data_vgpr_imm_base_sgpr_len: +; SDAG: ; %bb.0: ; %entry +; SDAG-NEXT: v_readfirstlane_b32 s2, v0 +; SDAG-NEXT: v_readfirstlane_b32 s3, v1 +; SDAG-NEXT: s_prefetch_data s[2:3], 0x200, s0, 0 +; SDAG-NEXT: s_endpgm +; +; GISEL-LABEL: prefetch_data_vgpr_imm_base_sgpr_len: +; GISEL: ; %bb.0: ; %entry +; GISEL-NEXT: v_add_co_u32 v0, vcc_lo, 0x200, v0 +; GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) +; GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo +; GISEL-NEXT: v_readfirstlane_b32 s2, v0 +; GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GISEL-NEXT: v_readfirstlane_b32 s3, v1 +; GISEL-NEXT: s_prefetch_data s[2:3], 0x0, s0, 0 +; GISEL-NEXT: s_endpgm entry: %gep = getelementptr i32, ptr addrspace(4) %ptr, i32 128 tail call void @llvm.amdgcn.s.prefetch.data.p4(ptr addrspace(4) %gep, i32 %len) @@ -113,13 +124,21 @@ entry: } define amdgpu_ps void @prefetch_data_vgpr_base_vgpr_len(ptr addrspace(4) %ptr, i32 %len) { -; GCN-LABEL: prefetch_data_vgpr_base_vgpr_len: -; GCN: ; %bb.0: ; %entry -; GCN-NEXT: v_readfirstlane_b32 s2, v2 -; GCN-NEXT: v_readfirstlane_b32 s0, v0 -; GCN-NEXT: v_readfirstlane_b32 s1, v1 -; GCN-NEXT: s_prefetch_data s[0:1], 0x0, s2, 0 -; GCN-NEXT: s_endpgm +; SDAG-LABEL: prefetch_data_vgpr_base_vgpr_len: +; SDAG: ; %bb.0: ; %entry +; SDAG-NEXT: v_readfirstlane_b32 s2, v2 +; SDAG-NEXT: v_readfirstlane_b32 s0, v0 +; SDAG-NEXT: v_readfirstlane_b32 s1, v1 +; SDAG-NEXT: s_prefetch_data s[0:1], 0x0, s2, 0 +; SDAG-NEXT: s_endpgm +; +; GISEL-LABEL: prefetch_data_vgpr_base_vgpr_len: +; GISEL: ; %bb.0: ; %entry +; GISEL-NEXT: v_readfirstlane_b32 s0, v0 +; GISEL-NEXT: v_readfirstlane_b32 s1, v1 +; GISEL-NEXT: v_readfirstlane_b32 s2, v2 +; GISEL-NEXT: s_prefetch_data s[0:1], 0x0, s2, 0 +; GISEL-NEXT: s_endpgm entry: tail call void @llvm.amdgcn.s.prefetch.data.p4(ptr addrspace(4) %ptr, i32 %len) ret void @@ -142,6 +161,3 @@ entry: declare void @llvm.amdgcn.s.prefetch.data.p4(ptr addrspace(4) %ptr, i32 %len) declare void @llvm.amdgcn.s.prefetch.data.p1(ptr addrspace(1) %ptr, i32 %len) declare void @llvm.amdgcn.s.prefetch.data.p0(ptr %ptr, i32 %len) -;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: -; GISEL: {{.*}} -; SDAG: {{.*}} diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.prefetch.inst.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.prefetch.inst.ll index 932537be5ecb0..b68870a4c4a66 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.prefetch.inst.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.prefetch.inst.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 ; RUN: llc -global-isel=0 -mtriple=amdgpu12.00 < %s | FileCheck --check-prefixes=GCN,GFX12,GFX12-SDAG %s -; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgpu12.00 < %s | FileCheck --check-prefixes=GCN,GFX12,GFX12-GISEL %s +; RUN: llc -global-isel=1 -mtriple=amdgpu12.00 < %s | FileCheck --check-prefixes=GCN,GFX12,GFX12-GISEL %s ; RUN: llc -global-isel=0 -mtriple=amdgpu12.50 < %s | FileCheck --check-prefixes=GCN,GFX1250,GFX1250-SDAG %s -; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgpu12.50 < %s | FileCheck --check-prefixes=GCN,GFX1250,GFX1250-GISEL %s +; RUN: llc -global-isel=1 -mtriple=amdgpu12.50 < %s | FileCheck --check-prefixes=GCN,GFX1250,GFX1250-GISEL %s define amdgpu_ps void @prefetch_inst_sgpr_base_sgpr_len(ptr addrspace(4) inreg %ptr, i32 inreg %len) { ; GFX12-LABEL: prefetch_inst_sgpr_base_sgpr_len: @@ -96,22 +96,47 @@ define amdgpu_ps void @prefetch_inst_vgpr_base_sgpr_len(ptr addrspace(4) %ptr, i } define amdgpu_ps void @prefetch_inst_vgpr_imm_base_sgpr_len(ptr addrspace(4) %ptr, i32 inreg %len) { -; GFX12-LABEL: prefetch_inst_vgpr_imm_base_sgpr_len: -; GFX12: ; %bb.0: -; GFX12-NEXT: v_readfirstlane_b32 s2, v0 -; GFX12-NEXT: v_readfirstlane_b32 s3, v1 -; GFX12-NEXT: s_prefetch_inst s[2:3], 0x200, s0, 0 -; GFX12-NEXT: s_endpgm +; GFX12-SDAG-LABEL: prefetch_inst_vgpr_imm_base_sgpr_len: +; GFX12-SDAG: ; %bb.0: +; GFX12-SDAG-NEXT: v_readfirstlane_b32 s2, v0 +; GFX12-SDAG-NEXT: v_readfirstlane_b32 s3, v1 +; GFX12-SDAG-NEXT: s_prefetch_inst s[2:3], 0x200, s0, 0 +; GFX12-SDAG-NEXT: s_endpgm ; -; GFX1250-LABEL: prefetch_inst_vgpr_imm_base_sgpr_len: -; GFX1250: ; %bb.0: -; GFX1250-NEXT: global_wb -; GFX1250-NEXT: v_nop -; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 -; GFX1250-NEXT: v_readfirstlane_b32 s2, v0 -; GFX1250-NEXT: v_readfirstlane_b32 s3, v1 -; GFX1250-NEXT: s_prefetch_inst s[2:3], 0x200, s0, 0 -; GFX1250-NEXT: s_endpgm +; GFX12-GISEL-LABEL: prefetch_inst_vgpr_imm_base_sgpr_len: +; GFX12-GISEL: ; %bb.0: +; GFX12-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, 0x200, v0 +; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX12-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo +; GFX12-GISEL-NEXT: v_readfirstlane_b32 s2, v0 +; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX12-GISEL-NEXT: v_readfirstlane_b32 s3, v1 +; GFX12-GISEL-NEXT: s_prefetch_inst s[2:3], 0x0, s0, 0 +; GFX12-GISEL-NEXT: s_endpgm +; +; GFX1250-SDAG-LABEL: prefetch_inst_vgpr_imm_base_sgpr_len: +; GFX1250-SDAG: ; %bb.0: +; GFX1250-SDAG-NEXT: global_wb +; GFX1250-SDAG-NEXT: v_nop +; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 +; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s2, v0 +; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s3, v1 +; GFX1250-SDAG-NEXT: s_prefetch_inst s[2:3], 0x200, s0, 0 +; GFX1250-SDAG-NEXT: s_endpgm +; +; GFX1250-GISEL-LABEL: prefetch_inst_vgpr_imm_base_sgpr_len: +; GFX1250-GISEL: ; %bb.0: +; GFX1250-GISEL-NEXT: global_wb +; GFX1250-GISEL-NEXT: v_nop +; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 +; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, 0x200, v0 +; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo +; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s2, v0 +; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s3, v1 +; GFX1250-GISEL-NEXT: s_prefetch_inst s[2:3], 0x0, s0, 0 +; GFX1250-GISEL-NEXT: s_endpgm %gep = getelementptr i32, ptr addrspace(4) %ptr, i32 128 tail call void @llvm.amdgcn.s.prefetch.inst.p4(ptr addrspace(4) %gep, i32 %len) ret void @@ -158,24 +183,43 @@ define amdgpu_ps void @prefetch_inst_vgpr_base_imm_len(ptr addrspace(4) %ptr) { } define amdgpu_ps void @prefetch_inst_vgpr_base_vgpr_len(ptr addrspace(4) %ptr, i32 %len) { -; GFX12-LABEL: prefetch_inst_vgpr_base_vgpr_len: -; GFX12: ; %bb.0: -; GFX12-NEXT: v_readfirstlane_b32 s2, v2 -; GFX12-NEXT: v_readfirstlane_b32 s0, v0 -; GFX12-NEXT: v_readfirstlane_b32 s1, v1 -; GFX12-NEXT: s_prefetch_inst s[0:1], 0x0, s2, 0 -; GFX12-NEXT: s_endpgm +; GFX12-SDAG-LABEL: prefetch_inst_vgpr_base_vgpr_len: +; GFX12-SDAG: ; %bb.0: +; GFX12-SDAG-NEXT: v_readfirstlane_b32 s2, v2 +; GFX12-SDAG-NEXT: v_readfirstlane_b32 s0, v0 +; GFX12-SDAG-NEXT: v_readfirstlane_b32 s1, v1 +; GFX12-SDAG-NEXT: s_prefetch_inst s[0:1], 0x0, s2, 0 +; GFX12-SDAG-NEXT: s_endpgm ; -; GFX1250-LABEL: prefetch_inst_vgpr_base_vgpr_len: -; GFX1250: ; %bb.0: -; GFX1250-NEXT: global_wb -; GFX1250-NEXT: v_nop -; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 -; GFX1250-NEXT: v_readfirstlane_b32 s2, v2 -; GFX1250-NEXT: v_readfirstlane_b32 s0, v0 -; GFX1250-NEXT: v_readfirstlane_b32 s1, v1 -; GFX1250-NEXT: s_prefetch_inst s[0:1], 0x0, s2, 0 -; GFX1250-NEXT: s_endpgm +; GFX12-GISEL-LABEL: prefetch_inst_vgpr_base_vgpr_len: +; GFX12-GISEL: ; %bb.0: +; GFX12-GISEL-NEXT: v_readfirstlane_b32 s0, v0 +; GFX12-GISEL-NEXT: v_readfirstlane_b32 s1, v1 +; GFX12-GISEL-NEXT: v_readfirstlane_b32 s2, v2 +; GFX12-GISEL-NEXT: s_prefetch_inst s[0:1], 0x0, s2, 0 +; GFX12-GISEL-NEXT: s_endpgm +; +; GFX1250-SDAG-LABEL: prefetch_inst_vgpr_base_vgpr_len: +; GFX1250-SDAG: ; %bb.0: +; GFX1250-SDAG-NEXT: global_wb +; GFX1250-SDAG-NEXT: v_nop +; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 +; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s2, v2 +; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s0, v0 +; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s1, v1 +; GFX1250-SDAG-NEXT: s_prefetch_inst s[0:1], 0x0, s2, 0 +; GFX1250-SDAG-NEXT: s_endpgm +; +; GFX1250-GISEL-LABEL: prefetch_inst_vgpr_base_vgpr_len: +; GFX1250-GISEL: ; %bb.0: +; GFX1250-GISEL-NEXT: global_wb +; GFX1250-GISEL-NEXT: v_nop +; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 +; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s0, v0 +; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s1, v1 +; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s2, v2 +; GFX1250-GISEL-NEXT: s_prefetch_inst s[0:1], 0x0, s2, 0 +; GFX1250-GISEL-NEXT: s_endpgm tail call void @llvm.amdgcn.s.prefetch.inst.p4(ptr addrspace(4) %ptr, i32 %len) ret void } @@ -312,24 +356,43 @@ define amdgpu_ps void @prefetch_inst_sgpr_base_vgpr_len_global(ptr addrspace(1) } define amdgpu_ps void @prefetch_inst_vgpr_base_vgpr_len_global(ptr addrspace(1) %ptr, i32 %len) { -; GFX12-LABEL: prefetch_inst_vgpr_base_vgpr_len_global: -; GFX12: ; %bb.0: -; GFX12-NEXT: v_readfirstlane_b32 s2, v2 -; GFX12-NEXT: v_readfirstlane_b32 s0, v0 -; GFX12-NEXT: v_readfirstlane_b32 s1, v1 -; GFX12-NEXT: s_prefetch_inst s[0:1], 0x0, s2, 0 -; GFX12-NEXT: s_endpgm +; GFX12-SDAG-LABEL: prefetch_inst_vgpr_base_vgpr_len_global: +; GFX12-SDAG: ; %bb.0: +; GFX12-SDAG-NEXT: v_readfirstlane_b32 s2, v2 +; GFX12-SDAG-NEXT: v_readfirstlane_b32 s0, v0 +; GFX12-SDAG-NEXT: v_readfirstlane_b32 s1, v1 +; GFX12-SDAG-NEXT: s_prefetch_inst s[0:1], 0x0, s2, 0 +; GFX12-SDAG-NEXT: s_endpgm ; -; GFX1250-LABEL: prefetch_inst_vgpr_base_vgpr_len_global: -; GFX1250: ; %bb.0: -; GFX1250-NEXT: global_wb -; GFX1250-NEXT: v_nop -; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 -; GFX1250-NEXT: v_readfirstlane_b32 s2, v2 -; GFX1250-NEXT: v_readfirstlane_b32 s0, v0 -; GFX1250-NEXT: v_readfirstlane_b32 s1, v1 -; GFX1250-NEXT: s_prefetch_inst s[0:1], 0x0, s2, 0 -; GFX1250-NEXT: s_endpgm +; GFX12-GISEL-LABEL: prefetch_inst_vgpr_base_vgpr_len_global: +; GFX12-GISEL: ; %bb.0: +; GFX12-GISEL-NEXT: v_readfirstlane_b32 s0, v0 +; GFX12-GISEL-NEXT: v_readfirstlane_b32 s1, v1 +; GFX12-GISEL-NEXT: v_readfirstlane_b32 s2, v2 +; GFX12-GISEL-NEXT: s_prefetch_inst s[0:1], 0x0, s2, 0 +; GFX12-GISEL-NEXT: s_endpgm +; +; GFX1250-SDAG-LABEL: prefetch_inst_vgpr_base_vgpr_len_global: +; GFX1250-SDAG: ; %bb.0: +; GFX1250-SDAG-NEXT: global_wb +; GFX1250-SDAG-NEXT: v_nop +; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 +; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s2, v2 +; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s0, v0 +; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s1, v1 +; GFX1250-SDAG-NEXT: s_prefetch_inst s[0:1], 0x0, s2, 0 +; GFX1250-SDAG-NEXT: s_endpgm +; +; GFX1250-GISEL-LABEL: prefetch_inst_vgpr_base_vgpr_len_global: +; GFX1250-GISEL: ; %bb.0: +; GFX1250-GISEL-NEXT: global_wb +; GFX1250-GISEL-NEXT: v_nop +; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 +; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s0, v0 +; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s1, v1 +; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s2, v2 +; GFX1250-GISEL-NEXT: s_prefetch_inst s[0:1], 0x0, s2, 0 +; GFX1250-GISEL-NEXT: s_endpgm tail call void @llvm.amdgcn.s.prefetch.inst.p1(ptr addrspace(1) %ptr, i32 %len) ret void } @@ -466,24 +529,43 @@ define amdgpu_ps void @prefetch_inst_sgpr_base_vgpr_len_flat(ptr inreg %ptr, i32 } define amdgpu_ps void @prefetch_inst_vgpr_base_vgpr_len_flat(ptr %ptr, i32 %len) { -; GFX12-LABEL: prefetch_inst_vgpr_base_vgpr_len_flat: -; GFX12: ; %bb.0: -; GFX12-NEXT: v_readfirstlane_b32 s2, v2 -; GFX12-NEXT: v_readfirstlane_b32 s0, v0 -; GFX12-NEXT: v_readfirstlane_b32 s1, v1 -; GFX12-NEXT: s_prefetch_inst s[0:1], 0x0, s2, 0 -; GFX12-NEXT: s_endpgm +; GFX12-SDAG-LABEL: prefetch_inst_vgpr_base_vgpr_len_flat: +; GFX12-SDAG: ; %bb.0: +; GFX12-SDAG-NEXT: v_readfirstlane_b32 s2, v2 +; GFX12-SDAG-NEXT: v_readfirstlane_b32 s0, v0 +; GFX12-SDAG-NEXT: v_readfirstlane_b32 s1, v1 +; GFX12-SDAG-NEXT: s_prefetch_inst s[0:1], 0x0, s2, 0 +; GFX12-SDAG-NEXT: s_endpgm ; -; GFX1250-LABEL: prefetch_inst_vgpr_base_vgpr_len_flat: -; GFX1250: ; %bb.0: -; GFX1250-NEXT: global_wb -; GFX1250-NEXT: v_nop -; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 -; GFX1250-NEXT: v_readfirstlane_b32 s2, v2 -; GFX1250-NEXT: v_readfirstlane_b32 s0, v0 -; GFX1250-NEXT: v_readfirstlane_b32 s1, v1 -; GFX1250-NEXT: s_prefetch_inst s[0:1], 0x0, s2, 0 -; GFX1250-NEXT: s_endpgm +; GFX12-GISEL-LABEL: prefetch_inst_vgpr_base_vgpr_len_flat: +; GFX12-GISEL: ; %bb.0: +; GFX12-GISEL-NEXT: v_readfirstlane_b32 s0, v0 +; GFX12-GISEL-NEXT: v_readfirstlane_b32 s1, v1 +; GFX12-GISEL-NEXT: v_readfirstlane_b32 s2, v2 +; GFX12-GISEL-NEXT: s_prefetch_inst s[0:1], 0x0, s2, 0 +; GFX12-GISEL-NEXT: s_endpgm +; +; GFX1250-SDAG-LABEL: prefetch_inst_vgpr_base_vgpr_len_flat: +; GFX1250-SDAG: ; %bb.0: +; GFX1250-SDAG-NEXT: global_wb +; GFX1250-SDAG-NEXT: v_nop +; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 +; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s2, v2 +; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s0, v0 +; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s1, v1 +; GFX1250-SDAG-NEXT: s_prefetch_inst s[0:1], 0x0, s2, 0 +; GFX1250-SDAG-NEXT: s_endpgm +; +; GFX1250-GISEL-LABEL: prefetch_inst_vgpr_base_vgpr_len_flat: +; GFX1250-GISEL: ; %bb.0: +; GFX1250-GISEL-NEXT: global_wb +; GFX1250-GISEL-NEXT: v_nop +; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 +; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s0, v0 +; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s1, v1 +; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s2, v2 +; GFX1250-GISEL-NEXT: s_prefetch_inst s[0:1], 0x0, s2, 0 +; GFX1250-GISEL-NEXT: s_endpgm tail call void @llvm.amdgcn.s.prefetch.inst.p0(ptr %ptr, i32 %len) ret void } @@ -547,7 +629,3 @@ declare amdgpu_ps void @target() ;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: ; GCN: {{.*}} -; GFX12-GISEL: {{.*}} -; GFX12-SDAG: {{.*}} -; GFX1250-GISEL: {{.*}} -; GFX1250-SDAG: {{.*}} diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wqm.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wqm.ll index b0d34091756c3..3c3fa8da2afc7 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wqm.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wqm.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 -; RUN: llc -mtriple=amdgpu11.00 -amdgpu-enable-delay-alu=0 -global-isel=1 -global-isel-abort=2 < %s | FileCheck -check-prefixes=GFX11 %s +; RUN: llc -mtriple=amdgpu11.00 -amdgpu-enable-delay-alu=0 -global-isel=1 < %s | FileCheck -check-prefixes=GFX11 %s ; RUN: llc -mtriple=amdgpu11.00 -amdgpu-enable-delay-alu=0 -global-isel=0 < %s | FileCheck -check-prefixes=GFX11 %s declare i32 @llvm.amdgcn.s.wqm.i32(i32) _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
