================
@@ -6391,17 +6407,10 @@ bool SIInstrInfo::isLegalRegOperand(const MachineInstr
&MI, unsigned OpIdx,
// See SIInstrInfo::isLegalGFX12PlusPackedMathFP32or64BitOperand for more
// information.
if (AMDGPU::isPackedFP32or64BitInst(MI.getOpcode()) &&
- AMDGPU::isGFX12Plus(ST) && MO.isReg() && RI.isSGPRReg(MRI, MO.getReg()))
{
- constexpr AMDGPU::OpName OpNames[] = {
- AMDGPU::OpName::src0, AMDGPU::OpName::src1, AMDGPU::OpName::src2};
-
- for (auto [I, OpName] : enumerate(OpNames)) {
- int SrcIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), OpNames[I]);
- if (static_cast<unsigned>(SrcIdx) == OpIdx &&
- !isLegalGFX12PlusPackedMathFP32or64BitOperand(MRI, MI, I, &MO))
- return false;
- }
- }
+ AMDGPU::isGFX12Plus(ST) && MO.isReg() && RI.isSGPRReg(MRI, MO.getReg())
&&
----------------
rampitec wrote:
It's already there, it is not a new code. I just squashed the condition.
https://github.com/llvm/llvm-project/pull/211374
_______________________________________________
llvm-branch-commits mailing list
[email protected]
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
