llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-backend-risc-v Author: llvmbot <details> <summary>Changes</summary> Backport 38da688c60b208a48d60b70396ac46716edc72d5 Requested by: @<!-- -->wangpc-pp --- Full diff: https://github.com/llvm/llvm-project/pull/216645.diff 2 Files Affected: - (modified) llvm/lib/Target/RISCV/RISCVInstrInfo.cpp (+6-1) - (added) llvm/test/CodeGen/RISCV/optimize-cond-branch-undef.mir (+36) ``````````diff diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp index e36410fbcb593..49d8fa0fc27fd 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp @@ -1622,7 +1622,12 @@ bool RISCVInstrInfo::isFromLoadImm(const MachineRegisterInfo &MRI, Imm = 0; return true; } - return Reg.isVirtual() && isLoadImm(MRI.getVRegDef(Reg), Imm); + + if (!Reg.isVirtual()) + return false; + + const MachineInstr *DefMI = MRI.getVRegDef(Reg); + return DefMI && isLoadImm(DefMI, Imm); } bool RISCVInstrInfo::optimizeCondBranch(MachineInstr &MI) const { diff --git a/llvm/test/CodeGen/RISCV/optimize-cond-branch-undef.mir b/llvm/test/CodeGen/RISCV/optimize-cond-branch-undef.mir new file mode 100644 index 0000000000000..2c291b5f3a120 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/optimize-cond-branch-undef.mir @@ -0,0 +1,36 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6 +# RUN: llc -mtriple=riscv64 -run-pass=peephole-opt -o - %s | FileCheck %s + +# A conditional branch on an undef register with no def must not crash the +# peephole optimizer while it checks whether the operand is a load-immediate. +--- +name: cond_branch_undef +tracksRegLiveness: true +body: | + ; CHECK-LABEL: name: cond_branch_undef + ; CHECK: bb.0: + ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000) + ; CHECK-NEXT: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: BLT undef %1:gpr, [[COPY]], %bb.1 + ; CHECK-NEXT: PseudoBR %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1: + ; CHECK-NEXT: PseudoRET + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2: + ; CHECK-NEXT: PseudoRET + bb.0: + successors: %bb.1, %bb.2 + liveins: $x10 + %0:gpr = COPY $x10 + BLT undef %1:gpr, %0, %bb.1 + PseudoBR %bb.2 + + bb.1: + PseudoRET + + bb.2: + PseudoRET +... `````````` </details> https://github.com/llvm/llvm-project/pull/216645 _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
