Author: Michael Jones Date: 2026-08-25T15:52:19-07:00 New Revision: 96767c6c95d26b977f47ce4fdf6b135224ff02f6
URL: https://github.com/llvm/llvm-project/commit/96767c6c95d26b977f47ce4fdf6b135224ff02f6 DIFF: https://github.com/llvm/llvm-project/commit/96767c6c95d26b977f47ce4fdf6b135224ff02f6.diff LOG: Revert "[PromoteMemToReg] Insert store undef when removing lifetime markers (…" This reverts commit efd053f8ef306e6fa21ab0cd1bd185ef48f09fc0. Added: Modified: llvm/lib/Transforms/Utils/Local.cpp llvm/lib/Transforms/Utils/PromoteMemoryToRegister.cpp llvm/test/Transforms/PhaseOrdering/ARM/arm_mean_q7.ll llvm/test/Transforms/PhaseOrdering/ARM/arm_var_q31.ll llvm/test/Transforms/PhaseOrdering/always-inline-alloca-promotion.ll Removed: llvm/test/Transforms/SROA/lifetime-aware-phi.ll ################################################################################ diff --git a/llvm/lib/Transforms/Utils/Local.cpp b/llvm/lib/Transforms/Utils/Local.cpp index 6084305241cc3..1e12427dc0d12 100644 --- a/llvm/lib/Transforms/Utils/Local.cpp +++ b/llvm/lib/Transforms/Utils/Local.cpp @@ -1660,9 +1660,6 @@ void llvm::ConvertDebugDeclareToDebugValue(DbgVariableRecord *DVR, auto *DIExpr = DVR->getExpression(); Value *DV = SI->getValueOperand(); - if (isa<UndefValue>(DV) && !isa<PoisonValue>(DV)) - return; - DebugLoc NewLoc = getDebugValueLoc(DVR); // If the alloca describes the variable itself, i.e. the expression in the diff --git a/llvm/lib/Transforms/Utils/PromoteMemoryToRegister.cpp b/llvm/lib/Transforms/Utils/PromoteMemoryToRegister.cpp index 21ddc78f1469b..ed0e864fd6905 100644 --- a/llvm/lib/Transforms/Utils/PromoteMemoryToRegister.cpp +++ b/llvm/lib/Transforms/Utils/PromoteMemoryToRegister.cpp @@ -523,22 +523,6 @@ static void removeIntrinsicUsers(AllocaInst *AI) { // Knowing that this alloca is promotable, we know that it's safe to kill all // instructions except for load and store. - // Determine the type used by loads/stores on this alloca. Per - // isAllocaPromotable, all loads/stores must use the same type, and GEP/ - // bitcast/addrspacecast derived pointers cannot have load/store users, so - // loads/stores are always direct users of the alloca. - Type *PromotedType = nullptr; - for (User *U : AI->users()) { - if (auto *LI = dyn_cast<LoadInst>(U)) { - PromotedType = LI->getType(); - break; - } - if (auto *SI = dyn_cast<StoreInst>(U)) { - PromotedType = SI->getValueOperand()->getType(); - break; - } - } - for (Use &U : llvm::make_early_inc_range(AI->uses())) { Instruction *I = cast<Instruction>(U.getUser()); if (isa<LoadInst>(I) || isa<StoreInst>(I)) @@ -551,8 +535,9 @@ static void removeIntrinsicUsers(AllocaInst *AI) { } if (!I->getType()->isVoidTy()) { - // Follow the use/def chain to erase users of this instruction now - // instead of leaving it for dead code elimination later. + // The only users of this bitcast/GEP instruction are lifetime intrinsics. + // Follow the use/def chain to erase them now instead of leaving it for + // dead code elimination later. for (Use &UU : llvm::make_early_inc_range(I->uses())) { Instruction *Inst = cast<Instruction>(UU.getUser()); @@ -561,23 +546,9 @@ static void removeIntrinsicUsers(AllocaInst *AI) { Inst->dropDroppableUse(UU); continue; } - Inst->eraseFromParent(); } } - - // Same as above for lifetime intrinsics directly on the alloca. If the - // alloca has no load/store users, PromotedType is null and the alloca will - // be deleted as dead, so no store is needed. - if (PromotedType) - if (auto *II = dyn_cast<IntrinsicInst>(I)) - if (II->isLifetimeStartOrEnd()) { - auto *Store = new StoreInst(UndefValue::get(PromotedType), AI, - /*isVolatile=*/false, AI->getAlign(), - I->getIterator()); - Store->setDebugLoc(II->getDebugLoc()); - } - I->eraseFromParent(); } } diff --git a/llvm/test/Transforms/PhaseOrdering/ARM/arm_mean_q7.ll b/llvm/test/Transforms/PhaseOrdering/ARM/arm_mean_q7.ll index f7b60684ac963..9ff9f92c4edca 100644 --- a/llvm/test/Transforms/PhaseOrdering/ARM/arm_mean_q7.ll +++ b/llvm/test/Transforms/PhaseOrdering/ARM/arm_mean_q7.ll @@ -14,8 +14,8 @@ define void @arm_mean_q7(ptr noundef %pSrc, i32 noundef %blockSize, ptr noundef ; CHECK-NEXT: br i1 [[CMP_NOT10]], label [[WHILE_END:%.*]], label [[WHILE_BODY:%.*]] ; CHECK: while.body: ; CHECK-NEXT: [[SUM_013:%.*]] = phi i32 [ [[TMP2:%.*]], [[WHILE_BODY]] ], [ 0, [[WHILE_BODY_PREHEADER:%.*]] ] -; CHECK-NEXT: [[BLKCNT_011:%.*]] = phi i32 [ [[DEC:%.*]], [[WHILE_BODY]] ], [ [[SHR]], [[WHILE_BODY_PREHEADER]] ] ; CHECK-NEXT: [[PSRC_ADDR_012:%.*]] = phi ptr [ [[ADD_PTR:%.*]], [[WHILE_BODY]] ], [ [[PSRC:%.*]], [[WHILE_BODY_PREHEADER]] ] +; CHECK-NEXT: [[BLKCNT_011:%.*]] = phi i32 [ [[DEC:%.*]], [[WHILE_BODY]] ], [ [[SHR]], [[WHILE_BODY_PREHEADER]] ] ; CHECK-NEXT: [[TMP0:%.*]] = load <16 x i8>, ptr [[PSRC_ADDR_012]], align 1 ; CHECK-NEXT: [[TMP1:%.*]] = tail call i32 @llvm.arm.mve.addv.v16i8(<16 x i8> [[TMP0]], i32 0) ; CHECK-NEXT: [[TMP2]] = add i32 [[TMP1]], [[SUM_013]] diff --git a/llvm/test/Transforms/PhaseOrdering/ARM/arm_var_q31.ll b/llvm/test/Transforms/PhaseOrdering/ARM/arm_var_q31.ll index 20daa8c86e4fb..2f89eb44fee4c 100644 --- a/llvm/test/Transforms/PhaseOrdering/ARM/arm_var_q31.ll +++ b/llvm/test/Transforms/PhaseOrdering/ARM/arm_var_q31.ll @@ -22,15 +22,15 @@ define void @arm_var_q31(ptr noundef %pSrc, i32 noundef %blockSize, ptr noundef ; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[WHILE_BODY_PREHEADER67:%.*]], label [[VECTOR_PH:%.*]] ; CHECK: vector.ph: ; CHECK-NEXT: [[N_VEC:%.*]] = and i32 [[SHR]], 1073741820 -; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[SHR]], 3 ; CHECK-NEXT: [[TMP0:%.*]] = shl i32 [[N_VEC]], 4 ; CHECK-NEXT: [[TMP1:%.*]] = getelementptr i8, ptr [[PSRC:%.*]], i32 [[TMP0]] +; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[SHR]], 3 ; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] ; CHECK: vector.body: ; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] ; CHECK-NEXT: [[VEC_PHI:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[TMP25:%.*]], [[VECTOR_BODY]] ] -; CHECK-NEXT: [[VEC_PHI53:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[TMP33:%.*]], [[VECTOR_BODY]] ] ; CHECK-NEXT: [[POINTER_PHI:%.*]] = phi ptr [ [[PSRC]], [[VECTOR_PH]] ], [ [[PTR_IND:%.*]], [[VECTOR_BODY]] ] +; CHECK-NEXT: [[VEC_PHI53:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[TMP33:%.*]], [[VECTOR_BODY]] ] ; CHECK-NEXT: [[VECTOR_GEP:%.*]] = getelementptr i8, ptr [[POINTER_PHI]], <4 x i32> <i32 0, i32 16, i32 32, i32 48> ; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw i8, <4 x ptr> [[VECTOR_GEP]], i32 4 ; CHECK-NEXT: [[WIDE_MASKED_GATHER:%.*]] = tail call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> align 4 [[VECTOR_GEP]], <4 x i1> splat (i1 true), <4 x i32> poison), !tbaa [[TBAA4:![0-9]+]] @@ -76,15 +76,15 @@ define void @arm_var_q31(ptr noundef %pSrc, i32 noundef %blockSize, ptr noundef ; CHECK-NEXT: br i1 [[CMP_N]], label [[WHILE_END_LOOPEXIT:%.*]], label [[WHILE_BODY_PREHEADER67]] ; CHECK: while.body.preheader65: ; CHECK-NEXT: [[SUMOFSQUARES_043_PH:%.*]] = phi i64 [ 0, [[WHILE_BODY_PREHEADER]] ], [ [[TMP25]], [[MIDDLE_BLOCK]] ] -; CHECK-NEXT: [[SUM_040_PH:%.*]] = phi i64 [ 0, [[WHILE_BODY_PREHEADER]] ], [ [[TMP33]], [[MIDDLE_BLOCK]] ] +; CHECK-NEXT: [[PSRC_ADDR_042_PH:%.*]] = phi ptr [ [[PSRC]], [[WHILE_BODY_PREHEADER]] ], [ [[TMP1]], [[MIDDLE_BLOCK]] ] ; CHECK-NEXT: [[BLKCNT_041_PH:%.*]] = phi i32 [ [[SHR]], [[WHILE_BODY_PREHEADER]] ], [ [[TMP2]], [[MIDDLE_BLOCK]] ] -; CHECK-NEXT: [[PSRC_ADDR_040_PH:%.*]] = phi ptr [ [[PSRC]], [[WHILE_BODY_PREHEADER]] ], [ [[TMP1]], [[MIDDLE_BLOCK]] ] +; CHECK-NEXT: [[SUM_040_PH:%.*]] = phi i64 [ 0, [[WHILE_BODY_PREHEADER]] ], [ [[TMP33]], [[MIDDLE_BLOCK]] ] ; CHECK-NEXT: br label [[WHILE_BODY:%.*]] ; CHECK: while.body: ; CHECK-NEXT: [[SUMOFSQUARES_043:%.*]] = phi i64 [ [[ADD27:%.*]], [[WHILE_BODY]] ], [ [[SUMOFSQUARES_043_PH]], [[WHILE_BODY_PREHEADER67]] ] -; CHECK-NEXT: [[SUM_040:%.*]] = phi i64 [ [[ADD29:%.*]], [[WHILE_BODY]] ], [ [[SUM_040_PH]], [[WHILE_BODY_PREHEADER67]] ] +; CHECK-NEXT: [[PSRC_ADDR_042:%.*]] = phi ptr [ [[INCDEC_PTR22:%.*]], [[WHILE_BODY]] ], [ [[PSRC_ADDR_042_PH]], [[WHILE_BODY_PREHEADER67]] ] ; CHECK-NEXT: [[BLKCNT_041:%.*]] = phi i32 [ [[DEC:%.*]], [[WHILE_BODY]] ], [ [[BLKCNT_041_PH]], [[WHILE_BODY_PREHEADER67]] ] -; CHECK-NEXT: [[PSRC_ADDR_042:%.*]] = phi ptr [ [[INCDEC_PTR22:%.*]], [[WHILE_BODY]] ], [ [[PSRC_ADDR_040_PH]], [[WHILE_BODY_PREHEADER67]] ] +; CHECK-NEXT: [[SUM_040:%.*]] = phi i64 [ [[ADD29:%.*]], [[WHILE_BODY]] ], [ [[SUM_040_PH]], [[WHILE_BODY_PREHEADER67]] ] ; CHECK-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds nuw i8, ptr [[PSRC_ADDR_042]], i32 4 ; CHECK-NEXT: [[TMP35:%.*]] = load i32, ptr [[PSRC_ADDR_042]], align 4, !tbaa [[TBAA4]] ; CHECK-NEXT: [[SHR2:%.*]] = ashr i32 [[TMP35]], 8 @@ -123,8 +123,8 @@ define void @arm_var_q31(ptr noundef %pSrc, i32 noundef %blockSize, ptr noundef ; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[PSRC]], i32 [[TMP39]] ; CHECK-NEXT: br label [[WHILE_END]] ; CHECK: while.end: -; CHECK-NEXT: [[PSRC_ADDR_0_LCSSA:%.*]] = phi ptr [ [[PSRC]], [[IF_END]] ], [ [[SCEVGEP]], [[WHILE_END_LOOPEXIT]] ] ; CHECK-NEXT: [[SUM_0_LCSSA:%.*]] = phi i64 [ 0, [[IF_END]] ], [ [[ADD29_LCSSA]], [[WHILE_END_LOOPEXIT]] ] +; CHECK-NEXT: [[PSRC_ADDR_0_LCSSA:%.*]] = phi ptr [ [[PSRC]], [[IF_END]] ], [ [[SCEVGEP]], [[WHILE_END_LOOPEXIT]] ] ; CHECK-NEXT: [[SUMOFSQUARES_0_LCSSA:%.*]] = phi i64 [ 0, [[IF_END]] ], [ [[ADD27_LCSSA]], [[WHILE_END_LOOPEXIT]] ] ; CHECK-NEXT: [[REM:%.*]] = and i32 [[BLOCKSIZE]], 3 ; CHECK-NEXT: [[CMP31_NOT46:%.*]] = icmp eq i32 [[REM]], 0 diff --git a/llvm/test/Transforms/PhaseOrdering/always-inline-alloca-promotion.ll b/llvm/test/Transforms/PhaseOrdering/always-inline-alloca-promotion.ll index 519cfaed87ab4..b235987c19d6b 100644 --- a/llvm/test/Transforms/PhaseOrdering/always-inline-alloca-promotion.ll +++ b/llvm/test/Transforms/PhaseOrdering/always-inline-alloca-promotion.ll @@ -12,10 +12,12 @@ define void @pluto() #0 { ; CHECK-SAME: ) local_unnamed_addr #[[ATTR0:[0-9]+]] { ; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr inttoptr (i64 48 to ptr), align 16 ; CHECK-NEXT: [[TMP2:%.*]] = icmp sgt i64 [[TMP1]], 0 -; CHECK-NEXT: [[TMP3:%.*]] = tail call <vscale x 4 x float> @llvm.vector.extract.nxv4f32.nxv16f32(<vscale x 16 x float> undef, i64 0) -; CHECK-NEXT: [[TMP4:%.*]] = select i1 [[TMP2]], <vscale x 4 x float> zeroinitializer, <vscale x 4 x float> [[TMP3]] +; CHECK-NEXT: [[TMP3:%.*]] = tail call <vscale x 16 x float> @llvm.vector.insert.nxv16f32.nxv4f32(<vscale x 16 x float> zeroinitializer, <vscale x 4 x float> zeroinitializer, i64 0) ; CHECK-NEXT: br label %[[SNORK_EXIT:.*]] ; CHECK: [[SNORK_EXIT]]: +; CHECK-NEXT: [[DOT0:%.*]] = phi <vscale x 16 x float> [ undef, [[TMP0:%.*]] ], [ [[SPEC_SELECT:%.*]], %[[SNORK_EXIT]] ] +; CHECK-NEXT: [[SPEC_SELECT]] = select i1 [[TMP2]], <vscale x 16 x float> [[TMP3]], <vscale x 16 x float> [[DOT0]] +; CHECK-NEXT: [[TMP4:%.*]] = tail call <vscale x 4 x float> @llvm.vector.extract.nxv4f32.nxv16f32(<vscale x 16 x float> [[SPEC_SELECT]], i64 0) ; CHECK-NEXT: tail call void @llvm.aarch64.sme.mopa.nxv4f32(i32 0, <vscale x 4 x i1> zeroinitializer, <vscale x 4 x i1> zeroinitializer, <vscale x 4 x float> zeroinitializer, <vscale x 4 x float> [[TMP4]]) ; CHECK-NEXT: br label %[[SNORK_EXIT]] ; diff --git a/llvm/test/Transforms/SROA/lifetime-aware-phi.ll b/llvm/test/Transforms/SROA/lifetime-aware-phi.ll deleted file mode 100644 index 6774c56e946b0..0000000000000 --- a/llvm/test/Transforms/SROA/lifetime-aware-phi.ll +++ /dev/null @@ -1,190 +0,0 @@ -; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6 -; RUN: opt < %s -passes=sroa -S | FileCheck %s - -; SROA should use lifetime intrinsics to avoid creating recurrent PHI nodes -; when promoting struct allocas. -; -; The alloca is reused across loop iterations. Without lifetime markers, SROA -; must conservatively assume the i32 field retains its value on the skip path, -; so it inserts a back-edge PHI at the loop header carrying the previous -; iteration's value. -; -; With lifetime.start at the top of the loop, the alloca's content is -; logically undefined at that point each iteration. SROA should propagate this -; onto each slice alloca: PromoteMemToReg can then treat lifetime.start as an -; implicit "store undef", breaking the back-edge dependence and eliminating -; the recurrent PHI. -; -; PromoteMemToReg treats lifetime markers as implicit "store undef", breaking -; back-edge dependences and eliminating recurrent PHIs in @with_lifetime and -; @with_lifetime_end. - -%struct.S = type { i8, i32, i8 } - -declare void @use(i32) - -; Without lifetime markers a recurrent PHI at the loop header is unavoidable. -define void @without_lifetime(i32 %val, i1 %c1, i1 %c2) { -; CHECK-LABEL: define void @without_lifetime( -; CHECK-SAME: i32 [[VAL:%.*]], i1 [[C1:%.*]], i1 [[C2:%.*]]) { -; CHECK-NEXT: [[ENTRY:.*]]: -; CHECK-NEXT: br label %[[LOOP:.*]] -; CHECK: [[LOOP]]: -; CHECK-NEXT: [[S_SROA_1_0:%.*]] = phi i32 [ undef, %[[ENTRY]] ], [ [[S_SROA_1_1:%.*]], %[[CLEANUP:.*]] ] -; CHECK-NEXT: br i1 [[C1]], label %[[INIT:.*]], label %[[SKIP:.*]] -; CHECK: [[INIT]]: -; CHECK-NEXT: br label %[[READ:.*]] -; CHECK: [[SKIP]]: -; CHECK-NEXT: br label %[[READ]] -; CHECK: [[READ]]: -; CHECK-NEXT: [[S_SROA_1_1]] = phi i32 [ [[VAL]], %[[INIT]] ], [ [[S_SROA_1_0]], %[[SKIP]] ] -; CHECK-NEXT: call void @use(i32 [[S_SROA_1_1]]) -; CHECK-NEXT: br label %[[CLEANUP]] -; CHECK: [[CLEANUP]]: -; CHECK-NEXT: br i1 [[C2]], label %[[LOOP]], label %[[EXIT:.*]] -; CHECK: [[EXIT]]: -; CHECK-NEXT: ret void -; -entry: - %s = alloca %struct.S, align 4 - br label %loop - -loop: - br i1 %c1, label %init, label %skip - -init: - %gep0 = getelementptr inbounds %struct.S, ptr %s, i32 0, i32 0 - store i8 65, ptr %gep0, align 4 - %gep1 = getelementptr inbounds %struct.S, ptr %s, i32 0, i32 1 - store i32 %val, ptr %gep1, align 4 - %gep2 = getelementptr inbounds %struct.S, ptr %s, i32 0, i32 2 - store i8 90, ptr %gep2, align 4 - br label %read - -skip: - br label %read - -read: - %gep1r = getelementptr inbounds %struct.S, ptr %s, i32 0, i32 1 - %v = load i32, ptr %gep1r, align 4 - call void @use(i32 %v) - br label %cleanup - -cleanup: - br i1 %c2, label %loop, label %exit - -exit: - ret void -} - -; With lifetime markers the back-edge PHI is unnecessary: lifetime.start -; at the top of the loop makes the alloca's content undef at that point, -; so the skip path should yield undef rather than carrying a stale value. -; No recurrent PHI should be created at the loop header. -; The only PHI is at the read block, merging %val (init) with undef (skip). -define void @with_lifetime(i32 %val, i1 %c1, i1 %c2) { -; CHECK-LABEL: define void @with_lifetime( -; CHECK-SAME: i32 [[VAL:%.*]], i1 [[C1:%.*]], i1 [[C2:%.*]]) { -; CHECK-NEXT: [[ENTRY:.*:]] -; CHECK-NEXT: br label %[[LOOP:.*]] -; CHECK: [[LOOP]]: -; CHECK-NEXT: br i1 [[C1]], label %[[INIT:.*]], label %[[SKIP:.*]] -; CHECK: [[INIT]]: -; CHECK-NEXT: br label %[[READ:.*]] -; CHECK: [[SKIP]]: -; CHECK-NEXT: br label %[[READ]] -; CHECK: [[READ]]: -; CHECK-NEXT: [[S_SROA_31_0:%.*]] = phi i32 [ [[VAL]], %[[INIT]] ], [ undef, %[[SKIP]] ] -; CHECK-NEXT: call void @use(i32 [[S_SROA_31_0]]) -; CHECK-NEXT: br label %[[CLEANUP:.*]] -; CHECK: [[CLEANUP]]: -; CHECK-NEXT: br i1 [[C2]], label %[[LOOP]], label %[[EXIT:.*]] -; CHECK: [[EXIT]]: -; CHECK-NEXT: ret void -; -entry: - %s = alloca %struct.S, align 4 - br label %loop - -loop: - call void @llvm.lifetime.start.p0(ptr %s) - br i1 %c1, label %init, label %skip - -init: - %gep0 = getelementptr inbounds %struct.S, ptr %s, i32 0, i32 0 - store i8 65, ptr %gep0, align 4 - %gep1 = getelementptr inbounds %struct.S, ptr %s, i32 0, i32 1 - store i32 %val, ptr %gep1, align 4 - %gep2 = getelementptr inbounds %struct.S, ptr %s, i32 0, i32 2 - store i8 90, ptr %gep2, align 4 - br label %read - -skip: - br label %read - -read: - %gep1r = getelementptr inbounds %struct.S, ptr %s, i32 0, i32 1 - %v = load i32, ptr %gep1r, align 4 - call void @use(i32 %v) - br label %cleanup - -cleanup: - call void @llvm.lifetime.end.p0(ptr %s) - br i1 %c2, label %loop, label %exit - -exit: - ret void -} - -; lifetime.end shortens live ranges: after lifetime.end the value is undef, -; so a PHI at the loop header carrying the value through the back-edge from -; the block containing lifetime.end is unnecessary. -define void @with_lifetime_end(i32 %val, i1 %c1, i1 %c2) { -; CHECK-LABEL: define void @with_lifetime_end( -; CHECK-SAME: i32 [[VAL:%.*]], i1 [[C1:%.*]], i1 [[C2:%.*]]) { -; CHECK-NEXT: [[ENTRY:.*:]] -; CHECK-NEXT: br label %[[LOOP:.*]] -; CHECK: [[LOOP]]: -; CHECK-NEXT: br i1 [[C1]], label %[[INIT:.*]], label %[[SKIP:.*]] -; CHECK: [[INIT]]: -; CHECK-NEXT: br label %[[READ:.*]] -; CHECK: [[SKIP]]: -; CHECK-NEXT: br label %[[READ]] -; CHECK: [[READ]]: -; CHECK-NEXT: [[S_SROA_31_0:%.*]] = phi i32 [ [[VAL]], %[[INIT]] ], [ undef, %[[SKIP]] ] -; CHECK-NEXT: call void @use(i32 [[S_SROA_31_0]]) -; CHECK-NEXT: br i1 [[C2]], label %[[LOOP]], label %[[EXIT:.*]] -; CHECK: [[EXIT]]: -; CHECK-NEXT: ret void -; -; No recurrent PHI at the loop header. -entry: - %s = alloca %struct.S, align 4 - br label %loop - -loop: - call void @llvm.lifetime.start.p0(ptr %s) - br i1 %c1, label %init, label %skip - -init: - %gep0 = getelementptr inbounds %struct.S, ptr %s, i32 0, i32 0 - store i8 65, ptr %gep0, align 4 - %gep1 = getelementptr inbounds %struct.S, ptr %s, i32 0, i32 1 - store i32 %val, ptr %gep1, align 4 - %gep2 = getelementptr inbounds %struct.S, ptr %s, i32 0, i32 2 - store i8 90, ptr %gep2, align 4 - br label %read - -skip: - br label %read - -read: - %gep1r = getelementptr inbounds %struct.S, ptr %s, i32 0, i32 1 - %v = load i32, ptr %gep1r, align 4 - call void @use(i32 %v) - call void @llvm.lifetime.end.p0(ptr %s) - br i1 %c2, label %loop, label %exit - -exit: - ret void -} _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
