https://github.com/petar-avramovic updated https://github.com/llvm/llvm-project/pull/217634
>From 5d702ab2d664fa99a0c64733aeee92f1c653035c Mon Sep 17 00:00:00 2001 From: Petar Avramovic <[email protected]> Date: Thu, 20 Aug 2026 15:43:57 +0200 Subject: [PATCH] AMDGPU/GlobalISel: Bitcasting G_TRUNC combine Creating the G_TRUNC that changes type as well. This is really the LLT::scalar trunc style that we inherited from switching to extended LLTs, very common on non-true16 targets. Affects inst-select pattern matching that were blocked by bitcast. --- llvm/lib/Target/AMDGPU/AMDGPUCombine.td | 13 +- .../CodeGen/AMDGPU/GlobalISel/fadd.bf16.ll | 8 +- .../AMDGPU/GlobalISel/fcanonicalize.bf16.ll | 9 +- .../CodeGen/AMDGPU/GlobalISel/fma.bf16.ll | 16 +- .../CodeGen/AMDGPU/GlobalISel/fmul.bf16.ll | 8 +- .../AMDGPU/GlobalISel/fp-int-conversions.ll | 3 +- .../CodeGen/AMDGPU/GlobalISel/fptrunc.bf16.ll | 204 ++++++----------- ...llvm.amdgcn.raw.buffer.store.format.f16.ll | 14 +- .../llvm.amdgcn.raw.buffer.store.ll | 8 +- .../llvm.amdgcn.raw.tbuffer.store.f16.ll | 214 ++++++++---------- ...vm.amdgcn.struct.buffer.load.format.f16.ll | 4 +- ...m.amdgcn.struct.buffer.store.format.f16.ll | 22 +- .../CodeGen/AMDGPU/isel-amdgpu-cs-chain-cc.ll | 8 +- llvm/test/CodeGen/AMDGPU/scalar-float-sop1.ll | 28 +-- 14 files changed, 216 insertions(+), 343 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/AMDGPUCombine.td b/llvm/lib/Target/AMDGPU/AMDGPUCombine.td index a11699c4f27b1..c1afcf493cbe4 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUCombine.td +++ b/llvm/lib/Target/AMDGPU/AMDGPUCombine.td @@ -255,6 +255,17 @@ def combine_or_s64_s32 : GICombineRule< (G_OR $or, $x_lo, $y), (G_MERGE_VALUES $dst, $or, $x_hi))>; +// (bitcast (trunc i32:$src)) -> (trunc i32:$src) with the bitcast result type. +// Both are scalars of the same size, so only the LLT kind differs; keeping the +// trunc alone lets matchers that look through a trunc chain still fire. +def bitcast_of_trunc : GICombineRule< + (defs root:$dst), + (match (G_TRUNC $trunc, $src), + (G_BITCAST $dst, $trunc), + [{ return MRI.getType(${dst}.getReg()).isScalar() && + MRI.getType(${trunc}.getReg()).isScalar(); }]), + (apply (G_TRUNC $dst, $src))>; + // (trunc (lshr i32:$src, 16)) -> (unmerge_hi i16:$src) // Reads the high half in place instead of shifting it down into a fresh // 32-bit register; with true16 the unmerge is just a hi16 subregister. @@ -330,7 +341,7 @@ def AMDGPUPostLegalizerCombiner: GICombiner< def AMDGPURegBankCombiner : GICombiner< "AMDGPURegBankCombinerImpl", - [unmerge_merge, unmerge_cst, unmerge_undef, + [bitcast_of_trunc, unmerge_merge, unmerge_cst, unmerge_undef, zext_trunc_fold, int_minmax_to_med3, ptr_add_immed_chain, fp_minmax_to_clamp, fp_minmax_to_med3, fmed3_intrinsic_to_clamp, identity_combines, redundant_and, constant_fold_cast_op, diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fadd.bf16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fadd.bf16.ll index 5b6edff208fd4..49cd5256fcfc9 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fadd.bf16.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fadd.bf16.ll @@ -308,7 +308,6 @@ define amdgpu_ps <2 x bfloat> @fadd_v2bf16_ss(<2 x bfloat> inreg %a, <2 x bfloat ; GFX12-NEXT: s_cselect_b32 s2, s4, s3 ; GFX12-NEXT: s_lshl_b32 s0, s0, 16 ; GFX12-NEXT: s_lshl_b32 s1, s1, 16 -; GFX12-NEXT: s_lshr_b32 s2, s2, 16 ; GFX12-NEXT: s_add_f32 s0, s0, s1 ; GFX12-NEXT: s_bfe_u32 s1, s0, 0x10010 ; GFX12-NEXT: s_or_b32 s3, s0, 0x400000 @@ -316,8 +315,7 @@ define amdgpu_ps <2 x bfloat> @fadd_v2bf16_ss(<2 x bfloat> inreg %a, <2 x bfloat ; GFX12-NEXT: s_addk_co_i32 s1, 0x7fff ; GFX12-NEXT: s_cmp_u_f32 s0, 0 ; GFX12-NEXT: s_cselect_b32 s0, s3, s1 -; GFX12-NEXT: s_lshr_b32 s0, s0, 16 -; GFX12-NEXT: s_pack_ll_b32_b16 s0, s2, s0 +; GFX12-NEXT: s_pack_hh_b32_b16 s0, s2, s0 ; GFX12-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-NEXT: ; return to shader part epilog ; @@ -340,7 +338,6 @@ define amdgpu_ps <2 x bfloat> @fadd_v2bf16_ss(<2 x bfloat> inreg %a, <2 x bfloat ; GFX1250-NEXT: s_cselect_b32 s2, s4, s3 ; GFX1250-NEXT: s_lshl_b32 s0, s0, 16 ; GFX1250-NEXT: s_lshl_b32 s1, s1, 16 -; GFX1250-NEXT: s_lshr_b32 s2, s2, 16 ; GFX1250-NEXT: s_add_f32 s0, s0, s1 ; GFX1250-NEXT: s_bfe_u32 s1, s0, 0x10010 ; GFX1250-NEXT: s_or_b32 s3, s0, 0x400000 @@ -348,8 +345,7 @@ define amdgpu_ps <2 x bfloat> @fadd_v2bf16_ss(<2 x bfloat> inreg %a, <2 x bfloat ; GFX1250-NEXT: s_addk_co_i32 s1, 0x7fff ; GFX1250-NEXT: s_cmp_u_f32 s0, 0 ; GFX1250-NEXT: s_cselect_b32 s0, s3, s1 -; GFX1250-NEXT: s_lshr_b32 s0, s0, 16 -; GFX1250-NEXT: s_pack_ll_b32_b16 s0, s2, s0 +; GFX1250-NEXT: s_pack_hh_b32_b16 s0, s2, s0 ; GFX1250-NEXT: v_mov_b32_e32 v0, s0 ; GFX1250-NEXT: ; return to shader part epilog %result = fadd <2 x bfloat> %a, %b diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fcanonicalize.bf16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fcanonicalize.bf16.ll index 086d7e295c006..9568d3573c679 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fcanonicalize.bf16.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fcanonicalize.bf16.ll @@ -217,7 +217,6 @@ define amdgpu_ps <2 x bfloat> @fcanonicalize_v2bf16_s(<2 x bfloat> inreg %src) { ; GFX12-NEXT: s_cselect_b32 s1, s3, s2 ; GFX12-NEXT: s_lshl_b32 s0, s0, 16 ; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0) -; GFX12-NEXT: s_lshr_b32 s1, s1, 16 ; GFX12-NEXT: v_max_num_f32_e64 v0, s0, s0 ; GFX12-NEXT: v_readfirstlane_b32 s0, v0 ; GFX12-NEXT: s_bfe_u32 s2, s0, 0x10010 @@ -227,9 +226,7 @@ define amdgpu_ps <2 x bfloat> @fcanonicalize_v2bf16_s(<2 x bfloat> inreg %src) { ; GFX12-NEXT: s_cmp_u_f32 s0, 0 ; GFX12-NEXT: s_cselect_b32 s0, s3, s2 ; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0) -; GFX12-NEXT: s_lshr_b32 s0, s0, 16 -; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0) -; GFX12-NEXT: s_pack_ll_b32_b16 s0, s1, s0 +; GFX12-NEXT: s_pack_hh_b32_b16 s0, s1, s0 ; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0) ; GFX12-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-NEXT: ; return to shader part epilog @@ -251,7 +248,6 @@ define amdgpu_ps <2 x bfloat> @fcanonicalize_v2bf16_s(<2 x bfloat> inreg %src) { ; GFX1250-NEXT: s_cmp_u_f32 s1, 0 ; GFX1250-NEXT: s_cselect_b32 s1, s3, s2 ; GFX1250-NEXT: s_lshl_b32 s0, s0, 16 -; GFX1250-NEXT: s_lshr_b32 s1, s1, 16 ; GFX1250-NEXT: v_max_num_f32_e64 v0, s0, s0 ; GFX1250-NEXT: v_readfirstlane_b32 s0, v0 ; GFX1250-NEXT: s_bfe_u32 s2, s0, 0x10010 @@ -260,8 +256,7 @@ define amdgpu_ps <2 x bfloat> @fcanonicalize_v2bf16_s(<2 x bfloat> inreg %src) { ; GFX1250-NEXT: s_addk_co_i32 s2, 0x7fff ; GFX1250-NEXT: s_cmp_u_f32 s0, 0 ; GFX1250-NEXT: s_cselect_b32 s0, s3, s2 -; GFX1250-NEXT: s_lshr_b32 s0, s0, 16 -; GFX1250-NEXT: s_pack_ll_b32_b16 s0, s1, s0 +; GFX1250-NEXT: s_pack_hh_b32_b16 s0, s1, s0 ; GFX1250-NEXT: v_mov_b32_e32 v0, s0 ; GFX1250-NEXT: ; return to shader part epilog %result = call <2 x bfloat> @llvm.canonicalize.v2bf16(<2 x bfloat> %src) diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fma.bf16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fma.bf16.ll index f411349cf92f8..a86f6df3e4471 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fma.bf16.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fma.bf16.ll @@ -346,15 +346,13 @@ define amdgpu_ps <2 x bfloat> @fma_v2bf16_sss(<2 x bfloat> inreg %a, <2 x bfloat ; GFX12-NEXT: s_lshl_b32 s1, s1, 16 ; GFX12-NEXT: s_lshl_b32 s2, s2, 16 ; GFX12-NEXT: s_fmac_f32 s2, s0, s1 -; GFX12-NEXT: s_lshr_b32 s1, s3, 16 ; GFX12-NEXT: s_bfe_u32 s0, s2, 0x10010 -; GFX12-NEXT: s_or_b32 s3, s2, 0x400000 +; GFX12-NEXT: s_or_b32 s1, s2, 0x400000 ; GFX12-NEXT: s_add_co_i32 s0, s0, s2 ; GFX12-NEXT: s_addk_co_i32 s0, 0x7fff ; GFX12-NEXT: s_cmp_u_f32 s2, 0 -; GFX12-NEXT: s_cselect_b32 s0, s3, s0 -; GFX12-NEXT: s_lshr_b32 s0, s0, 16 -; GFX12-NEXT: s_pack_ll_b32_b16 s0, s1, s0 +; GFX12-NEXT: s_cselect_b32 s0, s1, s0 +; GFX12-NEXT: s_pack_hh_b32_b16 s0, s3, s0 ; GFX12-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-NEXT: ; return to shader part epilog ; @@ -381,15 +379,13 @@ define amdgpu_ps <2 x bfloat> @fma_v2bf16_sss(<2 x bfloat> inreg %a, <2 x bfloat ; GFX1250-NEXT: s_lshl_b32 s1, s1, 16 ; GFX1250-NEXT: s_lshl_b32 s2, s2, 16 ; GFX1250-NEXT: s_fmac_f32 s2, s0, s1 -; GFX1250-NEXT: s_lshr_b32 s1, s3, 16 ; GFX1250-NEXT: s_bfe_u32 s0, s2, 0x10010 -; GFX1250-NEXT: s_or_b32 s3, s2, 0x400000 +; GFX1250-NEXT: s_or_b32 s1, s2, 0x400000 ; GFX1250-NEXT: s_add_co_i32 s0, s0, s2 ; GFX1250-NEXT: s_addk_co_i32 s0, 0x7fff ; GFX1250-NEXT: s_cmp_u_f32 s2, 0 -; GFX1250-NEXT: s_cselect_b32 s0, s3, s0 -; GFX1250-NEXT: s_lshr_b32 s0, s0, 16 -; GFX1250-NEXT: s_pack_ll_b32_b16 s0, s1, s0 +; GFX1250-NEXT: s_cselect_b32 s0, s1, s0 +; GFX1250-NEXT: s_pack_hh_b32_b16 s0, s3, s0 ; GFX1250-NEXT: v_mov_b32_e32 v0, s0 ; GFX1250-NEXT: ; return to shader part epilog %result = call <2 x bfloat> @llvm.fma.v2bf16(<2 x bfloat> %a, <2 x bfloat> %b, <2 x bfloat> %c) diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fmul.bf16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fmul.bf16.ll index 9c02c096aaf4c..9326fc77f13b0 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fmul.bf16.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fmul.bf16.ll @@ -308,7 +308,6 @@ define amdgpu_ps <2 x bfloat> @fmul_v2bf16_ss(<2 x bfloat> inreg %a, <2 x bfloat ; GFX12-NEXT: s_cselect_b32 s2, s4, s3 ; GFX12-NEXT: s_lshl_b32 s0, s0, 16 ; GFX12-NEXT: s_lshl_b32 s1, s1, 16 -; GFX12-NEXT: s_lshr_b32 s2, s2, 16 ; GFX12-NEXT: s_mul_f32 s0, s0, s1 ; GFX12-NEXT: s_bfe_u32 s1, s0, 0x10010 ; GFX12-NEXT: s_or_b32 s3, s0, 0x400000 @@ -316,8 +315,7 @@ define amdgpu_ps <2 x bfloat> @fmul_v2bf16_ss(<2 x bfloat> inreg %a, <2 x bfloat ; GFX12-NEXT: s_addk_co_i32 s1, 0x7fff ; GFX12-NEXT: s_cmp_u_f32 s0, 0 ; GFX12-NEXT: s_cselect_b32 s0, s3, s1 -; GFX12-NEXT: s_lshr_b32 s0, s0, 16 -; GFX12-NEXT: s_pack_ll_b32_b16 s0, s2, s0 +; GFX12-NEXT: s_pack_hh_b32_b16 s0, s2, s0 ; GFX12-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-NEXT: ; return to shader part epilog ; @@ -340,7 +338,6 @@ define amdgpu_ps <2 x bfloat> @fmul_v2bf16_ss(<2 x bfloat> inreg %a, <2 x bfloat ; GFX1250-NEXT: s_cselect_b32 s2, s4, s3 ; GFX1250-NEXT: s_lshl_b32 s0, s0, 16 ; GFX1250-NEXT: s_lshl_b32 s1, s1, 16 -; GFX1250-NEXT: s_lshr_b32 s2, s2, 16 ; GFX1250-NEXT: s_mul_f32 s0, s0, s1 ; GFX1250-NEXT: s_bfe_u32 s1, s0, 0x10010 ; GFX1250-NEXT: s_or_b32 s3, s0, 0x400000 @@ -348,8 +345,7 @@ define amdgpu_ps <2 x bfloat> @fmul_v2bf16_ss(<2 x bfloat> inreg %a, <2 x bfloat ; GFX1250-NEXT: s_addk_co_i32 s1, 0x7fff ; GFX1250-NEXT: s_cmp_u_f32 s0, 0 ; GFX1250-NEXT: s_cselect_b32 s0, s3, s1 -; GFX1250-NEXT: s_lshr_b32 s0, s0, 16 -; GFX1250-NEXT: s_pack_ll_b32_b16 s0, s2, s0 +; GFX1250-NEXT: s_pack_hh_b32_b16 s0, s2, s0 ; GFX1250-NEXT: v_mov_b32_e32 v0, s0 ; GFX1250-NEXT: ; return to shader part epilog %result = fmul <2 x bfloat> %a, %b diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fp-int-conversions.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fp-int-conversions.ll index e8a0da8c1259e..26fab4aeb914f 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fp-int-conversions.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fp-int-conversions.ll @@ -689,8 +689,7 @@ define amdgpu_ps float @fpext_hif16_to_32(<2 x half> inreg %val) { ; ; GFX12-LABEL: fpext_hif16_to_32: ; GFX12: ; %bb.0: -; GFX12: s_lshr_b32 s0, s0, 16 -; GFX12: s_cvt_f32_f16 s0, s0 +; GFX12: s_cvt_hi_f32_f16 s0, s0 ; GFX12: v_mov_b32_e32 v0, s0 ; GFX12: ; return to shader part epilog %hielt = extractelement <2 x half> %val, i32 1 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fptrunc.bf16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fptrunc.bf16.ll index f9e9b145aa955..edabf84bd3c04 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fptrunc.bf16.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fptrunc.bf16.ll @@ -422,147 +422,73 @@ define amdgpu_ps bfloat @fptrunc_f64_to_bf16_v(double %a) { } define amdgpu_ps <2 x bfloat> @fptrunc_v2f32_to_v2bf16_s(<2 x float> inreg %a) { -; GFX11-FAKE16-LABEL: fptrunc_v2f32_to_v2bf16_s: -; GFX11-FAKE16: ; %bb.0: -; GFX11-FAKE16-NEXT: s_bfe_u32 s2, s0, 0x10010 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s3, s0, 0 -; GFX11-FAKE16-NEXT: s_add_i32 s2, s2, s0 -; GFX11-FAKE16-NEXT: s_bitset1_b32 s0, 22 -; GFX11-FAKE16-NEXT: s_addk_i32 s2, 0x7fff -; GFX11-FAKE16-NEXT: s_cmp_lg_u32 s3, 0 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s3, s1, 0 -; GFX11-FAKE16-NEXT: s_cselect_b32 s0, s0, s2 -; GFX11-FAKE16-NEXT: s_bfe_u32 s2, s1, 0x10010 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1) -; GFX11-FAKE16-NEXT: s_add_i32 s2, s2, s1 -; GFX11-FAKE16-NEXT: s_bitset1_b32 s1, 22 -; GFX11-FAKE16-NEXT: s_addk_i32 s2, 0x7fff -; GFX11-FAKE16-NEXT: s_cmp_lg_u32 s3, 0 -; GFX11-FAKE16-NEXT: s_cselect_b32 s1, s1, s2 -; GFX11-FAKE16-NEXT: s_pack_hh_b32_b16 s0, s0, s1 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX11-FAKE16-NEXT: v_mov_b32_e32 v0, s0 -; GFX11-FAKE16-NEXT: ; return to shader part epilog -; -; GFX11-TRUE16-LABEL: fptrunc_v2f32_to_v2bf16_s: -; GFX11-TRUE16: ; %bb.0: -; GFX11-TRUE16-NEXT: s_bfe_u32 s2, s0, 0x10010 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s3, s0, 0 -; GFX11-TRUE16-NEXT: s_add_i32 s2, s2, s0 -; GFX11-TRUE16-NEXT: s_bitset1_b32 s0, 22 -; GFX11-TRUE16-NEXT: s_addk_i32 s2, 0x7fff -; GFX11-TRUE16-NEXT: s_cmp_lg_u32 s3, 0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s3, s1, 0 -; GFX11-TRUE16-NEXT: s_cselect_b32 s0, s0, s2 -; GFX11-TRUE16-NEXT: s_bfe_u32 s2, s1, 0x10010 -; GFX11-TRUE16-NEXT: s_lshr_b32 s0, s0, 16 -; GFX11-TRUE16-NEXT: s_add_i32 s2, s2, s1 -; GFX11-TRUE16-NEXT: s_bitset1_b32 s1, 22 -; GFX11-TRUE16-NEXT: s_addk_i32 s2, 0x7fff -; GFX11-TRUE16-NEXT: s_cmp_lg_u32 s3, 0 -; GFX11-TRUE16-NEXT: s_cselect_b32 s1, s1, s2 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) -; GFX11-TRUE16-NEXT: s_lshr_b32 s1, s1, 16 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s0, s0, s1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, s0 -; GFX11-TRUE16-NEXT: ; return to shader part epilog -; -; GFX12-FAKE16-LABEL: fptrunc_v2f32_to_v2bf16_s: -; GFX12-FAKE16: ; %bb.0: -; GFX12-FAKE16-NEXT: s_bfe_u32 s2, s0, 0x10010 -; GFX12-FAKE16-NEXT: s_or_b32 s3, s0, 0x400000 -; GFX12-FAKE16-NEXT: s_add_co_i32 s2, s2, s0 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX12-FAKE16-NEXT: s_addk_co_i32 s2, 0x7fff -; GFX12-FAKE16-NEXT: s_cmp_u_f32 s0, 0 -; GFX12-FAKE16-NEXT: s_cselect_b32 s0, s3, s2 -; GFX12-FAKE16-NEXT: s_bfe_u32 s2, s1, 0x10010 -; GFX12-FAKE16-NEXT: s_or_b32 s3, s1, 0x400000 -; GFX12-FAKE16-NEXT: s_add_co_i32 s2, s2, s1 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) -; GFX12-FAKE16-NEXT: s_addk_co_i32 s2, 0x7fff -; GFX12-FAKE16-NEXT: s_cmp_u_f32 s1, 0 -; GFX12-FAKE16-NEXT: s_cselect_b32 s1, s3, s2 -; GFX12-FAKE16-NEXT: s_pack_hh_b32_b16 s0, s0, s1 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX12-FAKE16-NEXT: v_mov_b32_e32 v0, s0 -; GFX12-FAKE16-NEXT: ; return to shader part epilog -; -; GFX12-TRUE16-LABEL: fptrunc_v2f32_to_v2bf16_s: -; GFX12-TRUE16: ; %bb.0: -; GFX12-TRUE16-NEXT: s_bfe_u32 s2, s0, 0x10010 -; GFX12-TRUE16-NEXT: s_or_b32 s3, s0, 0x400000 -; GFX12-TRUE16-NEXT: s_add_co_i32 s2, s2, s0 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX12-TRUE16-NEXT: s_addk_co_i32 s2, 0x7fff -; GFX12-TRUE16-NEXT: s_cmp_u_f32 s0, 0 -; GFX12-TRUE16-NEXT: s_cselect_b32 s0, s3, s2 -; GFX12-TRUE16-NEXT: s_bfe_u32 s2, s1, 0x10010 -; GFX12-TRUE16-NEXT: s_lshr_b32 s0, s0, 16 -; GFX12-TRUE16-NEXT: s_add_co_i32 s2, s2, s1 -; GFX12-TRUE16-NEXT: s_or_b32 s3, s1, 0x400000 -; GFX12-TRUE16-NEXT: s_addk_co_i32 s2, 0x7fff -; GFX12-TRUE16-NEXT: s_cmp_u_f32 s1, 0 -; GFX12-TRUE16-NEXT: s_cselect_b32 s1, s3, s2 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) -; GFX12-TRUE16-NEXT: s_lshr_b32 s1, s1, 16 -; GFX12-TRUE16-NEXT: s_pack_ll_b32_b16 s0, s0, s1 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX12-TRUE16-NEXT: v_mov_b32_e32 v0, s0 -; GFX12-TRUE16-NEXT: ; return to shader part epilog +; GFX11-LABEL: fptrunc_v2f32_to_v2bf16_s: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_bfe_u32 s2, s0, 0x10010 +; GFX11-NEXT: v_cmp_u_f32_e64 s3, s0, 0 +; GFX11-NEXT: s_add_i32 s2, s2, s0 +; GFX11-NEXT: s_bitset1_b32 s0, 22 +; GFX11-NEXT: s_addk_i32 s2, 0x7fff +; GFX11-NEXT: s_cmp_lg_u32 s3, 0 +; GFX11-NEXT: v_cmp_u_f32_e64 s3, s1, 0 +; GFX11-NEXT: s_cselect_b32 s0, s0, s2 +; GFX11-NEXT: s_bfe_u32 s2, s1, 0x10010 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1) +; GFX11-NEXT: s_add_i32 s2, s2, s1 +; GFX11-NEXT: s_bitset1_b32 s1, 22 +; GFX11-NEXT: s_addk_i32 s2, 0x7fff +; GFX11-NEXT: s_cmp_lg_u32 s3, 0 +; GFX11-NEXT: s_cselect_b32 s1, s1, s2 +; GFX11-NEXT: s_pack_hh_b32_b16 s0, s0, s1 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-NEXT: v_mov_b32_e32 v0, s0 +; GFX11-NEXT: ; return to shader part epilog ; -; GFX1250-FAKE16-LABEL: fptrunc_v2f32_to_v2bf16_s: -; GFX1250-FAKE16: ; %bb.0: -; GFX1250-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 -; GFX1250-FAKE16-NEXT: s_mov_b64 s[64:65], 0 -; GFX1250-FAKE16-NEXT: v_nop -; GFX1250-FAKE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-FAKE16-NEXT: s_bfe_u32 s2, s0, 0x10010 -; GFX1250-FAKE16-NEXT: s_or_b32 s3, s0, 0x400000 -; GFX1250-FAKE16-NEXT: s_add_co_i32 s2, s2, s0 -; GFX1250-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX1250-FAKE16-NEXT: s_addk_co_i32 s2, 0x7fff -; GFX1250-FAKE16-NEXT: s_cmp_u_f32 s0, 0 -; GFX1250-FAKE16-NEXT: s_cselect_b32 s0, s3, s2 -; GFX1250-FAKE16-NEXT: s_bfe_u32 s2, s1, 0x10010 -; GFX1250-FAKE16-NEXT: s_or_b32 s3, s1, 0x400000 -; GFX1250-FAKE16-NEXT: s_add_co_i32 s2, s2, s1 -; GFX1250-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) -; GFX1250-FAKE16-NEXT: s_addk_co_i32 s2, 0x7fff -; GFX1250-FAKE16-NEXT: s_cmp_u_f32 s1, 0 -; GFX1250-FAKE16-NEXT: s_cselect_b32 s1, s3, s2 -; GFX1250-FAKE16-NEXT: s_pack_hh_b32_b16 s0, s0, s1 -; GFX1250-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX1250-FAKE16-NEXT: v_mov_b32_e32 v0, s0 -; GFX1250-FAKE16-NEXT: ; return to shader part epilog +; GFX12-LABEL: fptrunc_v2f32_to_v2bf16_s: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_bfe_u32 s2, s0, 0x10010 +; GFX12-NEXT: s_or_b32 s3, s0, 0x400000 +; GFX12-NEXT: s_add_co_i32 s2, s2, s0 +; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX12-NEXT: s_addk_co_i32 s2, 0x7fff +; GFX12-NEXT: s_cmp_u_f32 s0, 0 +; GFX12-NEXT: s_cselect_b32 s0, s3, s2 +; GFX12-NEXT: s_bfe_u32 s2, s1, 0x10010 +; GFX12-NEXT: s_or_b32 s3, s1, 0x400000 +; GFX12-NEXT: s_add_co_i32 s2, s2, s1 +; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) +; GFX12-NEXT: s_addk_co_i32 s2, 0x7fff +; GFX12-NEXT: s_cmp_u_f32 s1, 0 +; GFX12-NEXT: s_cselect_b32 s1, s3, s2 +; GFX12-NEXT: s_pack_hh_b32_b16 s0, s0, s1 +; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX12-NEXT: v_mov_b32_e32 v0, s0 +; GFX12-NEXT: ; return to shader part epilog ; -; GFX1250-TRUE16-LABEL: fptrunc_v2f32_to_v2bf16_s: -; GFX1250-TRUE16: ; %bb.0: -; GFX1250-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 -; GFX1250-TRUE16-NEXT: s_mov_b64 s[64:65], 0 -; GFX1250-TRUE16-NEXT: v_nop -; GFX1250-TRUE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-TRUE16-NEXT: s_bfe_u32 s2, s0, 0x10010 -; GFX1250-TRUE16-NEXT: s_or_b32 s3, s0, 0x400000 -; GFX1250-TRUE16-NEXT: s_add_co_i32 s2, s2, s0 -; GFX1250-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX1250-TRUE16-NEXT: s_addk_co_i32 s2, 0x7fff -; GFX1250-TRUE16-NEXT: s_cmp_u_f32 s0, 0 -; GFX1250-TRUE16-NEXT: s_cselect_b32 s0, s3, s2 -; GFX1250-TRUE16-NEXT: s_bfe_u32 s2, s1, 0x10010 -; GFX1250-TRUE16-NEXT: s_lshr_b32 s0, s0, 16 -; GFX1250-TRUE16-NEXT: s_add_co_i32 s2, s2, s1 -; GFX1250-TRUE16-NEXT: s_or_b32 s3, s1, 0x400000 -; GFX1250-TRUE16-NEXT: s_addk_co_i32 s2, 0x7fff -; GFX1250-TRUE16-NEXT: s_cmp_u_f32 s1, 0 -; GFX1250-TRUE16-NEXT: s_cselect_b32 s1, s3, s2 -; GFX1250-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) -; GFX1250-TRUE16-NEXT: s_lshr_b32 s1, s1, 16 -; GFX1250-TRUE16-NEXT: s_pack_ll_b32_b16 s0, s0, s1 -; GFX1250-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX1250-TRUE16-NEXT: v_mov_b32_e32 v0, s0 -; GFX1250-TRUE16-NEXT: ; return to shader part epilog +; GFX1250-LABEL: fptrunc_v2f32_to_v2bf16_s: +; GFX1250: ; %bb.0: +; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 +; GFX1250-NEXT: s_mov_b64 s[64:65], 0 +; GFX1250-NEXT: v_nop +; GFX1250-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE +; GFX1250-NEXT: s_bfe_u32 s2, s0, 0x10010 +; GFX1250-NEXT: s_or_b32 s3, s0, 0x400000 +; GFX1250-NEXT: s_add_co_i32 s2, s2, s0 +; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX1250-NEXT: s_addk_co_i32 s2, 0x7fff +; GFX1250-NEXT: s_cmp_u_f32 s0, 0 +; GFX1250-NEXT: s_cselect_b32 s0, s3, s2 +; GFX1250-NEXT: s_bfe_u32 s2, s1, 0x10010 +; GFX1250-NEXT: s_or_b32 s3, s1, 0x400000 +; GFX1250-NEXT: s_add_co_i32 s2, s2, s1 +; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) +; GFX1250-NEXT: s_addk_co_i32 s2, 0x7fff +; GFX1250-NEXT: s_cmp_u_f32 s1, 0 +; GFX1250-NEXT: s_cselect_b32 s1, s3, s2 +; GFX1250-NEXT: s_pack_hh_b32_b16 s0, s0, s1 +; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX1250-NEXT: v_mov_b32_e32 v0, s0 +; GFX1250-NEXT: ; return to shader part epilog %result = fptrunc <2 x float> %a to <2 x bfloat> ret <2 x bfloat> %result } diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.format.f16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.format.f16.ll index e355992416d1f..699aca2631ae0 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.format.f16.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.format.f16.ll @@ -44,11 +44,9 @@ define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffse ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_16 = COPY [[COPY4]].lo16 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6 - ; GFX12-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY5]] - ; GFX12-NEXT: BUFFER_STORE_FORMAT_D16_X_VBUFFER_OFFEN_exact [[COPY8]], [[COPY6]], [[REG_SEQUENCE]], [[COPY7]], 0, 0, 0, implicit $exec :: (dereferenceable store (f16), align 1, addrspace 8) + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: BUFFER_STORE_FORMAT_D16_X_VBUFFER_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, implicit $exec :: (dereferenceable store (f16), align 1, addrspace 8) ; GFX12-NEXT: S_ENDPGM 0 call void @llvm.amdgcn.raw.buffer.store.format.f16(half %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0) ret void @@ -93,10 +91,8 @@ define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__voffset_409 ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_16 = COPY [[COPY4]].lo16 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY5]] - ; GFX12-NEXT: BUFFER_STORE_FORMAT_D16_X_VBUFFER_OFFSET_exact [[COPY7]], [[REG_SEQUENCE]], [[COPY6]], 4095, 0, 0, implicit $exec :: (dereferenceable store (f16), align 1, addrspace 8) + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: BUFFER_STORE_FORMAT_D16_X_VBUFFER_OFFSET_exact [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 4095, 0, 0, implicit $exec :: (dereferenceable store (f16), align 1, addrspace 8) ; GFX12-NEXT: S_ENDPGM 0 call void @llvm.amdgcn.raw.buffer.store.format.f16(half %val, <4 x i32> %rsrc, i32 4095, i32 %soffset, i32 0) ret void diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.ll index a9ada36d4b2ff..f9019b82cbf62 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.ll @@ -968,11 +968,9 @@ define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_16 = COPY [[COPY4]].lo16 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6 - ; GFX12-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY5]] - ; GFX12-NEXT: BUFFER_STORE_SHORT_VBUFFER_OFFEN_exact [[COPY8]], [[COPY6]], [[REG_SEQUENCE]], [[COPY7]], 0, 0, 0, implicit $exec :: (dereferenceable store (f16), align 1, addrspace 8) + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: BUFFER_STORE_SHORT_VBUFFER_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, implicit $exec :: (dereferenceable store (f16), align 1, addrspace 8) ; GFX12-NEXT: S_ENDPGM 0 call void @llvm.amdgcn.raw.buffer.store.f16(half %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0) ret void diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.f16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.f16.ll index 4225ab16bac30..dc338db089823 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.f16.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.f16.ll @@ -39,16 +39,14 @@ define amdgpu_ps void @raw_tbuffer_store_f16__sgpr_rsrc__vgpr_voffset__sgpr_soff ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 ; GFX12-NEXT: {{ $}} ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:vgpr_16 = COPY [[COPY]].lo16 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr5 - ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6 - ; GFX12-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY1]] - ; GFX12-NEXT: TBUFFER_STORE_FORMAT_D16_X_VBUFFER_OFFEN_exact [[COPY8]], [[COPY6]], [[REG_SEQUENCE]], [[COPY7]], 0, 78, 0, 0, implicit $exec :: (dereferenceable store (f16), align 1, addrspace 8) + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: TBUFFER_STORE_FORMAT_D16_X_VBUFFER_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 78, 0, 0, implicit $exec :: (dereferenceable store (f16), align 1, addrspace 8) ; GFX12-NEXT: S_ENDPGM 0 call void @llvm.amdgcn.raw.tbuffer.store.f16(half %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 0) ret void @@ -327,38 +325,36 @@ define amdgpu_ps void @raw_tbuffer_store_f16__vgpr_rsrc__vgpr_voffset__sgpr_soff ; GFX12-NEXT: liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 ; GFX12-NEXT: {{ $}} ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:vgpr_16 = COPY [[COPY]].lo16 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr2 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr3 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr4 - ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr5 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY1]] + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4 + ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr2 ; GFX12-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_MOV_B32 $exec_lo ; GFX12-NEXT: {{ $}} ; GFX12-NEXT: bb.2: ; GFX12-NEXT: successors: %bb.3(0x80000000) ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY2]], implicit $exec - ; GFX12-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY3]], implicit $exec - ; GFX12-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec - ; GFX12-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]], implicit $exec + ; GFX12-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY1]], implicit $exec + ; GFX12-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY2]], implicit $exec + ; GFX12-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY3]], implicit $exec + ; GFX12-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec ; GFX12-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3 - ; GFX12-NEXT: [[COPY9:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1 - ; GFX12-NEXT: [[COPY10:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3 - ; GFX12-NEXT: [[COPY11:%[0-9]+]]:sreg_64 = COPY [[REG_SEQUENCE1]].sub0_sub1 - ; GFX12-NEXT: [[COPY12:%[0-9]+]]:sreg_64 = COPY [[REG_SEQUENCE1]].sub2_sub3 - ; GFX12-NEXT: [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U64_e64 [[COPY11]], [[COPY9]], implicit $exec - ; GFX12-NEXT: [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U64_e64 [[COPY12]], [[COPY10]], implicit $exec + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1 + ; GFX12-NEXT: [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3 + ; GFX12-NEXT: [[COPY9:%[0-9]+]]:sreg_64 = COPY [[REG_SEQUENCE1]].sub0_sub1 + ; GFX12-NEXT: [[COPY10:%[0-9]+]]:sreg_64 = COPY [[REG_SEQUENCE1]].sub2_sub3 + ; GFX12-NEXT: [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U64_e64 [[COPY9]], [[COPY7]], implicit $exec + ; GFX12-NEXT: [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U64_e64 [[COPY10]], [[COPY8]], implicit $exec ; GFX12-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_B32 [[V_CMP_EQ_U64_e64_]], [[V_CMP_EQ_U64_e64_1]], implicit-def dead $scc ; GFX12-NEXT: [[S_AND_SAVEEXEC_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_SAVEEXEC_B32 killed [[S_AND_B32_]], implicit-def $exec, implicit-def $scc, implicit $exec ; GFX12-NEXT: {{ $}} ; GFX12-NEXT: bb.3: ; GFX12-NEXT: successors: %bb.4(0x40000000), %bb.2(0x40000000) ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: TBUFFER_STORE_FORMAT_D16_X_VBUFFER_OFFEN_exact [[COPY8]], [[COPY6]], [[REG_SEQUENCE1]], [[COPY7]], 0, 94, 0, 0, implicit $exec :: (dereferenceable store (f16), align 1, addrspace 8) + ; GFX12-NEXT: TBUFFER_STORE_FORMAT_D16_X_VBUFFER_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE1]], [[COPY6]], 0, 94, 0, 0, implicit $exec :: (dereferenceable store (f16), align 1, addrspace 8) ; GFX12-NEXT: $exec_lo = S_XOR_B32_term $exec_lo, [[S_AND_SAVEEXEC_B32_]], implicit-def $scc ; GFX12-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec ; GFX12-NEXT: {{ $}} @@ -481,41 +477,39 @@ define amdgpu_ps void @raw_tbuffer_store_f16__vgpr_rsrc__vgpr_voffset__vgpr_soff ; GFX12-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6 ; GFX12-NEXT: {{ $}} ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:vgpr_16 = COPY [[COPY]].lo16 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr2 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr3 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr4 - ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr5 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr6 - ; GFX12-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY1]] + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4 + ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr6 ; GFX12-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_MOV_B32 $exec_lo ; GFX12-NEXT: {{ $}} ; GFX12-NEXT: bb.2: ; GFX12-NEXT: successors: %bb.3(0x80000000) ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY2]], implicit $exec - ; GFX12-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY3]], implicit $exec - ; GFX12-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec - ; GFX12-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]], implicit $exec + ; GFX12-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY1]], implicit $exec + ; GFX12-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY2]], implicit $exec + ; GFX12-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY3]], implicit $exec + ; GFX12-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec ; GFX12-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3 - ; GFX12-NEXT: [[COPY9:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1 - ; GFX12-NEXT: [[COPY10:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3 - ; GFX12-NEXT: [[COPY11:%[0-9]+]]:sreg_64 = COPY [[REG_SEQUENCE1]].sub0_sub1 - ; GFX12-NEXT: [[COPY12:%[0-9]+]]:sreg_64 = COPY [[REG_SEQUENCE1]].sub2_sub3 - ; GFX12-NEXT: [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U64_e64 [[COPY11]], [[COPY9]], implicit $exec - ; GFX12-NEXT: [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U64_e64 [[COPY12]], [[COPY10]], implicit $exec + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1 + ; GFX12-NEXT: [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3 + ; GFX12-NEXT: [[COPY9:%[0-9]+]]:sreg_64 = COPY [[REG_SEQUENCE1]].sub0_sub1 + ; GFX12-NEXT: [[COPY10:%[0-9]+]]:sreg_64 = COPY [[REG_SEQUENCE1]].sub2_sub3 + ; GFX12-NEXT: [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U64_e64 [[COPY9]], [[COPY7]], implicit $exec + ; GFX12-NEXT: [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U64_e64 [[COPY10]], [[COPY8]], implicit $exec ; GFX12-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_B32 [[V_CMP_EQ_U64_e64_]], [[V_CMP_EQ_U64_e64_1]], implicit-def dead $scc - ; GFX12-NEXT: [[V_READFIRSTLANE_B32_4:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]], implicit $exec - ; GFX12-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U32_e64 [[V_READFIRSTLANE_B32_4]], [[COPY7]], implicit $exec + ; GFX12-NEXT: [[V_READFIRSTLANE_B32_4:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]], implicit $exec + ; GFX12-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U32_e64 [[V_READFIRSTLANE_B32_4]], [[COPY6]], implicit $exec ; GFX12-NEXT: [[S_AND_B32_1:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_B32 [[S_AND_B32_]], [[V_CMP_EQ_U32_e64_]], implicit-def dead $scc ; GFX12-NEXT: [[S_AND_SAVEEXEC_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_SAVEEXEC_B32 killed [[S_AND_B32_1]], implicit-def $exec, implicit-def $scc, implicit $exec ; GFX12-NEXT: {{ $}} ; GFX12-NEXT: bb.3: ; GFX12-NEXT: successors: %bb.4(0x40000000), %bb.2(0x40000000) ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: TBUFFER_STORE_FORMAT_D16_X_VBUFFER_OFFEN_exact [[COPY8]], [[COPY6]], [[REG_SEQUENCE1]], [[V_READFIRSTLANE_B32_4]], 0, 78, 0, 0, implicit $exec :: (dereferenceable store (f16), align 1, addrspace 8) + ; GFX12-NEXT: TBUFFER_STORE_FORMAT_D16_X_VBUFFER_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE1]], [[V_READFIRSTLANE_B32_4]], 0, 78, 0, 0, implicit $exec :: (dereferenceable store (f16), align 1, addrspace 8) ; GFX12-NEXT: $exec_lo = S_XOR_B32_term $exec_lo, [[S_AND_SAVEEXEC_B32_]], implicit-def $scc ; GFX12-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec ; GFX12-NEXT: {{ $}} @@ -640,42 +634,40 @@ define amdgpu_ps void @raw_tbuffer_store_f16__vgpr_rsrc__sgpr_voffset__vgpr_soff ; GFX12-NEXT: liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 ; GFX12-NEXT: {{ $}} ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:vgpr_16 = COPY [[COPY]].lo16 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr2 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr3 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr4 - ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr5 - ; GFX12-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY1]] - ; GFX12-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[COPY6]] + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4 + ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr5 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY5]] ; GFX12-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_MOV_B32 $exec_lo ; GFX12-NEXT: {{ $}} ; GFX12-NEXT: bb.2: ; GFX12-NEXT: successors: %bb.3(0x80000000) ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY2]], implicit $exec - ; GFX12-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY3]], implicit $exec - ; GFX12-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec - ; GFX12-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]], implicit $exec + ; GFX12-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY1]], implicit $exec + ; GFX12-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY2]], implicit $exec + ; GFX12-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY3]], implicit $exec + ; GFX12-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec ; GFX12-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3 - ; GFX12-NEXT: [[COPY10:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1 - ; GFX12-NEXT: [[COPY11:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3 - ; GFX12-NEXT: [[COPY12:%[0-9]+]]:sreg_64 = COPY [[REG_SEQUENCE1]].sub0_sub1 - ; GFX12-NEXT: [[COPY13:%[0-9]+]]:sreg_64 = COPY [[REG_SEQUENCE1]].sub2_sub3 - ; GFX12-NEXT: [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U64_e64 [[COPY12]], [[COPY10]], implicit $exec - ; GFX12-NEXT: [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U64_e64 [[COPY13]], [[COPY11]], implicit $exec + ; GFX12-NEXT: [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1 + ; GFX12-NEXT: [[COPY9:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3 + ; GFX12-NEXT: [[COPY10:%[0-9]+]]:sreg_64 = COPY [[REG_SEQUENCE1]].sub0_sub1 + ; GFX12-NEXT: [[COPY11:%[0-9]+]]:sreg_64 = COPY [[REG_SEQUENCE1]].sub2_sub3 + ; GFX12-NEXT: [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U64_e64 [[COPY10]], [[COPY8]], implicit $exec + ; GFX12-NEXT: [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U64_e64 [[COPY11]], [[COPY9]], implicit $exec ; GFX12-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_B32 [[V_CMP_EQ_U64_e64_]], [[V_CMP_EQ_U64_e64_1]], implicit-def dead $scc - ; GFX12-NEXT: [[V_READFIRSTLANE_B32_4:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]], implicit $exec - ; GFX12-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U32_e64 [[V_READFIRSTLANE_B32_4]], [[COPY7]], implicit $exec + ; GFX12-NEXT: [[V_READFIRSTLANE_B32_4:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]], implicit $exec + ; GFX12-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U32_e64 [[V_READFIRSTLANE_B32_4]], [[COPY6]], implicit $exec ; GFX12-NEXT: [[S_AND_B32_1:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_B32 [[S_AND_B32_]], [[V_CMP_EQ_U32_e64_]], implicit-def dead $scc ; GFX12-NEXT: [[S_AND_SAVEEXEC_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_SAVEEXEC_B32 killed [[S_AND_B32_1]], implicit-def $exec, implicit-def $scc, implicit $exec ; GFX12-NEXT: {{ $}} ; GFX12-NEXT: bb.3: ; GFX12-NEXT: successors: %bb.4(0x40000000), %bb.2(0x40000000) ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: TBUFFER_STORE_FORMAT_D16_X_VBUFFER_OFFEN_exact [[COPY8]], [[COPY9]], [[REG_SEQUENCE1]], [[V_READFIRSTLANE_B32_4]], 0, 78, 0, 0, implicit $exec :: (dereferenceable store (f16), align 1, addrspace 8) + ; GFX12-NEXT: TBUFFER_STORE_FORMAT_D16_X_VBUFFER_OFFEN_exact [[COPY]], [[COPY7]], [[REG_SEQUENCE1]], [[V_READFIRSTLANE_B32_4]], 0, 78, 0, 0, implicit $exec :: (dereferenceable store (f16), align 1, addrspace 8) ; GFX12-NEXT: $exec_lo = S_XOR_B32_term $exec_lo, [[S_AND_SAVEEXEC_B32_]], implicit-def $scc ; GFX12-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec ; GFX12-NEXT: {{ $}} @@ -726,16 +718,14 @@ define amdgpu_ps void @raw_tbuffer_store_f16__sgpr_rsrc__vgpr_voffset__sgpr_soff ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 ; GFX12-NEXT: {{ $}} ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:vgpr_16 = COPY [[COPY]].lo16 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr5 - ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6 - ; GFX12-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY1]] - ; GFX12-NEXT: TBUFFER_STORE_FORMAT_D16_X_VBUFFER_OFFEN_exact [[COPY8]], [[COPY6]], [[REG_SEQUENCE]], [[COPY7]], 0, 78, 1, 0, implicit $exec :: (dereferenceable store (f16), align 1, addrspace 8) + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: TBUFFER_STORE_FORMAT_D16_X_VBUFFER_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 78, 1, 0, implicit $exec :: (dereferenceable store (f16), align 1, addrspace 8) ; GFX12-NEXT: S_ENDPGM 0 call void @llvm.amdgcn.raw.tbuffer.store.f16(half %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 1) ret void @@ -777,16 +767,14 @@ define amdgpu_ps void @raw_tbuffer_store_f16__sgpr_rsrc__vgpr_voffset__sgpr_soff ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 ; GFX12-NEXT: {{ $}} ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:vgpr_16 = COPY [[COPY]].lo16 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr5 - ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6 - ; GFX12-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY1]] - ; GFX12-NEXT: TBUFFER_STORE_FORMAT_D16_X_VBUFFER_OFFEN_exact [[COPY8]], [[COPY6]], [[REG_SEQUENCE]], [[COPY7]], 0, 78, 2, 0, implicit $exec :: (dereferenceable store (f16), align 1, addrspace 8) + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: TBUFFER_STORE_FORMAT_D16_X_VBUFFER_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 78, 2, 0, implicit $exec :: (dereferenceable store (f16), align 1, addrspace 8) ; GFX12-NEXT: S_ENDPGM 0 call void @llvm.amdgcn.raw.tbuffer.store.f16(half %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 2) ret void @@ -828,16 +816,14 @@ define amdgpu_ps void @raw_tbuffer_store_f16__sgpr_rsrc__vgpr_voffset__sgpr_soff ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 ; GFX12-NEXT: {{ $}} ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:vgpr_16 = COPY [[COPY]].lo16 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr5 - ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6 - ; GFX12-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY1]] - ; GFX12-NEXT: TBUFFER_STORE_FORMAT_D16_X_VBUFFER_OFFEN_exact [[COPY8]], [[COPY6]], [[REG_SEQUENCE]], [[COPY7]], 0, 78, 3, 0, implicit $exec :: (dereferenceable store (f16), align 1, addrspace 8) + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: TBUFFER_STORE_FORMAT_D16_X_VBUFFER_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 78, 3, 0, implicit $exec :: (dereferenceable store (f16), align 1, addrspace 8) ; GFX12-NEXT: S_ENDPGM 0 call void @llvm.amdgcn.raw.tbuffer.store.f16(half %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 3) ret void @@ -879,16 +865,14 @@ define amdgpu_ps void @raw_tbuffer_store_f16__sgpr_rsrc__vgpr_voffset__sgpr_soff ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 ; GFX12-NEXT: {{ $}} ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:vgpr_16 = COPY [[COPY]].lo16 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr5 - ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6 - ; GFX12-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY1]] - ; GFX12-NEXT: TBUFFER_STORE_FORMAT_D16_X_VBUFFER_OFFEN_exact [[COPY8]], [[COPY6]], [[REG_SEQUENCE]], [[COPY7]], 0, 78, 4, 0, implicit $exec :: (dereferenceable store (f16), align 1, addrspace 8) + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: TBUFFER_STORE_FORMAT_D16_X_VBUFFER_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 78, 4, 0, implicit $exec :: (dereferenceable store (f16), align 1, addrspace 8) ; GFX12-NEXT: S_ENDPGM 0 call void @llvm.amdgcn.raw.tbuffer.store.f16(half %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 4) ret void diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.format.f16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.format.f16.ll index 1588f254b801d..55045e250819b 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.format.f16.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.format.f16.ll @@ -511,9 +511,7 @@ define amdgpu_ps half @struct_buffer_load_format_i16__sgpr_rsrc__vgpr_vindex__vg ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 ; GFX12-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1 ; GFX12-NEXT: [[BUFFER_LOAD_FORMAT_D16_X_VBUFFER_BOTHEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_D16_X_VBUFFER_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, implicit $exec :: (dereferenceable load (i16), align 1, addrspace 8) - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:vgpr_16 = COPY [[BUFFER_LOAD_FORMAT_D16_X_VBUFFER_BOTHEN]].lo16 - ; GFX12-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY7]] - ; GFX12-NEXT: $vgpr0 = COPY [[COPY8]] + ; GFX12-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_FORMAT_D16_X_VBUFFER_BOTHEN]] ; GFX12-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 %val = call i16 @llvm.amdgcn.struct.buffer.load.format.i16(<4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0) %fval = bitcast i16 %val to half diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.store.format.f16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.store.format.f16.ll index 8473cbb2ddceb..5517a8c2728ac 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.store.format.f16.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.store.format.f16.ll @@ -43,18 +43,16 @@ define amdgpu_ps void @struct_buffer_store_format_f16__vgpr_val__sgpr_rsrc__vgpr ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2 ; GFX12-NEXT: {{ $}} ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:vgpr_16 = COPY [[COPY]].lo16 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr5 - ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr2 - ; GFX12-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr6 - ; GFX12-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[COPY1]] - ; GFX12-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY7]], %subreg.sub1 - ; GFX12-NEXT: BUFFER_STORE_FORMAT_D16_X_VBUFFER_BOTHEN_exact [[COPY9]], [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY8]], 0, 0, 0, implicit $exec :: (dereferenceable store (f16), align 1, addrspace 8) + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY5]], %subreg.sub0, [[COPY6]], %subreg.sub1 + ; GFX12-NEXT: BUFFER_STORE_FORMAT_D16_X_VBUFFER_BOTHEN_exact [[COPY]], [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY7]], 0, 0, 0, implicit $exec :: (dereferenceable store (f16), align 1, addrspace 8) ; GFX12-NEXT: S_ENDPGM 0 call void @llvm.amdgcn.struct.buffer.store.format.f16(half %val, <4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0) ret void diff --git a/llvm/test/CodeGen/AMDGPU/isel-amdgpu-cs-chain-cc.ll b/llvm/test/CodeGen/AMDGPU/isel-amdgpu-cs-chain-cc.ll index e99181f425be9..1d50caa3722a9 100644 --- a/llvm/test/CodeGen/AMDGPU/isel-amdgpu-cs-chain-cc.ll +++ b/llvm/test/CodeGen/AMDGPU/isel-amdgpu-cs-chain-cc.ll @@ -527,11 +527,9 @@ define amdgpu_cs_chain void @amdgpu_cs_chain_cc_half(half inreg %a, half %b) { ; GISEL-GFX11-NEXT: {{ $}} ; GISEL-GFX11-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GISEL-GFX11-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr8 - ; GISEL-GFX11-NEXT: [[COPY2:%[0-9]+]]:vgpr_16 = COPY [[COPY1]].lo16 ; GISEL-GFX11-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc, implicit-def $sgpr32, implicit $sgpr32 ; GISEL-GFX11-NEXT: $vgpr0 = COPY [[COPY]] - ; GISEL-GFX11-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY2]] - ; GISEL-GFX11-NEXT: $vgpr1 = COPY [[COPY3]] + ; GISEL-GFX11-NEXT: $vgpr1 = COPY [[COPY1]] ; GISEL-GFX11-NEXT: [[SI_PC_ADD_REL_OFFSET:%[0-9]+]]:sreg_64 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-gotprel32-lo) @use, target-flags(amdgpu-gotprel32-hi) @use, implicit-def $scc ; GISEL-GFX11-NEXT: [[S_LOAD_DWORDX2_IMM:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM [[SI_PC_ADD_REL_OFFSET]], 0, 0 :: (dereferenceable invariant load (p0) from got, addrspace 4) ; GISEL-GFX11-NEXT: $sgpr30_sgpr31 = noconvergent SI_CALL [[S_LOAD_DWORDX2_IMM]], @use, csr_amdgpu_si_gfx, implicit $vgpr0, implicit $vgpr1 @@ -597,11 +595,9 @@ define amdgpu_cs_chain void @amdgpu_cs_chain_cc_bfloat(bfloat inreg %a, bfloat % ; GISEL-GFX11-NEXT: {{ $}} ; GISEL-GFX11-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GISEL-GFX11-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr8 - ; GISEL-GFX11-NEXT: [[COPY2:%[0-9]+]]:vgpr_16 = COPY [[COPY1]].lo16 ; GISEL-GFX11-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc, implicit-def $sgpr32, implicit $sgpr32 ; GISEL-GFX11-NEXT: $vgpr0 = COPY [[COPY]] - ; GISEL-GFX11-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY2]] - ; GISEL-GFX11-NEXT: $vgpr1 = COPY [[COPY3]] + ; GISEL-GFX11-NEXT: $vgpr1 = COPY [[COPY1]] ; GISEL-GFX11-NEXT: [[SI_PC_ADD_REL_OFFSET:%[0-9]+]]:sreg_64 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-gotprel32-lo) @use, target-flags(amdgpu-gotprel32-hi) @use, implicit-def $scc ; GISEL-GFX11-NEXT: [[S_LOAD_DWORDX2_IMM:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM [[SI_PC_ADD_REL_OFFSET]], 0, 0 :: (dereferenceable invariant load (p0) from got, addrspace 4) ; GISEL-GFX11-NEXT: $sgpr30_sgpr31 = noconvergent SI_CALL [[S_LOAD_DWORDX2_IMM]], @use, csr_amdgpu_si_gfx, implicit $vgpr0, implicit $vgpr1 diff --git a/llvm/test/CodeGen/AMDGPU/scalar-float-sop1.ll b/llvm/test/CodeGen/AMDGPU/scalar-float-sop1.ll index 965dc1c048b90..f2fbb1bd4e43d 100644 --- a/llvm/test/CodeGen/AMDGPU/scalar-float-sop1.ll +++ b/llvm/test/CodeGen/AMDGPU/scalar-float-sop1.ll @@ -74,28 +74,12 @@ define amdgpu_vs float @fpext_f16_to_f32(half inreg %val) { } define amdgpu_vs float @fpext_hif16_to_32(<2 x half> inreg %val) { -; SDAG-LABEL: fpext_hif16_to_32: -; SDAG: ; %bb.0: -; SDAG-NEXT: s_cvt_hi_f32_f16 s0, s0 -; SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_3) -; SDAG-NEXT: v_mov_b32_e32 v0, s0 -; SDAG-NEXT: ; return to shader part epilog -; -; GISEL-GFX11-LABEL: fpext_hif16_to_32: -; GISEL-GFX11: ; %bb.0: -; GISEL-GFX11-NEXT: s_lshr_b32 s0, s0, 16 -; GISEL-GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_3) -; GISEL-GFX11-NEXT: s_cvt_f32_f16 s0, s0 -; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s0 -; GISEL-GFX11-NEXT: ; return to shader part epilog -; -; GISEL-GFX12-LABEL: fpext_hif16_to_32: -; GISEL-GFX12: ; %bb.0: -; GISEL-GFX12-NEXT: s_lshr_b32 s0, s0, 16 -; GISEL-GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_3) -; GISEL-GFX12-NEXT: s_cvt_f32_f16 s0, s0 -; GISEL-GFX12-NEXT: v_mov_b32_e32 v0, s0 -; GISEL-GFX12-NEXT: ; return to shader part epilog +; CHECK-LABEL: fpext_hif16_to_32: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_cvt_hi_f32_f16 s0, s0 +; CHECK-NEXT: s_delay_alu instid0(SALU_CYCLE_3) +; CHECK-NEXT: v_mov_b32_e32 v0, s0 +; CHECK-NEXT: ; return to shader part epilog %hielt = extractelement <2 x half> %val, i32 1 %res = fpext half %hielt to float ret float %res _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
