https://github.com/vikramRH updated https://github.com/llvm/llvm-project/pull/217321
>From 6c107619c174bdd18c20122b28b1c9b6efc7064e Mon Sep 17 00:00:00 2001 From: vikhegde <[email protected]> Date: Wed, 19 Aug 2026 16:44:03 +0530 Subject: [PATCH 1/2] [AMDGPU][GIsel][NPM] Port "AMDGPURegBankSelect" to NPM --- llvm/lib/Target/AMDGPU/AMDGPU.h | 21 ++++++- llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def | 5 +- .../lib/Target/AMDGPU/AMDGPURegBankSelect.cpp | 62 +++++++++++++------ .../lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 4 +- .../regbankselect-mui-regbankselect.mir | 1 + 5 files changed, 68 insertions(+), 25 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.h b/llvm/lib/Target/AMDGPU/AMDGPU.h index 6684141c0cefb..aeff3dad2ca07 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPU.h +++ b/llvm/lib/Target/AMDGPU/AMDGPU.h @@ -46,7 +46,22 @@ class AMDGPUGlobalISelDivergenceLoweringPass PreservedAnalyses run(MachineFunction &MF, MachineFunctionAnalysisManager &MFAM); }; -FunctionPass *createAMDGPURegBankSelectPass(); +FunctionPass *createAMDGPURegBankSelectLegacyPass(); + +class AMDGPURegBankSelectPass + : public RequiredPassInfoMixin<AMDGPURegBankSelectPass> { +public: + PreservedAnalyses run(MachineFunction &MF, + MachineFunctionAnalysisManager &MFAM); + + MachineFunctionProperties getRequiredProperties() const { + return MachineFunctionProperties().setIsSSA().setLegalized(); + } + + MachineFunctionProperties getSetProperties() const { + return MachineFunctionProperties().setRegBankSelected(); + } +}; FunctionPass *createAMDGPURegBankLegalizePass(); // SI Passes @@ -227,8 +242,8 @@ extern char &SILowerI1CopiesLegacyID; void initializeAMDGPUGlobalISelDivergenceLoweringLegacyPass(PassRegistry &); extern char &AMDGPUGlobalISelDivergenceLoweringLegacyID; -void initializeAMDGPURegBankSelectPass(PassRegistry &); -extern char &AMDGPURegBankSelectID; +void initializeAMDGPURegBankSelectLegacyPass(PassRegistry &); +extern char &AMDGPURegBankSelectLegacyID; void initializeAMDGPURegBankLegalizePass(PassRegistry &); extern char &AMDGPURegBankLegalizeID; diff --git a/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def b/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def index b1df815c99005..bbbb71006402c 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def +++ b/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def @@ -130,6 +130,7 @@ MACHINE_FUNCTION_PASS("amdgpu-set-wave-priority", AMDGPUSetWavePriorityPass()) MACHINE_FUNCTION_PASS("amdgpu-pre-ra-optimizations", GCNPreRAOptimizationsPass()) MACHINE_FUNCTION_PASS("amdgpu-prelegalizer-combiner", AMDGPUPreLegalizerCombinerPass()) +MACHINE_FUNCTION_PASS("amdgpu-regbankselect", AMDGPURegBankSelectPass()) MACHINE_FUNCTION_PASS("amdgpu-preload-kern-arg-prolog", AMDGPUPreloadKernArgPrologPass()) MACHINE_FUNCTION_PASS("amdgpu-prepare-agpr-alloc", AMDGPUPrepareAGPRAllocPass()) MACHINE_FUNCTION_PASS("amdgpu-nsa-reassign", GCNNSAReassignPass()) @@ -164,8 +165,8 @@ MACHINE_FUNCTION_PASS("si-wqm", SIWholeQuadModePass()) #define DUMMY_MACHINE_FUNCTION_PASS(NAME, CREATE_PASS) // Global ISel passes -DUMMY_MACHINE_FUNCTION_PASS("amdgpu-postlegalizer-combiner", AMDGPUPostLegalizerCombinerPass()) -DUMMY_MACHINE_FUNCTION_PASS("amdgpu-regbankselect", AMDGPURegBankSelectPass()) +DUMMY_MACHINE_FUNCTION_PASS("amdgpu-postlegalizer-combiner", + AMDGPUPostLegalizerCombinerPass()) DUMMY_MACHINE_FUNCTION_PASS("amdgpu-regbanklegalize", AMDGPURegBankLegalizePass()) DUMMY_MACHINE_FUNCTION_PASS("amdgpu-regbank-combiner", AMDGPURegBankCombinerPass()) diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankSelect.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankSelect.cpp index f55f183b92eee..262d5019b3fde 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPURegBankSelect.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankSelect.cpp @@ -20,6 +20,8 @@ #include "GCNSubtarget.h" #include "llvm/CodeGen/GlobalISel/CSEInfo.h" #include "llvm/CodeGen/GlobalISel/CSEMIRBuilder.h" +#include "llvm/CodeGen/MachineFunctionAnalysisManager.h" +#include "llvm/CodeGen/MachinePassManager.h" #include "llvm/CodeGen/MachineUniformityAnalysis.h" #include "llvm/CodeGen/TargetPassConfig.h" #include "llvm/InitializePasses.h" @@ -31,11 +33,11 @@ using namespace AMDGPU; namespace { -class AMDGPURegBankSelect : public MachineFunctionPass { +class AMDGPURegBankSelectLegacy : public MachineFunctionPass { public: static char ID; - AMDGPURegBankSelect() : MachineFunctionPass(ID) {} + AMDGPURegBankSelectLegacy() : MachineFunctionPass(ID) {} bool runOnMachineFunction(MachineFunction &MF) override; @@ -59,20 +61,20 @@ class AMDGPURegBankSelect : public MachineFunctionPass { } // End anonymous namespace. -INITIALIZE_PASS_BEGIN(AMDGPURegBankSelect, DEBUG_TYPE, +INITIALIZE_PASS_BEGIN(AMDGPURegBankSelectLegacy, DEBUG_TYPE, "AMDGPU Register Bank Select", false, false) INITIALIZE_PASS_DEPENDENCY(TargetPassConfig) INITIALIZE_PASS_DEPENDENCY(GISelCSEAnalysisWrapperPass) INITIALIZE_PASS_DEPENDENCY(MachineUniformityAnalysisPass) -INITIALIZE_PASS_END(AMDGPURegBankSelect, DEBUG_TYPE, +INITIALIZE_PASS_END(AMDGPURegBankSelectLegacy, DEBUG_TYPE, "AMDGPU Register Bank Select", false, false) -char AMDGPURegBankSelect::ID = 0; +char AMDGPURegBankSelectLegacy::ID = 0; -char &llvm::AMDGPURegBankSelectID = AMDGPURegBankSelect::ID; +char &llvm::AMDGPURegBankSelectLegacyID = AMDGPURegBankSelectLegacy::ID; -FunctionPass *llvm::createAMDGPURegBankSelectPass() { - return new AMDGPURegBankSelect(); +FunctionPass *llvm::createAMDGPURegBankSelectLegacyPass() { + return new AMDGPURegBankSelectLegacy(); } class RegBankSelectHelper { @@ -197,15 +199,9 @@ static Register getVReg(MachineOperand &Op) { return Reg; } -bool AMDGPURegBankSelect::runOnMachineFunction(MachineFunction &MF) { - if (MF.getProperties().hasFailedISel()) - return false; - +static bool runRegBankSelect(MachineFunction &MF, GISelCSEInfo &CSEInfo, + const MachineUniformityInfo &MUI) { // Setup the instruction builder with CSE. - const TargetPassConfig &TPC = getAnalysis<TargetPassConfig>(); - GISelCSEAnalysisWrapper &Wrapper = - getAnalysis<GISelCSEAnalysisWrapperPass>().getCSEWrapper(); - GISelCSEInfo &CSEInfo = Wrapper.get(TPC.getCSEConfig()); GISelObserverWrapper Observer; Observer.addObserver(&CSEInfo); @@ -217,8 +213,6 @@ bool AMDGPURegBankSelect::runOnMachineFunction(MachineFunction &MF) { RAIIMFObserverInstaller MFObserverInstaller(MF, Observer); IntrinsicLaneMaskAnalyzer ILMA(MF); - MachineUniformityInfo &MUI = - getAnalysis<MachineUniformityAnalysisPass>().getUniformityInfo(); MachineRegisterInfo &MRI = *B.getMRI(); const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); RegBankSelectHelper RBSHelper(B, ILMA, MUI, *ST.getRegisterInfo(), @@ -289,3 +283,35 @@ bool AMDGPURegBankSelect::runOnMachineFunction(MachineFunction &MF) { return true; } + +bool AMDGPURegBankSelectLegacy::runOnMachineFunction(MachineFunction &MF) { + if (MF.getProperties().hasFailedISel()) + return false; + + const TargetPassConfig &TPC = getAnalysis<TargetPassConfig>(); + GISelCSEAnalysisWrapper &Wrapper = + getAnalysis<GISelCSEAnalysisWrapperPass>().getCSEWrapper(); + GISelCSEInfo &CSEInfo = Wrapper.get(TPC.getCSEConfig()); + const MachineUniformityInfo &MUI = + getAnalysis<MachineUniformityAnalysisPass>().getUniformityInfo(); + + return runRegBankSelect(MF, CSEInfo, MUI); +} + +PreservedAnalyses +AMDGPURegBankSelectPass::run(MachineFunction &MF, + MachineFunctionAnalysisManager &MFAM) { + MFPropsModifier _(*this, MF); + + if (MF.getProperties().hasFailedISel()) + return PreservedAnalyses::all(); + + GISelCSEInfo *CSEInfo = MFAM.getResult<GISelCSEAnalysis>(MF).get(); + const MachineUniformityInfo &MUI = + MFAM.getResult<MachineUniformityAnalysis>(MF); + + if (!runRegBankSelect(MF, *CSEInfo, MUI)) + return PreservedAnalyses::all(); + + return getMachineFunctionPassPreservedAnalyses(); +} diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp index 0f8fc6afb85c0..8fd5f4bd085dc 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp @@ -689,7 +689,7 @@ extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUTarget() { initializeGCNDPPCombineLegacyPass(*PR); initializeSILowerI1CopiesLegacyPass(*PR); initializeAMDGPUGlobalISelDivergenceLoweringLegacyPass(*PR); - initializeAMDGPURegBankSelectPass(*PR); + initializeAMDGPURegBankSelectLegacyPass(*PR); initializeAMDGPURegBankLegalizePass(*PR); initializeSILowerWWMCopiesLegacyPass(*PR); initializeAMDGPUMarkLastScratchLoadLegacyPass(*PR); @@ -1805,7 +1805,7 @@ void GCNPassConfig::addPreRegBankSelect() { } bool GCNPassConfig::addRegBankSelect() { - addPass(createAMDGPURegBankSelectPass()); + addPass(createAMDGPURegBankSelectLegacyPass()); addPass(createAMDGPURegBankLegalizePass()); return false; } diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui-regbankselect.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui-regbankselect.mir index 6cbae4620913a..82e6d67e2d6ee 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui-regbankselect.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui-regbankselect.mir @@ -1,5 +1,6 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 # RUN: llc -mtriple=amdgpu10.10 -run-pass=amdgpu-reg-bank-select %s -verify-machineinstrs -o - | FileCheck %s +# RUN: llc -mtriple=amdgpu10.10 -passes=amdgpu-reg-bank-select -verify-each %s -o - | FileCheck %s --- name: uniform_in_vgpr >From 667367962cf7257fea15fcb5d92885b960df8e78 Mon Sep 17 00:00:00 2001 From: vikhegde <[email protected]> Date: Tue, 25 Aug 2026 17:09:21 +0530 Subject: [PATCH 2/2] comments --- llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def | 2 +- .../lib/Target/AMDGPU/AMDGPURegBankSelect.cpp | 44 ++++++++++--------- 2 files changed, 24 insertions(+), 22 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def b/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def index bbbb71006402c..9164a5f92fbc7 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def +++ b/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def @@ -130,7 +130,7 @@ MACHINE_FUNCTION_PASS("amdgpu-set-wave-priority", AMDGPUSetWavePriorityPass()) MACHINE_FUNCTION_PASS("amdgpu-pre-ra-optimizations", GCNPreRAOptimizationsPass()) MACHINE_FUNCTION_PASS("amdgpu-prelegalizer-combiner", AMDGPUPreLegalizerCombinerPass()) -MACHINE_FUNCTION_PASS("amdgpu-regbankselect", AMDGPURegBankSelectPass()) +MACHINE_FUNCTION_PASS("amdgpu-reg-bank-select", AMDGPURegBankSelectPass()) MACHINE_FUNCTION_PASS("amdgpu-preload-kern-arg-prolog", AMDGPUPreloadKernArgPrologPass()) MACHINE_FUNCTION_PASS("amdgpu-prepare-agpr-alloc", AMDGPUPrepareAGPRAllocPass()) MACHINE_FUNCTION_PASS("amdgpu-nsa-reassign", GCNNSAReassignPass()) diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankSelect.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankSelect.cpp index 262d5019b3fde..f6ed59324d0a8 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPURegBankSelect.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankSelect.cpp @@ -199,8 +199,15 @@ static Register getVReg(MachineOperand &Op) { return Reg; } -static bool runRegBankSelect(MachineFunction &MF, GISelCSEInfo &CSEInfo, - const MachineUniformityInfo &MUI) { +static bool +runRegBankSelect(MachineFunction &MF, function_ref<GISelCSEInfo *()> GetCSEInfo, + function_ref<const MachineUniformityInfo *()> GetMUI) { + if (MF.getProperties().hasFailedISel()) + return false; + + GISelCSEInfo &CSEInfo = *GetCSEInfo(); + const MachineUniformityInfo &MUI = *GetMUI(); + // Setup the instruction builder with CSE. GISelObserverWrapper Observer; Observer.addObserver(&CSEInfo); @@ -285,17 +292,17 @@ static bool runRegBankSelect(MachineFunction &MF, GISelCSEInfo &CSEInfo, } bool AMDGPURegBankSelectLegacy::runOnMachineFunction(MachineFunction &MF) { - if (MF.getProperties().hasFailedISel()) - return false; - - const TargetPassConfig &TPC = getAnalysis<TargetPassConfig>(); - GISelCSEAnalysisWrapper &Wrapper = - getAnalysis<GISelCSEAnalysisWrapperPass>().getCSEWrapper(); - GISelCSEInfo &CSEInfo = Wrapper.get(TPC.getCSEConfig()); - const MachineUniformityInfo &MUI = - getAnalysis<MachineUniformityAnalysisPass>().getUniformityInfo(); - - return runRegBankSelect(MF, CSEInfo, MUI); + return runRegBankSelect( + MF, + [&]() { + GISelCSEAnalysisWrapper &Wrapper = + getAnalysis<GISelCSEAnalysisWrapperPass>().getCSEWrapper(); + return &Wrapper.get(getAnalysis<TargetPassConfig>().getCSEConfig()); + }, + [&]() { + return &getAnalysis<MachineUniformityAnalysisPass>() + .getUniformityInfo(); + }); } PreservedAnalyses @@ -303,14 +310,9 @@ AMDGPURegBankSelectPass::run(MachineFunction &MF, MachineFunctionAnalysisManager &MFAM) { MFPropsModifier _(*this, MF); - if (MF.getProperties().hasFailedISel()) - return PreservedAnalyses::all(); - - GISelCSEInfo *CSEInfo = MFAM.getResult<GISelCSEAnalysis>(MF).get(); - const MachineUniformityInfo &MUI = - MFAM.getResult<MachineUniformityAnalysis>(MF); - - if (!runRegBankSelect(MF, *CSEInfo, MUI)) + if (!runRegBankSelect( + MF, [&]() { return MFAM.getResult<GISelCSEAnalysis>(MF).get(); }, + [&]() { return &MFAM.getResult<MachineUniformityAnalysis>(MF); })) return PreservedAnalyses::all(); return getMachineFunctionPassPreservedAnalyses(); _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
