https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/220928
>From 3af5fa956f4674910c6ff2af8a58d31a8cd3968a Mon Sep 17 00:00:00 2001 From: Matt Arsenault <[email protected]> Date: Thu, 20 Aug 2026 23:26:25 +0200 Subject: [PATCH] AMDGPU: Remove llvm.amdgcn.addrspacecast.nonnull The intrinsic is fully replaced by the nonnull flag on addrspacecast, so remove it. Old bitcode/IR is autoupgraded, though this is very conservative. This intrinsic was only inserted by the backend, and hopefully nobody was directly emitting it. Co-authored-by: Claude (Claude-Opus-4.8) <[email protected]> --- llvm/include/llvm/IR/IntrinsicsAMDGPU.td | 7 -- llvm/lib/IR/AutoUpgrade.cpp | 16 +++++ llvm/lib/Target/AMDGPU/AMDGPUAttributor.cpp | 27 +------- .../lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 18 ++--- .../AMDGPU/AMDGPUTargetTransformInfo.cpp | 8 --- llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 41 ++--------- llvm/lib/Target/AMDGPU/SIISelLowering.h | 4 -- llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 5 +- .../AMDGPU/MIR/addrspacecast.mir | 6 +- .../AMDGPU/addrspacecast.ll | 4 +- .../Bitcode/amdgcn-addrspacecast-nonnull.ll | 42 ++++++++++++ llvm/test/CodeGen/AMDGPU/addrspacecast-gas.ll | 4 +- ...utor-flatscratchinit-undefined-behavior.ll | 24 +++---- ...tor-flatscratchinit-undefined-behavior2.ll | 4 +- .../AMDGPU/attributor-flatscratchinit.ll | 14 ++-- .../llvm.amdgcn.addrspacecast.nonnull.ll | 68 ------------------- 16 files changed, 98 insertions(+), 194 deletions(-) create mode 100644 llvm/test/Bitcode/amdgcn-addrspacecast-nonnull.ll delete mode 100644 llvm/test/CodeGen/AMDGPU/llvm.amdgcn.addrspacecast.nonnull.ll diff --git a/llvm/include/llvm/IR/IntrinsicsAMDGPU.td b/llvm/include/llvm/IR/IntrinsicsAMDGPU.td index 716a3f312b0f2..0e40ce71ee794 100644 --- a/llvm/include/llvm/IR/IntrinsicsAMDGPU.td +++ b/llvm/include/llvm/IR/IntrinsicsAMDGPU.td @@ -4366,13 +4366,6 @@ def int_amdgcn_global_load_monitor_b32 : AMDGPULoadMonitor<global_ptr_ty>; def int_amdgcn_global_load_monitor_b64 : AMDGPULoadMonitor<global_ptr_ty>; def int_amdgcn_global_load_monitor_b128 : AMDGPULoadMonitor<global_ptr_ty>; -/// Emit an addrspacecast without null pointer checking. -/// Should only be inserted by a pass based on analysis of an addrspacecast's src. -def int_amdgcn_addrspacecast_nonnull : DefaultAttrsIntrinsic< - [llvm_anyptr_ty], [llvm_anyptr_ty], - [IntrNoMem, IntrSpeculatable] ->; - /// Make it clear to the backend that this value is really dead. For instance, /// when used as an input to a phi node, it will make it possible for the /// backend to allocate the dead lanes for operations within the corresponding diff --git a/llvm/lib/IR/AutoUpgrade.cpp b/llvm/lib/IR/AutoUpgrade.cpp index b3153b050334d..88078df97ce91 100644 --- a/llvm/lib/IR/AutoUpgrade.cpp +++ b/llvm/lib/IR/AutoUpgrade.cpp @@ -1677,6 +1677,13 @@ static bool upgradeIntrinsicFunction1(Function *F, Function *&NewFn, break; // No other 'amdgcn.atomic.*' } + if (Name.starts_with("addrspacecast.nonnull")) { + // Replaced with an addrspacecast instruction carrying the nonnull flag, + // so there's no new declaration. + NewFn = nullptr; + return true; + } + switch (F->getIntrinsicID()) { default: break; @@ -5314,6 +5321,15 @@ static Value *upgradeAMDGCNIntrinsicCall(StringRef Name, CallBase *CI, return NewCall; } + if (Name.starts_with("addrspacecast.nonnull")) { + if (CI->getNumOperands() < 2) // Malformed bitcode. + return nullptr; + Value *ASC = Builder.CreateAddrSpaceCast( + CI->getArgOperand(0), CI->getType(), "", /*IsNonNull=*/true); + ASC->takeName(CI); + return ASC; + } + AtomicRMWInst::BinOp RMWOp = StringSwitch<AtomicRMWInst::BinOp>(Name) .StartsWith("ds.fadd", AtomicRMWInst::FAdd) diff --git a/llvm/lib/Target/AMDGPU/AMDGPUAttributor.cpp b/llvm/lib/Target/AMDGPU/AMDGPUAttributor.cpp index 630ffad96e451..875657a556329 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUAttributor.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUAttributor.cpp @@ -780,32 +780,7 @@ struct AAAMDAttributesFunction : public AAAMDAttributes { } } - // Finally check callees. - - // This is called on each callee; false means callee shouldn't have - // no-flat-scratch-init. - auto CheckForNoFlatScratchInit = [&](Instruction &I) { - const auto &CB = cast<CallBase>(I); - const Function *Callee = CB.getCalledFunction(); - - // Callee == 0 for inline asm or indirect call with known callees. - // In the latter case, updateImpl() already checked the callees and we - // know their FLAT_SCRATCH_INIT bit is set. - // If function has indirect call with unknown callees, the bit is - // already removed in updateImpl() and execution won't reach here. - if (!Callee) - return true; - - return Callee->getIntrinsicID() != - Intrinsic::amdgcn_addrspacecast_nonnull; - }; - - UsedAssumedInformation = false; - // If any callee is false (i.e. need FlatScratchInit), - // checkForAllCallLikeInstructions returns false, in which case this - // function returns true. - return !A.checkForAllCallLikeInstructions(CheckForNoFlatScratchInit, *this, - UsedAssumedInformation); + return false; } }; diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp index c4a7c77f6968f..49d055461ccb1 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp @@ -2533,17 +2533,12 @@ bool AMDGPULegalizerInfo::legalizeAddrSpaceCast( MachineIRBuilder &B) const { MachineFunction &MF = B.getMF(); - // MI can either be a G_ADDRSPACE_CAST or a - // G_INTRINSIC @llvm.amdgcn.addrspacecast.nonnull - assert(MI.getOpcode() == TargetOpcode::G_ADDRSPACE_CAST || - (isa<GIntrinsic>(MI) && cast<GIntrinsic>(MI).getIntrinsicID() == - Intrinsic::amdgcn_addrspacecast_nonnull)); + assert(MI.getOpcode() == TargetOpcode::G_ADDRSPACE_CAST); const LLT I32 = LLT::integer(32); const LLT I64 = LLT::integer(64); Register Dst = MI.getOperand(0).getReg(); - Register Src = isa<GIntrinsic>(MI) ? MI.getOperand(2).getReg() - : MI.getOperand(1).getReg(); + Register Src = MI.getOperand(1).getReg(); LLT DstTy = MRI.getType(Dst); LLT SrcTy = MRI.getType(Src); unsigned DestAS = DstTy.getAddressSpace(); @@ -2556,10 +2551,9 @@ bool AMDGPULegalizerInfo::legalizeAddrSpaceCast( const AMDGPUTargetMachine &TM = static_cast<const AMDGPUTargetMachine &>(MF.getTarget()); - // The source is known non-null for llvm.amdgcn.addrspacecast.nonnull or a - // G_ADDRSPACE_CAST carrying the nonnull flag; otherwise we need to guess. - const bool IsNonNull = - isa<GIntrinsic>(MI) || MI.getFlag(MachineInstr::MIFlag::NonNull); + // The source is known non-null for a G_ADDRSPACE_CAST carrying the nonnull + // flag; otherwise we need to guess. + const bool IsNonNull = MI.getFlag(MachineInstr::MIFlag::NonNull); if (TM.isNoopAddrSpaceCast(SrcAS, DestAS)) { MI.setDesc(B.getTII().get(TargetOpcode::G_BITCAST)); @@ -8330,8 +8324,6 @@ bool AMDGPULegalizerInfo::legalizeIntrinsic(LegalizerHelper &Helper, MI.eraseFromParent(); return true; } - case Intrinsic::amdgcn_addrspacecast_nonnull: - return legalizeAddrSpaceCast(MI, MRI, B); case Intrinsic::amdgcn_make_buffer_rsrc: return legalizePointerAsRsrcIntrin(MI, MRI, B); case Intrinsic::amdgcn_kernarg_segment_ptr: diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp index f6ff44e585589..a7556278b7e0d 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp @@ -1198,14 +1198,6 @@ bool GCNTTIImpl::isSourceOfDivergence(const Value *V) const { switch (IID) { case Intrinsic::read_register: return isReadRegisterSourceOfDivergence(Intrinsic); - case Intrinsic::amdgcn_addrspacecast_nonnull: { - unsigned SrcAS = - Intrinsic->getOperand(0)->getType()->getPointerAddressSpace(); - unsigned DstAS = Intrinsic->getType()->getPointerAddressSpace(); - return SrcAS == AMDGPUAS::PRIVATE_ADDRESS && - DstAS == AMDGPUAS::FLAT_ADDRESS && - ST->hasGloballyAddressableScratch(); - } case Intrinsic::amdgcn_workitem_id_y: case Intrinsic::amdgcn_workitem_id_z: { const Function *F = Intrinsic->getFunction(); diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index 3bad6d330c0ad..9f718a517dfbe 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -1897,23 +1897,6 @@ void SITargetLowering::getTgtMemIntrinsic(SmallVectorImpl<IntrinsicInfo> &Infos, } } -void SITargetLowering::CollectTargetIntrinsicOperands( - const CallInst &I, SmallVectorImpl<SDValue> &Ops, SelectionDAG &DAG) const { - switch (cast<IntrinsicInst>(I).getIntrinsicID()) { - case Intrinsic::amdgcn_addrspacecast_nonnull: { - // The DAG's ValueType loses the addrspaces. - // Add them as 2 extra Constant operands "from" and "to". - unsigned SrcAS = I.getOperand(0)->getType()->getPointerAddressSpace(); - unsigned DstAS = I.getType()->getPointerAddressSpace(); - Ops.push_back(DAG.getTargetConstant(SrcAS, SDLoc(), MVT::i32)); - Ops.push_back(DAG.getTargetConstant(DstAS, SDLoc(), MVT::i32)); - break; - } - default: - break; - } -} - bool SITargetLowering::getAddrModeArguments(const IntrinsicInst *II, SmallVectorImpl<Value *> &Ops, Type *&AccessTy) const { @@ -9412,23 +9395,11 @@ SDValue SITargetLowering::lowerADDRSPACECAST(SDValue Op, const AMDGPUTargetMachine &TM = static_cast<const AMDGPUTargetMachine &>(getTargetMachine()); - unsigned DestAS, SrcAS; - SDValue Src; - bool IsNonNull = false; - if (const auto *ASC = dyn_cast<AddrSpaceCastSDNode>(Op)) { - SrcAS = ASC->getSrcAddressSpace(); - Src = ASC->getOperand(0); - DestAS = ASC->getDestAddressSpace(); - IsNonNull = ASC->getFlags().hasNonNull(); - } else { - assert(Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN && - Op.getConstantOperandVal(0) == - Intrinsic::amdgcn_addrspacecast_nonnull); - Src = Op->getOperand(1); - SrcAS = Op->getConstantOperandVal(2); - DestAS = Op->getConstantOperandVal(3); - IsNonNull = true; - } + const auto *ASC = cast<AddrSpaceCastSDNode>(Op); + unsigned SrcAS = ASC->getSrcAddressSpace(); + SDValue Src = ASC->getOperand(0); + unsigned DestAS = ASC->getDestAddressSpace(); + bool IsNonNull = ASC->getFlags().hasNonNull(); SDValue FlatNullPtr = DAG.getConstant(0, SL, MVT::i64); @@ -11643,8 +11614,6 @@ SDValue SITargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, } return SDValue(); } - case Intrinsic::amdgcn_addrspacecast_nonnull: - return lowerADDRSPACECAST(Op, DAG); case Intrinsic::amdgcn_readlane: case Intrinsic::amdgcn_readfirstlane: case Intrinsic::amdgcn_writelane: diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.h b/llvm/lib/Target/AMDGPU/SIISelLowering.h index 215107fcec712..8c20207ae58dc 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.h +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.h @@ -355,10 +355,6 @@ class SITargetLowering final : public AMDGPUTargetLowering { MachineFunction &MF, unsigned IntrinsicID) const override; - void CollectTargetIntrinsicOperands(const CallInst &I, - SmallVectorImpl<SDValue> &Ops, - SelectionDAG &DAG) const override; - bool getAddrModeArguments(const IntrinsicInst *I, SmallVectorImpl<Value *> &Ops, Type *&AccessTy) const override; diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp index 173c88f6c17fd..4283b4f5bfce6 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp @@ -11148,8 +11148,7 @@ SIInstrInfo::getGenericValueUniformity(const MachineInstr &MI) const { auto HandleAddrSpaceCast = [this, &MRI](const MachineInstr &MI) { Register Dst = MI.getOperand(0).getReg(); - Register Src = isa<GIntrinsic>(MI) ? MI.getOperand(2).getReg() - : MI.getOperand(1).getReg(); + Register Src = MI.getOperand(1).getReg(); LLT DstTy = MRI.getType(Dst); LLT SrcTy = MRI.getType(Src); unsigned DstAS = DstTy.getAddressSpace(); @@ -11175,8 +11174,6 @@ SIInstrInfo::getGenericValueUniformity(const MachineInstr &MI) const { return ValueUniformity::AlwaysUniform; switch (IID) { - case Intrinsic::amdgcn_addrspacecast_nonnull: - return HandleAddrSpaceCast(MI); case Intrinsic::amdgcn_if: case Intrinsic::amdgcn_else: // FIXME: Uniform if second result diff --git a/llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/addrspacecast.mir b/llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/addrspacecast.mir index 58107b329fb38..f1bafc6ef8bac 100644 --- a/llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/addrspacecast.mir +++ b/llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/addrspacecast.mir @@ -4,14 +4,14 @@ # UNI: ALL VALUES UNIFORM # DIV: DIVERGENT: %3: %3:_(p0) = G_ADDRSPACE_CAST %2:_(p5) -# DIV: DIVERGENT: %4: %4:_(p0) = G_INTRINSIC intrinsic(@llvm.amdgcn.addrspacecast.nonnull), %2:_(p5) +# DIV: DIVERGENT: %4: %4:_(p0) = nonnull G_ADDRSPACE_CAST %2:_(p5) --- | define void @foo() { %alloca = alloca i32, align 4, addrspace(5) %cast = addrspacecast ptr addrspace(5) %alloca to ptr store i32 1, ptr %cast, align 4 - %cast.1 = call ptr @llvm.amdgcn.addrspacecast.nonnull.p0.p5(ptr addrspace(5) %alloca) + %cast.1 = addrspacecast nonnull ptr addrspace(5) %alloca to ptr store i32 2, ptr %cast.1, align 4 ret void } @@ -29,7 +29,7 @@ body: | %8:_(p5) = G_FRAME_INDEX %stack.0.alloca %9:_(p0) = G_ADDRSPACE_CAST %8(p5) G_STORE %10(s32), %9(p0) :: (store (s32) into %ir.cast) - %11:_(p0) = G_INTRINSIC intrinsic(@llvm.amdgcn.addrspacecast.nonnull), %8(p5) + %11:_(p0) = nonnull G_ADDRSPACE_CAST %8(p5) G_STORE %12(s32), %11(p0) :: (store (s32) into %ir.cast.1) SI_RETURN ... diff --git a/llvm/test/Analysis/UniformityAnalysis/AMDGPU/addrspacecast.ll b/llvm/test/Analysis/UniformityAnalysis/AMDGPU/addrspacecast.ll index d652b02bd7a51..1391857bd71c7 100644 --- a/llvm/test/Analysis/UniformityAnalysis/AMDGPU/addrspacecast.ll +++ b/llvm/test/Analysis/UniformityAnalysis/AMDGPU/addrspacecast.ll @@ -3,12 +3,12 @@ ; UNI: ALL VALUES UNIFORM ; DIV: DIVERGENT: %cast = addrspacecast ptr addrspace(5) %alloca to ptr -; DIV: DIVERGENT: %cast.1 = call ptr @llvm.amdgcn.addrspacecast.nonnull.p0.p5(ptr addrspace(5) %alloca) +; DIV: DIVERGENT: %cast.1 = addrspacecast nonnull ptr addrspace(5) %alloca to ptr define void @foo() { %alloca = alloca i32, align 4, addrspace(5) %cast = addrspacecast ptr addrspace(5) %alloca to ptr store i32 1, ptr %cast - %cast.1 = call ptr @llvm.amdgcn.addrspacecast.nonnull.p0.p5(ptr addrspace(5) %alloca) + %cast.1 = addrspacecast nonnull ptr addrspace(5) %alloca to ptr store i32 2, ptr %cast.1 ret void } diff --git a/llvm/test/Bitcode/amdgcn-addrspacecast-nonnull.ll b/llvm/test/Bitcode/amdgcn-addrspacecast-nonnull.ll new file mode 100644 index 0000000000000..d370432b72937 --- /dev/null +++ b/llvm/test/Bitcode/amdgcn-addrspacecast-nonnull.ll @@ -0,0 +1,42 @@ +; RUN: llvm-as < %s | llvm-dis | FileCheck %s + +; The llvm.amdgcn.addrspacecast.nonnull intrinsic is replaced by an +; addrspacecast instruction carrying the nonnull flag. + +define ptr @local_to_flat(ptr addrspace(3) %ptr) { + ; CHECK: %res = addrspacecast nonnull ptr addrspace(3) %ptr to ptr + %res = call ptr @llvm.amdgcn.addrspacecast.nonnull.p0.p3(ptr addrspace(3) %ptr) + ret ptr %res +} + +define ptr @private_to_flat(ptr addrspace(5) %ptr) { + ; CHECK: %res = addrspacecast nonnull ptr addrspace(5) %ptr to ptr + %res = call ptr @llvm.amdgcn.addrspacecast.nonnull.p0.p5(ptr addrspace(5) %ptr) + ret ptr %res +} + +define ptr addrspace(3) @flat_to_local(ptr %ptr) { + ; CHECK: %res = addrspacecast nonnull ptr %ptr to ptr addrspace(3) + %res = call ptr addrspace(3) @llvm.amdgcn.addrspacecast.nonnull.p3.p0(ptr %ptr) + ret ptr addrspace(3) %res +} + +define ptr addrspace(5) @flat_to_private(ptr %ptr) { + ; CHECK: %res = addrspacecast nonnull ptr %ptr to ptr addrspace(5) + %res = call ptr addrspace(5) @llvm.amdgcn.addrspacecast.nonnull.p5.p0(ptr %ptr) + ret ptr addrspace(5) %res +} + +; A malformed call with too few arguments is dropped instead of upgraded. +define void @malformed_no_args() { + ; CHECK-LABEL: @malformed_no_args( + ; CHECK-NEXT: ret void + call ptr @llvm.amdgcn.addrspacecast.nonnull.p0.p3.malformed() + ret void +} + +declare ptr @llvm.amdgcn.addrspacecast.nonnull.p0.p3(ptr addrspace(3)) +declare ptr @llvm.amdgcn.addrspacecast.nonnull.p0.p5(ptr addrspace(5)) +declare ptr addrspace(3) @llvm.amdgcn.addrspacecast.nonnull.p3.p0(ptr) +declare ptr addrspace(5) @llvm.amdgcn.addrspacecast.nonnull.p5.p0(ptr) +declare ptr @llvm.amdgcn.addrspacecast.nonnull.p0.p3.malformed() diff --git a/llvm/test/CodeGen/AMDGPU/addrspacecast-gas.ll b/llvm/test/CodeGen/AMDGPU/addrspacecast-gas.ll index e1a9d849c87cd..208c8530781d5 100644 --- a/llvm/test/CodeGen/AMDGPU/addrspacecast-gas.ll +++ b/llvm/test/CodeGen/AMDGPU/addrspacecast-gas.ll @@ -90,7 +90,7 @@ define amdgpu_kernel void @use_private_to_flat_addrspacecast_nonnull(ptr addrspa ; GFX1250-GISEL-NEXT: flat_store_b32 v[0:1], v2 scope:SCOPE_SYS ; GFX1250-GISEL-NEXT: s_wait_storecnt 0x0 ; GFX1250-GISEL-NEXT: s_endpgm - %stof = call ptr @llvm.amdgcn.addrspacecast.nonnull.p0.p5(ptr addrspace(5) %ptr) + %stof = addrspacecast nonnull ptr addrspace(5) %ptr to ptr store volatile i32 0, ptr %stof ret void } @@ -144,7 +144,7 @@ define amdgpu_kernel void @use_flat_to_private_addrspacecast_nonnull(ptr %ptr) { ; GFX1250-GISEL-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SYS ; GFX1250-GISEL-NEXT: s_wait_storecnt 0x0 ; GFX1250-GISEL-NEXT: s_endpgm - %ftos = call ptr addrspace(5) @llvm.amdgcn.addrspacecast.nonnull.p5.p0(ptr %ptr) + %ftos = addrspacecast nonnull ptr %ptr to ptr addrspace(5) store volatile i32 0, ptr addrspace(5) %ftos ret void } diff --git a/llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit-undefined-behavior.ll b/llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit-undefined-behavior.ll index d3e0f581dc03f..42867927707a0 100644 --- a/llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit-undefined-behavior.ll +++ b/llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit-undefined-behavior.ll @@ -97,17 +97,17 @@ define amdgpu_kernel void @private_constant_expression_use(ptr addrspace(1) noca define amdgpu_kernel void @calls_intrin_ascast_cc_kernel(ptr addrspace(3) %ptr) #0 { ; GFX9-LABEL: define amdgpu_kernel void @calls_intrin_ascast_cc_kernel( ; GFX9-SAME: ptr addrspace(3) [[PTR:%.*]]) #[[ATTR0]] { -; GFX9-NEXT: [[TMP1:%.*]] = call ptr @llvm.amdgcn.addrspacecast.nonnull.p0.p3(ptr addrspace(3) [[PTR]]) -; GFX9-NEXT: store volatile i32 7, ptr [[TMP1]], align 4 +; GFX9-NEXT: [[TMP1:%.*]] = addrspacecast nonnull ptr addrspace(3) [[PTR]] to ptr +; GFX9-NEXT: store volatile i32 7, ptr [[TMP1]], align 4, !noalias.addrspace [[META1:![0-9]+]] ; GFX9-NEXT: ret void ; ; GFX10-LABEL: define amdgpu_kernel void @calls_intrin_ascast_cc_kernel( ; GFX10-SAME: ptr addrspace(3) [[PTR:%.*]]) #[[ATTR0]] { -; GFX10-NEXT: [[TMP1:%.*]] = call ptr @llvm.amdgcn.addrspacecast.nonnull.p0.p3(ptr addrspace(3) [[PTR]]) -; GFX10-NEXT: store volatile i32 7, ptr [[TMP1]], align 4 +; GFX10-NEXT: [[TMP1:%.*]] = addrspacecast nonnull ptr addrspace(3) [[PTR]] to ptr +; GFX10-NEXT: store volatile i32 7, ptr [[TMP1]], align 4, !noalias.addrspace [[META1:![0-9]+]] ; GFX10-NEXT: ret void ; - %1 = call ptr @llvm.amdgcn.addrspacecast.nonnull.p0.p3(ptr addrspace(3) %ptr) + %1 = addrspacecast nonnull ptr addrspace(3) %ptr to ptr store volatile i32 7, ptr %1, align 4 ret void } @@ -115,17 +115,17 @@ define amdgpu_kernel void @calls_intrin_ascast_cc_kernel(ptr addrspace(3) %ptr) define void @calls_intrin_ascast(ptr addrspace(3) %ptr) #0 { ; GFX9-LABEL: define void @calls_intrin_ascast( ; GFX9-SAME: ptr addrspace(3) [[PTR:%.*]]) #[[ATTR0]] { -; GFX9-NEXT: [[TMP1:%.*]] = call ptr @llvm.amdgcn.addrspacecast.nonnull.p0.p3(ptr addrspace(3) [[PTR]]) -; GFX9-NEXT: store volatile i32 7, ptr [[TMP1]], align 4 +; GFX9-NEXT: [[TMP1:%.*]] = addrspacecast nonnull ptr addrspace(3) [[PTR]] to ptr +; GFX9-NEXT: store volatile i32 7, ptr [[TMP1]], align 4, !noalias.addrspace [[META1]] ; GFX9-NEXT: ret void ; ; GFX10-LABEL: define void @calls_intrin_ascast( ; GFX10-SAME: ptr addrspace(3) [[PTR:%.*]]) #[[ATTR0]] { -; GFX10-NEXT: [[TMP1:%.*]] = call ptr @llvm.amdgcn.addrspacecast.nonnull.p0.p3(ptr addrspace(3) [[PTR]]) -; GFX10-NEXT: store volatile i32 7, ptr [[TMP1]], align 4 +; GFX10-NEXT: [[TMP1:%.*]] = addrspacecast nonnull ptr addrspace(3) [[PTR]] to ptr +; GFX10-NEXT: store volatile i32 7, ptr [[TMP1]], align 4, !noalias.addrspace [[META1]] ; GFX10-NEXT: ret void ; - %1 = call ptr @llvm.amdgcn.addrspacecast.nonnull.p0.p3(ptr addrspace(3) %ptr) + %1 = addrspacecast nonnull ptr addrspace(3) %ptr to ptr store volatile i32 7, ptr %1, align 4 ret void } @@ -148,12 +148,12 @@ define amdgpu_kernel void @call_calls_intrin_ascast_cc_kernel(ptr addrspace(3) % attributes #0 = { "amdgpu-no-flat-scratch-init" } ;. ; GFX9: attributes #[[ATTR0]] = { "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "amdgpu-no-wwm" } -; GFX9: attributes #[[ATTR1:[0-9]+]] = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } ;. ; GFX10: attributes #[[ATTR0]] = { "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "amdgpu-no-wwm" } -; GFX10: attributes #[[ATTR1:[0-9]+]] = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } ;. ; GFX9: [[META0]] = !{i32 1, i32 5, i32 6, i32 10} +; GFX9: [[META1]] = !{i32 1, i32 3, i32 4, i32 10} ;. ; GFX10: [[META0]] = !{i32 1, i32 5, i32 6, i32 10} +; GFX10: [[META1]] = !{i32 1, i32 3, i32 4, i32 10} ;. diff --git a/llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit-undefined-behavior2.ll b/llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit-undefined-behavior2.ll index b155b09a81c78..d65bbbd6e3f8c 100644 --- a/llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit-undefined-behavior2.ll +++ b/llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit-undefined-behavior2.ll @@ -657,7 +657,7 @@ define amdgpu_kernel void @calls_intrin_ascast_cc_kernel(ptr addrspace(3) %ptr) ; GFX10-NEXT: flat_store_dword v[0:1], v2 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_endpgm - %1 = call ptr @llvm.amdgcn.addrspacecast.nonnull.p0.p3(ptr addrspace(3) %ptr) + %1 = addrspacecast nonnull ptr addrspace(3) %ptr to ptr store volatile i32 7, ptr %1, align 4 ret void } @@ -727,7 +727,7 @@ define void @calls_intrin_ascast(ptr addrspace(3) %ptr) #0 { ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_setpc_b64 s[30:31] - %1 = call ptr @llvm.amdgcn.addrspacecast.nonnull.p0.p3(ptr addrspace(3) %ptr) + %1 = addrspacecast nonnull ptr addrspace(3) %ptr to ptr store volatile i32 7, ptr %1, align 4 ret void } diff --git a/llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit.ll b/llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit.ll index 11fd660813a13..0f05caffd8d9a 100644 --- a/llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit.ll +++ b/llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit.ll @@ -825,18 +825,18 @@ define amdgpu_kernel void @call_use_intrinsic_workitem_id_x_cc_kernel() { define amdgpu_kernel void @calls_intrin_ascast_cc_kernel(ptr addrspace(3) %ptr) { ; GFX9-LABEL: define amdgpu_kernel void @calls_intrin_ascast_cc_kernel( -; GFX9-SAME: ptr addrspace(3) [[PTR:%.*]]) #[[ATTR1]] { -; GFX9-NEXT: [[TMP1:%.*]] = call ptr @llvm.amdgcn.addrspacecast.nonnull.p0.p3(ptr addrspace(3) [[PTR]]) -; GFX9-NEXT: store volatile i32 7, ptr [[TMP1]], align 4 +; GFX9-SAME: ptr addrspace(3) [[PTR:%.*]]) #[[ATTR0]] { +; GFX9-NEXT: [[TMP1:%.*]] = addrspacecast nonnull ptr addrspace(3) [[PTR]] to ptr +; GFX9-NEXT: store volatile i32 7, ptr [[TMP1]], align 4, !noalias.addrspace [[META2]] ; GFX9-NEXT: ret void ; ; GFX10-LABEL: define amdgpu_kernel void @calls_intrin_ascast_cc_kernel( -; GFX10-SAME: ptr addrspace(3) [[PTR:%.*]]) #[[ATTR1]] { -; GFX10-NEXT: [[TMP1:%.*]] = call ptr @llvm.amdgcn.addrspacecast.nonnull.p0.p3(ptr addrspace(3) [[PTR]]) -; GFX10-NEXT: store volatile i32 7, ptr [[TMP1]], align 4 +; GFX10-SAME: ptr addrspace(3) [[PTR:%.*]]) #[[ATTR0]] { +; GFX10-NEXT: [[TMP1:%.*]] = addrspacecast nonnull ptr addrspace(3) [[PTR]] to ptr +; GFX10-NEXT: store volatile i32 7, ptr [[TMP1]], align 4, !noalias.addrspace [[META2]] ; GFX10-NEXT: ret void ; - %1 = call ptr @llvm.amdgcn.addrspacecast.nonnull.p0.p3(ptr addrspace(3) %ptr) + %1 = addrspacecast nonnull ptr addrspace(3) %ptr to ptr store volatile i32 7, ptr %1, align 4 ret void } diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.addrspacecast.nonnull.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.addrspacecast.nonnull.ll deleted file mode 100644 index d4b026610a184..0000000000000 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.addrspacecast.nonnull.ll +++ /dev/null @@ -1,68 +0,0 @@ -; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 -; RUN: llc -mtriple=amdgpu9.00-amd-amdhsa < %s | FileCheck %s --check-prefixes=ASM,DAGISEL-ASM -; RUN: llc -mtriple=amdgpu9.00-amd-amdhsa -global-isel < %s | FileCheck %s --check-prefixes=ASM,GISEL-ASM - -define void @local_to_flat(ptr addrspace(3) %ptr) { -; ASM-LABEL: local_to_flat: -; ASM: ; %bb.0: -; ASM-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; ASM-NEXT: s_mov_b64 s[4:5], src_shared_base -; ASM-NEXT: v_mov_b32_e32 v1, s5 -; ASM-NEXT: v_mov_b32_e32 v2, 7 -; ASM-NEXT: flat_store_dword v[0:1], v2 -; ASM-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; ASM-NEXT: s_setpc_b64 s[30:31] - %1 = call ptr @llvm.amdgcn.addrspacecast.nonnull.p0.p3(ptr addrspace(3) %ptr) - store volatile i32 7, ptr %1, align 4 - ret void -} - -define void @private_to_flat(ptr addrspace(5) %ptr) { -; ASM-LABEL: private_to_flat: -; ASM: ; %bb.0: -; ASM-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; ASM-NEXT: s_mov_b64 s[4:5], src_private_base -; ASM-NEXT: v_mov_b32_e32 v1, s5 -; ASM-NEXT: v_mov_b32_e32 v2, 7 -; ASM-NEXT: flat_store_dword v[0:1], v2 -; ASM-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; ASM-NEXT: s_setpc_b64 s[30:31] - %1 = call ptr @llvm.amdgcn.addrspacecast.nonnull.p0.p5(ptr addrspace(5) %ptr) - store volatile i32 7, ptr %1, align 4 - ret void -} - -define void @flat_to_local(ptr %ptr) { -; ASM-LABEL: flat_to_local: -; ASM: ; %bb.0: -; ASM-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; ASM-NEXT: v_mov_b32_e32 v1, 7 -; ASM-NEXT: ds_write_b32 v0, v1 -; ASM-NEXT: s_waitcnt lgkmcnt(0) -; ASM-NEXT: s_setpc_b64 s[30:31] - %1 = call ptr addrspace(3) @llvm.amdgcn.addrspacecast.nonnull.p3.p0(ptr %ptr) - store volatile i32 7, ptr addrspace(3) %1, align 4 - ret void -} - -define void @flat_to_private(ptr %ptr) { -; ASM-LABEL: flat_to_private: -; ASM: ; %bb.0: -; ASM-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; ASM-NEXT: v_mov_b32_e32 v1, 7 -; ASM-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen -; ASM-NEXT: s_waitcnt vmcnt(0) -; ASM-NEXT: s_setpc_b64 s[30:31] - %1 = call ptr addrspace(5) @llvm.amdgcn.addrspacecast.nonnull.p5.p0(ptr %ptr) - store volatile i32 7, ptr addrspace(5) %1, align 4 - ret void -} - -declare ptr @llvm.amdgcn.addrspacecast.nonnull.p0.p3(ptr addrspace(3)) -declare ptr @llvm.amdgcn.addrspacecast.nonnull.p0.p5(ptr addrspace(5)) -declare ptr addrspace(3) @llvm.amdgcn.addrspacecast.nonnull.p3.p0(ptr) -declare ptr addrspace(5) @llvm.amdgcn.addrspacecast.nonnull.p5.p0(ptr) - -;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: -; DAGISEL-ASM: {{.*}} -; GISEL-ASM: {{.*}} _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
