https://github.com/llvmbot created https://github.com/llvm/llvm-project/pull/221969
Backport 7fd0dd89cf63bd363b7884232202fa958ccc974a Requested by: @mstorsjo >From 0c792c64f2e604d83c4be0bf8be3b11e1193dc49 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Bernhard=20=C3=9Cbelacker?= <[email protected]> Date: Thu, 27 Aug 2026 13:50:55 +0200 Subject: [PATCH] [win/asan] GetInstructionSize: Add some more instructions. (#219038) These got reported in #96270. - Allow "0F B6 44 24 XX : movzx eax, byte ptr [esp + XX]" for x86 and x86_64. - Add "0F B6 4C 24 XX : movzx ecx, byte ptr [esp + XX]" - Add "4F 8D 0C XX : lea r9, [...]" - Add "66 83 3A XX : cmp word ptr [rdx], XX" - Add "85 D2 : test edx, edx" - Add "8D 44 24 XX : lea eax, [esp + XX]" - Add "F3 0F 1E FA : endbr64" - Add "F3 0F 1E FB : endbr32" (cherry picked from commit 7fd0dd89cf63bd363b7884232202fa958ccc974a) --- compiler-rt/lib/interception/interception_win.cpp | 14 +++++++++----- .../interception/tests/interception_win_test.cpp | 9 ++++++++- 2 files changed, 17 insertions(+), 6 deletions(-) diff --git a/compiler-rt/lib/interception/interception_win.cpp b/compiler-rt/lib/interception/interception_win.cpp index 86a622ed48b50..b43776418f621 100644 --- a/compiler-rt/lib/interception/interception_win.cpp +++ b/compiler-rt/lib/interception/interception_win.cpp @@ -676,6 +676,7 @@ static size_t GetInstructionSize(uptr address, size_t* rel_offset = nullptr) { case 0xC084: // 84 C0 : test al,al case 0xC984: // 84 C9 : test cl,cl case 0xD284: // 84 D2 : test dl,dl + case 0xD285: // 85 D2 : test edx, edx return 2; case 0x3980: // 80 39 XX : cmp BYTE PTR [rcx], XX @@ -699,7 +700,9 @@ static size_t GetInstructionSize(uptr address, size_t* rel_offset = nullptr) { } switch (0x00FFFFFF & *(u32 *)address) { + case 0x24448D: // 8D 44 24 XX : lea eax, [esp + XX] case 0x244C8D: // 8D 4C 24 XX : lea ecx, [esp + XX] + case 0x3A8366: // 66 83 3A XX : cmp word ptr [rdx], XX case 0x2474FF: // FF 74 24 XX : push qword ptr [rsp + XX] return 4; case 0x24A48D: // 8D A4 24 XX XX XX XX : lea esp, [esp + XX XX XX XX] @@ -708,7 +711,12 @@ static size_t GetInstructionSize(uptr address, size_t* rel_offset = nullptr) { switch (*(u32*)(address)) { case 0xc0ef0f66: // 66 0f ef c0 : pxor xmm0, xmm0 + case 0xFA1E0FF3: // F3 0F 1E FA : endbr64 + case 0xFB1E0FF3: // F3 0F 1E FB : endbr32 return 4; + case 0x2444B60F: // 0F B6 44 24 XX : movzx eax, byte ptr [esp + XX] + case 0x244CB60F: // 0F B6 4C 24 XX : movzx ecx, byte ptr [esp + XX] + return 5; } switch (0x000000FF & *(u32 *)address) { @@ -885,6 +893,7 @@ static size_t GetInstructionSize(uptr address, size_t* rel_offset = nullptr) { case 0x488d49: // 49 8d 48 XX : lea rcx, [...] case 0x048d4c: // 4c 8d 04 XX : lea r8, [...] case 0x148d4e: // 4e 8d 14 XX : lea r10, [...] + case 0x0C8D4F: // 4F 8D 0C XX : lea r9, [...] case 0x398366: // 66 83 39 XX : cmp WORD PTR [rcx], XX return 4; @@ -1004,11 +1013,6 @@ static size_t GetInstructionSize(uptr address, size_t* rel_offset = nullptr) { case 0x247C8B: // 8B 7C 24 XX : mov edi, dword ptr [esp + XX] return 4; } - - switch (*(u32*)address) { - case 0x2444B60F: // 0F B6 44 24 XX : movzx eax, byte ptr [esp + XX] - return 5; - } #endif // Unknown instruction! This might happen when we add a new interceptor, use diff --git a/compiler-rt/lib/interception/tests/interception_win_test.cpp b/compiler-rt/lib/interception/tests/interception_win_test.cpp index 054d5405971dd..d3a52e9007b7a 100644 --- a/compiler-rt/lib/interception/tests/interception_win_test.cpp +++ b/compiler-rt/lib/interception/tests/interception_win_test.cpp @@ -852,6 +852,7 @@ const struct InstructionSizeData { { 2, {0x84, 0xC9}, 0, "84 C9 : test cl,cl"}, { 2, {0x84, 0xD2}, 0, "84 D2 : test dl,dl"}, { 2, {0x84, 0xDB}, 0, "84 DB : test bl,bl"}, + { 2, {0x85, 0xD2}, 0, "85 D2 : test edx, edx"}, { 2, {0x89, 0xc8}, 0, "89 C8 : mov eax, ecx"}, { 2, {0x89, 0xD1}, 0, "89 D1 : mov ecx, edx"}, { 2, {0x89, 0xE5}, 0, "89 E5 : mov ebp, esp"}, @@ -869,8 +870,14 @@ const struct InstructionSizeData { { 3, {0x8D, 0x45, 0x72}, 0, "8D 45 XX : lea eax, [ebp + XX]"}, { 3, {0xc2, 0x71, 0x72}, 0, "C2 XX XX : ret XX (needed for registering weak functions)"}, { 4, {0x66, 0x0f, 0xef, 0xc0}, 0, "66 0f ef c0 : pxor xmm0, xmm0"}, + { 4, {0x66, 0x83, 0x3A, 0x73}, 0, "66 83 3A XX : cmp word ptr [rdx], XX"}, + { 4, {0x8D, 0x44, 0x24, 0x73}, 0, "8D 44 24 XX : lea eax, [esp + XX]"}, { 4, {0x8D, 0x4C, 0x24, 0x73}, 0, "8D 4C 24 XX : lea ecx, [esp + XX]"}, + { 4, {0xF3, 0x0F, 0x1E, 0xFA}, 0, "F3 0F 1E FA : endbr64"}, + { 4, {0xF3, 0x0F, 0x1E, 0xFB}, 0, "F3 0F 1E FB : endbr32"}, { 4, {0xFF, 0x74, 0x24, 0x73}, 0, "FF 74 24 XX : push qword ptr [rsp + XX]"}, + { 5, {0x0F, 0xB6, 0x44, 0x24, 0x74}, 0, "0F B6 44 24 XX : movzx eax, byte ptr [esp + XX]"}, + { 5, {0x0F, 0xB6, 0x4C, 0x24, 0x74}, 0, "0F B6 4C 24 XX : movzx ecx, byte ptr [esp + XX]"}, { 5, {0x68, 0x71, 0x72, 0x73, 0x74}, 0, "68 XX XX XX XX : push imm32"}, { 5, {0xb8, 0x71, 0x72, 0x73, 0x74}, 0, "b8 XX XX XX XX : mov eax, XX XX XX XX"}, { 5, {0xB9, 0x71, 0x72, 0x73, 0x74}, 0, "b9 XX XX XX XX : mov ecx, XX XX XX XX"}, @@ -986,6 +993,7 @@ const struct InstructionSizeData { { 4, {0x49, 0x8d, 0x48, 0x73}, 0, "49 8d 48 XX : lea rcx, [...]"}, { 4, {0x4c, 0x8d, 0x04, 0x73}, 0, "4c 8d 04 XX : lea r8, [...]"}, { 4, {0x4e, 0x8d, 0x14, 0x73}, 0, "4e 8d 14 XX : lea r10, [...]"}, + { 4, {0x4F, 0x8D, 0x0C, 0x73}, 0, "4F 8D 0C XX : lea r9, [...]"}, { 4, {0x66, 0x83, 0x39, 0x73}, 0, "66 83 39 XX : cmp WORD PTR [rcx], XX"}, { 4, {0x80, 0x78, 0x72, 0x73}, 0, "80 78 YY XX : cmp BYTE PTR [rax+YY], XX"}, { 4, {0x80, 0x79, 0x72, 0x73}, 0, "80 79 YY XX : cmp BYTE ptr [rcx+YY], XX"}, @@ -1070,7 +1078,6 @@ const struct InstructionSizeData { { 4, {0x8B, 0x6C, 0x24, 0x73}, 0, "8B 6C 24 XX : mov ebp, dword ptr [esp + XX]"}, { 4, {0x8B, 0x74, 0x24, 0x73}, 0, "8B 74 24 XX : mov esi, dword ptr [esp + XX]"}, { 4, {0x8B, 0x7C, 0x24, 0x73}, 0, "8B 7C 24 XX : mov edi, dword ptr [esp + XX]"}, - { 5, {0x0F, 0xB6, 0x44, 0x24, 0x74}, 0, "0F B6 44 24 XX : movzx eax, byte ptr [esp + XX]"}, { 5, {0xA1, 0x71, 0x72, 0x73, 0x74}, 0, "A1 XX XX XX XX : mov eax, dword ptr ds:[XXXXXXXX]"}, { 6, {0xF7, 0xC1, 0x72, 0x73, 0x74, 0x75}, 0, "F7 C1 XX YY ZZ WW : test ecx, WWZZYYXX"}, { 7, {0x83, 0x3D, 0x72, 0x73, 0x74, 0x75, 0x76}, 0, "83 3D XX YY ZZ WW TT : cmp TT, WWZZYYXX"}, _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
