================
@@ -8097,8 +8095,16 @@ void SIInstrInfo::legalizeOperandsVALUt16(MachineInstr
&MI, unsigned OpIdx,
if (!RI.isVGPRClass(CurrRC))
return;
- int16_t RCID = getOpRegClassID(get(Opcode).operands()[OpIdx]);
- const TargetRegisterClass *ExpectedRC = RI.getRegClass(RCID);
+ const TargetRegisterClass *ExpectedRC;
+ if (MI.isPHI()) {
+ // A PHI is generic, so it carries no operand register classes.
+ ExpectedRC = MRI.getRegClass(MI.getOperand(0).getReg());
+ } else {
+ if (OpIdx >= get(Opcode).getNumOperands() ||
+ get(Opcode).operands()[OpIdx].RegClass == -1)
----------------
shiltian wrote:
Use a variable for `get(Opcode).operands()[OpIdx]`?
https://github.com/llvm/llvm-project/pull/222155
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