https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/221670
>From 98b04e58708736f67945aea621ecf324a7f13e50 Mon Sep 17 00:00:00 2001 From: Matt Arsenault <[email protected]> Date: Sun, 6 Sep 2026 13:00:31 +0200 Subject: [PATCH] PPC: Replace EnableAIXExtendedAltivecABI with "target-abi" module flag Continue purging ABI-influencing TargetOptions fields. Eliminate this case by migrating to a module flag, reusing the generic target-abi module flag with a new value. Co-authored-by: Claude (Claude-Opus-4.8) <[email protected]> --- clang/include/clang/Basic/CodeGenOptions.def | 1 - clang/lib/Basic/Targets/PPC.cpp | 3 ++ clang/lib/CodeGen/BackendUtil.cpp | 1 - clang/lib/Driver/ToolChains/CommonArgs.cpp | 11 ----- clang/lib/Frontend/CompilerInvocation.cpp | 3 -- .../PowerPC/aix-vec-extabi-module-flag.c | 18 ++++++++ clang/test/Driver/lto-aix.c | 8 ++-- flang/include/flang/Frontend/TargetOptions.h | 3 -- flang/lib/Frontend/CompilerInstance.cpp | 1 - flang/lib/Frontend/CompilerInvocation.cpp | 9 ++-- flang/lib/Frontend/FrontendActions.cpp | 2 +- .../Integration/PowerPC/aix-vec-extabi.f90 | 13 ++++++ llvm/include/llvm/CodeGen/CommandFlags.h | 2 - llvm/include/llvm/Target/TargetMachine.h | 4 -- llvm/include/llvm/Target/TargetOptions.h | 26 +++++------ llvm/lib/CodeGen/CommandFlags.cpp | 7 --- llvm/lib/Target/PowerPC/PPC.h | 10 ++++- llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp | 2 +- llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 3 +- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp | 43 ++++++++++--------- llvm/lib/Target/PowerPC/PPCSubtarget.h | 6 +++ llvm/lib/Target/PowerPC/PPCTargetMachine.cpp | 2 +- llvm/test/CodeGen/PowerPC/aix-alloca-r31.ll | 4 +- llvm/test/CodeGen/PowerPC/aix-cc-altivec.ll | 4 +- .../CodeGen/PowerPC/aix-cc-ext-vec-abi.ll | 4 +- .../CodeGen/PowerPC/aix-csr-vector-extabi.ll | 8 ++-- .../CodeGen/PowerPC/aix-dfltabi-rsrvd-reg.ll | 2 +- ...ix-emit-tracebacktable-clobber-register.ll | 8 ++-- .../aix-emit-tracebacktable-vectorinfo.ll | 4 +- ...-emit-tracebacktable-vectorinfo_hasvarg.ll | 2 +- .../CodeGen/PowerPC/aix-insert-extract.ll | 4 +- .../test/CodeGen/PowerPC/aix-spills-for-eh.ll | 4 +- .../PowerPC/aix-vec-arg-spills-callee.ll | 8 ++-- .../CodeGen/PowerPC/aix-vec-arg-spills-mir.ll | 4 +- .../CodeGen/PowerPC/aix-vec-arg-spills.ll | 4 +- .../CodeGen/PowerPC/aix-vec_extract_p9.ll | 4 +- .../CodeGen/PowerPC/aix-vec_extract_p9_2.ll | 4 +- .../CodeGen/PowerPC/aix-vec_insert_elt.ll | 8 ++-- .../PowerPC/aix-vector-stack-caller.ll | 4 +- llvm/test/CodeGen/PowerPC/aix-vector-stack.ll | 4 +- .../PowerPC/aix-vector-vararg-caller.ll | 4 +- .../PowerPC/aix-vector-vararg-fixed-caller.ll | 4 +- .../aix32-p8-scalar_vector_conversions.ll | 2 +- .../PowerPC/aix32-vector-pair-cc-spills.ll | 2 +- .../aix32-vector-vararg-callee-split.ll | 2 +- .../PowerPC/aix32-vector-vararg-callee.ll | 2 +- .../aix32-vector-vararg-caller-split.ll | 2 +- .../aix32-vector-vararg-fixed-callee.ll | 2 +- .../PowerPC/aix64-vector-pair-cc-spills.ll | 2 +- .../PowerPC/aix64-vector-vararg-callee.ll | 2 +- .../aix64-vector-vararg-fixed-callee.ll | 2 +- .../PowerPC/aix64-virtual-call-no-spills.ll | 2 +- llvm/test/CodeGen/PowerPC/bswap64.ll | 2 +- .../CodeGen/PowerPC/builtins-ppc-p9-darn.ll | 2 +- .../PowerPC/cannonicalize-vector-shifts.ll | 4 +- llvm/test/CodeGen/PowerPC/cmpb-ppc32.ll | 2 +- llvm/test/CodeGen/PowerPC/cmpb.ll | 2 +- llvm/test/CodeGen/PowerPC/constants-i64.ll | 2 +- llvm/test/CodeGen/PowerPC/fdiv.ll | 2 +- llvm/test/CodeGen/PowerPC/fma-assoc.ll | 2 +- llvm/test/CodeGen/PowerPC/ftrunc-vec.ll | 2 +- llvm/test/CodeGen/PowerPC/gpr-vsr-spill.ll | 2 +- llvm/test/CodeGen/PowerPC/maddld.ll | 2 +- .../test/CodeGen/PowerPC/mi-peephole-splat.ll | 4 +- .../CodeGen/PowerPC/mmaplus-intrinsics.ll | 4 +- llvm/test/CodeGen/PowerPC/mulli.ll | 2 +- .../PowerPC/p10-handle-split-promote-vec.ll | 2 +- .../PowerPC/p8-scalar_vector_conversions.ll | 2 +- .../PowerPC/ppc64-rop-protection-aix.ll | 24 +++++------ llvm/test/CodeGen/PowerPC/pr33093.ll | 2 +- llvm/test/CodeGen/PowerPC/pre-inc-disable.ll | 4 +- llvm/test/CodeGen/PowerPC/setcc-to-sub.ll | 2 +- llvm/test/CodeGen/PowerPC/unal-vec-ldst.ll | 2 +- llvm/test/CodeGen/PowerPC/vec-bswap.ll | 4 +- llvm/test/CodeGen/PowerPC/vec_clz.ll | 4 +- llvm/test/CodeGen/PowerPC/vec_constants.ll | 4 +- llvm/test/CodeGen/PowerPC/vec_revb.ll | 2 +- .../CodeGen/PowerPC/vec_shuffle_p8vector.ll | 4 +- llvm/test/CodeGen/PowerPC/vmladduhm.ll | 4 +- .../test/CodeGen/PowerPC/xxpermdi_mnemonics.s | 8 ++-- .../LoopVectorize/PowerPC/massv-calls.ll | 2 +- .../PGOProfile/ppc-prevent-mma-types.ll | 2 +- 82 files changed, 199 insertions(+), 197 deletions(-) create mode 100644 clang/test/CodeGen/PowerPC/aix-vec-extabi-module-flag.c create mode 100644 flang/test/Integration/PowerPC/aix-vec-extabi.f90 diff --git a/clang/include/clang/Basic/CodeGenOptions.def b/clang/include/clang/Basic/CodeGenOptions.def index 2a04538677005..e93131d9c48fe 100644 --- a/clang/include/clang/Basic/CodeGenOptions.def +++ b/clang/include/clang/Basic/CodeGenOptions.def @@ -57,7 +57,6 @@ CODEGENOPT(UniqueBasicBlockSectionNames, 1, 1, Benign) ///< Set for -funique-bas ///< Produce unique section names with ///< basic block sections. CODEGENOPT(SeparateNamedSections, 1, 0, Benign) ///< Set for -fseparate-named-sections. -CODEGENOPT(EnableAIXExtendedAltivecABI, 1, 0, Benign) ///< Set for -mabi=vec-extabi. Enables the extended Altivec ABI on AIX. CODEGENOPT(XCOFFReadOnlyPointers, 1, 0, Benign) ///< Set for -mxcoff-roptr. CODEGENOPT(AllTocData, 1, 0, Benign) ///< AIX -mtocdata ENUM_CODEGENOPT(FramePointer, FramePointerKind, 3, FramePointerKind::None, Benign) /// frame-pointer: all,non-leaf,non-leaf-no-reserve,reserved,none diff --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp index 1ecb474c1ede8..b293bdb05f241 100644 --- a/clang/lib/Basic/Targets/PPC.cpp +++ b/clang/lib/Basic/Targets/PPC.cpp @@ -843,6 +843,9 @@ void PPCTargetInfo::adjust(DiagnosticsEngine &Diags, LangOptions &Opts, if (getTriple().isOSAIX() && Opts.EnableAIXQuadwordAtomicsABI && HasQuadwordAtomics) MaxAtomicInlineWidth = 128; + + if (getTriple().isOSAIX() && Opts.EnableAIXExtendedAltivecABI) + ABI = "vec-extabi"; } llvm::SmallVector<Builtin::InfosShard> diff --git a/clang/lib/CodeGen/BackendUtil.cpp b/clang/lib/CodeGen/BackendUtil.cpp index 9d8fd319f6f17..b93916064b877 100644 --- a/clang/lib/CodeGen/BackendUtil.cpp +++ b/clang/lib/CodeGen/BackendUtil.cpp @@ -447,7 +447,6 @@ static bool initTargetOptions(const CompilerInstance &CI, Options.ForceDwarfFrameSection = CodeGenOpts.ForceDwarfFrameSection; Options.EmitCallGraphSection = CodeGenOpts.CallGraphSection; Options.EmitCallSiteInfo = CodeGenOpts.EmitCallSiteInfo; - Options.EnableAIXExtendedAltivecABI = LangOpts.EnableAIXExtendedAltivecABI; Options.XRayFunctionIndex = CodeGenOpts.XRayFunctionIndex; Options.LoopAlignment = CodeGenOpts.LoopAlignment; Options.DebugStrictDwarf = CodeGenOpts.DebugStrictDwarf; diff --git a/clang/lib/Driver/ToolChains/CommonArgs.cpp b/clang/lib/Driver/ToolChains/CommonArgs.cpp index 64859a318485b..9ebc1785a2006 100644 --- a/clang/lib/Driver/ToolChains/CommonArgs.cpp +++ b/clang/lib/Driver/ToolChains/CommonArgs.cpp @@ -1253,17 +1253,6 @@ void tools::addLTOOptions(const ToolChain &ToolChain, const ArgList &Args, options::OPT_gno_strict_dwarf, true)) CmdArgs.push_back( Args.MakeArgString(Twine(PluginOptPrefix) + "-strict-dwarf=true")); - - for (const Arg *A : Args.filtered_reverse(options::OPT_mabi_EQ)) { - StringRef V = A->getValue(); - if (V == "vec-default") - break; - if (V == "vec-extabi") { - CmdArgs.push_back( - Args.MakeArgString(Twine(PluginOptPrefix) + "-vec-extabi")); - break; - } - } } bool UseSeparateSections = diff --git a/clang/lib/Frontend/CompilerInvocation.cpp b/clang/lib/Frontend/CompilerInvocation.cpp index 037647f76bd1d..9c0d7b1e310fb 100644 --- a/clang/lib/Frontend/CompilerInvocation.cpp +++ b/clang/lib/Frontend/CompilerInvocation.cpp @@ -1760,9 +1760,6 @@ void CompilerInvocationBase::GenerateCodeGenArgs(const CodeGenOptions &Opts, GenerateArg(Consumer, Opt); } - if (Opts.EnableAIXExtendedAltivecABI) - GenerateArg(Consumer, OPT_mabi_EQ_vec_extabi); - if (Opts.XCOFFReadOnlyPointers) GenerateArg(Consumer, OPT_mxcoff_roptr); diff --git a/clang/test/CodeGen/PowerPC/aix-vec-extabi-module-flag.c b/clang/test/CodeGen/PowerPC/aix-vec-extabi-module-flag.c new file mode 100644 index 0000000000000..0c447767877e9 --- /dev/null +++ b/clang/test/CodeGen/PowerPC/aix-vec-extabi-module-flag.c @@ -0,0 +1,18 @@ +// Check that the AIX extended Altivec ABI is emitted as the "target-abi" module +// flag + +// RUN: %clang_cc1 -triple powerpc-unknown-aix -target-feature +altivec \ +// RUN: -target-cpu pwr8 -mabi=vec-extabi -emit-llvm %s -o - \ +// RUN: | FileCheck %s --check-prefix=EXTABI +// RUN: %clang_cc1 -triple powerpc64-unknown-aix -target-feature +altivec \ +// RUN: -target-cpu pwr8 -mabi=vec-extabi -emit-llvm %s -o - \ +// RUN: | FileCheck %s --check-prefix=EXTABI + +// RUN: %clang_cc1 -triple powerpc-unknown-aix -target-feature +altivec \ +// RUN: -target-cpu pwr8 -emit-llvm %s -o - \ +// RUN: | FileCheck %s --check-prefix=DFLTABI + +// EXTABI: !{i32 1, !"target-abi", !"vec-extabi"} +// DFLTABI-NOT: "target-abi" + +void f(void) {} diff --git a/clang/test/Driver/lto-aix.c b/clang/test/Driver/lto-aix.c index a07dbd759fa5f..381d9207e3ea2 100644 --- a/clang/test/Driver/lto-aix.c +++ b/clang/test/Driver/lto-aix.c @@ -27,14 +27,12 @@ // O2: "-bplugin_opt:-O2" // O3: "-bplugin_opt:-O3" -// vec-extabi option +// The vec-extabi option is emitted into the IR via the "target-abi" module flag +// // RUN: %clang --target=powerpc-ibm-aix --sysroot %S/Inputs/aix_ppc_tree %s \ // RUN: -fuse-ld=ld -flto -mabi=vec-extabi -### 2>&1 \ -// RUN: | FileCheck --check-prefix=VECEXTABI %s -// RUN: %clang --target=powerpc-ibm-aix --sysroot %S/Inputs/aix_ppc_tree %s \ -// RUN: -fuse-ld=ld -flto -### 2>&1 | FileCheck --check-prefix=NOVECEXTABI %s +// RUN: | FileCheck --check-prefix=NOVECEXTABI %s // -// VECEXTABI: "-bplugin_opt:-vec-extabi" // NOVECEXTABI-NOT: "-bplugin_opt:-vec-extabi" // Test debugging options diff --git a/flang/include/flang/Frontend/TargetOptions.h b/flang/include/flang/Frontend/TargetOptions.h index fc7a2a3089f15..3b81c76ffdcd9 100644 --- a/flang/include/flang/Frontend/TargetOptions.h +++ b/flang/include/flang/Frontend/TargetOptions.h @@ -48,9 +48,6 @@ class TargetOptions { /// The integer KINDs disabled for this target std::vector<int> disabledIntegerKinds; - /// Extended Altivec ABI on AIX - bool EnableAIXExtendedAltivecABI; - /// Print verbose assembly bool asmVerbose = false; diff --git a/flang/lib/Frontend/CompilerInstance.cpp b/flang/lib/Frontend/CompilerInstance.cpp index 0b9dfc49c3a81..1b09fcfd049af 100644 --- a/flang/lib/Frontend/CompilerInstance.cpp +++ b/flang/lib/Frontend/CompilerInstance.cpp @@ -380,7 +380,6 @@ bool CompilerInstance::setUpTargetMachine() { std::optional<llvm::CodeModel::Model> cm = getCodeModel(CGOpts.CodeModel); llvm::TargetOptions tOpts = llvm::TargetOptions(); - tOpts.EnableAIXExtendedAltivecABI = targetOpts.EnableAIXExtendedAltivecABI; tOpts.EnableMachineFunctionSplitter = targetOpts.SplitMachineFunctions; tOpts.VecLib = convertDriverVectorLibraryToVectorLibrary(CGOpts.getVecLib()); tOpts.MCOptions.DisableIntegratedAS = CGOpts.DisableIntegratedAS; diff --git a/flang/lib/Frontend/CompilerInvocation.cpp b/flang/lib/Frontend/CompilerInvocation.cpp index b76b38ff6497f..8a303d4e65669 100644 --- a/flang/lib/Frontend/CompilerInvocation.cpp +++ b/flang/lib/Frontend/CompilerInvocation.cpp @@ -612,13 +612,10 @@ static void parseTargetArgs(TargetOptions &opts, llvm::opt::ArgList &args) { opts.disabledIntegerKinds.push_back(16); if (const llvm::opt::Arg *a = args.getLastArg(clang::options::OPT_mabi_EQ)) { - opts.abi = a->getValue(); llvm::StringRef V = a->getValue(); - if (V == "vec-extabi") { - opts.EnableAIXExtendedAltivecABI = true; - } else if (V == "vec-default") { - opts.EnableAIXExtendedAltivecABI = false; - } + // Normalize "vec-default" to an empty ABI name; the AIX extended Altivec + // ABI is carried to the backend as the "vec-extabi" target-abi module flag. + opts.abi = V == "vec-default" ? "" : V.str(); } opts.SplitMachineFunctions = diff --git a/flang/lib/Frontend/FrontendActions.cpp b/flang/lib/Frontend/FrontendActions.cpp index 648574fae18cf..41421e82f25dd 100644 --- a/flang/lib/Frontend/FrontendActions.cpp +++ b/flang/lib/Frontend/FrontendActions.cpp @@ -848,7 +848,7 @@ void CodeGenAction::generateLLVMIR() { } } - if (triple.isRISCV() && !targetOpts.abi.empty()) + if (!targetOpts.abi.empty()) llvmModule->addModuleFlag( llvm::Module::Error, "target-abi", llvm::MDString::get(llvmModule->getContext(), targetOpts.abi)); diff --git a/flang/test/Integration/PowerPC/aix-vec-extabi.f90 b/flang/test/Integration/PowerPC/aix-vec-extabi.f90 new file mode 100644 index 0000000000000..3394ad9aa6ce4 --- /dev/null +++ b/flang/test/Integration/PowerPC/aix-vec-extabi.f90 @@ -0,0 +1,13 @@ +! Check that the AIX extended Altivec ABI is emitted as the +! "target-abi" module flag + +! REQUIRES: target=powerpc{{.*}} +! RUN: %flang_fc1 -triple powerpc-ibm-aix7.2.0.0 -mabi=vec-extabi -emit-llvm -o - %s | FileCheck %s --check-prefix=EXTABI +! RUN: %flang_fc1 -triple powerpc-ibm-aix7.2.0.0 -mabi=vec-default -emit-llvm -o - %s | FileCheck %s --check-prefix=DEFAULT +! RUN: %flang_fc1 -triple powerpc-ibm-aix7.2.0.0 -emit-llvm -o - %s | FileCheck %s --check-prefix=DEFAULT + +! EXTABI: !{i32 1, !"target-abi", !"vec-extabi"} +! DEFAULT-NOT: "target-abi" + +subroutine func +end subroutine func diff --git a/llvm/include/llvm/CodeGen/CommandFlags.h b/llvm/include/llvm/CodeGen/CommandFlags.h index a13e1592e2a0d..3d4bfbdcf883f 100644 --- a/llvm/include/llvm/CodeGen/CommandFlags.h +++ b/llvm/include/llvm/CodeGen/CommandFlags.h @@ -71,8 +71,6 @@ LLVM_ABI bool getDontPlaceZerosInBSS(); LLVM_ABI bool getEnableGuaranteedTailCallOpt(); -LLVM_ABI bool getEnableAIXExtendedAltivecABI(); - LLVM_ABI bool getDisableTailCalls(); LLVM_ABI bool getStackSymbolOrdering(); diff --git a/llvm/include/llvm/Target/TargetMachine.h b/llvm/include/llvm/Target/TargetMachine.h index 57c35ed564616..ba017910c263d 100644 --- a/llvm/include/llvm/Target/TargetMachine.h +++ b/llvm/include/llvm/Target/TargetMachine.h @@ -329,10 +329,6 @@ class LLVM_ABI TargetMachine { void setCFIFixup(bool Enable) { Options.EnableCFIFixup = Enable; } - bool getAIXExtendedAltivecABI() const { - return Options.EnableAIXExtendedAltivecABI; - } - bool getUniqueSectionNames() const { return Options.UniqueSectionNames; } /// Return true if unique basic block section names must be generated. diff --git a/llvm/include/llvm/Target/TargetOptions.h b/llvm/include/llvm/Target/TargetOptions.h index e94e43f0e867f..e9be0fab75cca 100644 --- a/llvm/include/llvm/Target/TargetOptions.h +++ b/llvm/include/llvm/Target/TargetOptions.h @@ -111,16 +111,16 @@ enum CodeObjectVersionKind { class TargetOptions { public: TargetOptions() - : EnableAIXExtendedAltivecABI(false), NoZerosInBSS(false), - GuaranteedTailCallOpt(false), StackSymbolOrdering(true), - EnableFastISel(false), EnableGlobalISel(false), UseInitArray(false), - FunctionSections(false), DataSections(false), - IgnoreXCOFFVisibility(false), XCOFFTracebackTable(true), - UniqueSectionNames(true), UniqueBasicBlockSectionNames(false), - SeparateNamedSections(false), TrapUnreachable(false), - NoTrapAfterNoreturn(false), TLSSize(0), EmulatedTLS(false), - EnableTLSDESC(false), EnableIPRA(false), EmitStackSizeSection(false), - EnableMachineOutliner(false), EnableMachineFunctionSplitter(false), + : NoZerosInBSS(false), GuaranteedTailCallOpt(false), + StackSymbolOrdering(true), EnableFastISel(false), + EnableGlobalISel(false), UseInitArray(false), FunctionSections(false), + DataSections(false), IgnoreXCOFFVisibility(false), + XCOFFTracebackTable(true), UniqueSectionNames(true), + UniqueBasicBlockSectionNames(false), SeparateNamedSections(false), + TrapUnreachable(false), NoTrapAfterNoreturn(false), TLSSize(0), + EmulatedTLS(false), EnableTLSDESC(false), EnableIPRA(false), + EmitStackSizeSection(false), EnableMachineOutliner(false), + EnableMachineFunctionSplitter(false), EnableStaticDataPartitioning(false), SupportsDefaultOutlining(false), EnableDefaultMachineVerifier(true), EmitAddrsig(false), BBAddrMap(false), EmitCallGraphSection(false), EmitCallSiteInfo(false), @@ -130,12 +130,6 @@ class TargetOptions { JMCInstrument(false), EnableCFIFixup(false), MisExpect(false), XCOFFReadOnlyPointers(false), VerifyArgABICompliance(true) {} - /// EnableAIXExtendedAltivecABI - This flag returns true when -vec-extabi is - /// specified. The code generator is then able to use both volatile and - /// nonvolitle vector registers. When false, the code generator only uses - /// volatile vector registers which is the default setting on AIX. - unsigned EnableAIXExtendedAltivecABI : 1; - /// NoZerosInBSS - By default some codegens place zero-initialized data to /// .bss section. This flag disables such behaviour (necessary, e.g. for /// crt*.o compiling). diff --git a/llvm/lib/CodeGen/CommandFlags.cpp b/llvm/lib/CodeGen/CommandFlags.cpp index 2025979ce9178..9e075fe579c7c 100644 --- a/llvm/lib/CodeGen/CommandFlags.cpp +++ b/llvm/lib/CodeGen/CommandFlags.cpp @@ -76,7 +76,6 @@ CGOPT_EXP(uint64_t, LargeDataThreshold) CGOPT(ExceptionHandling, ExceptionModel) CGOPT_EXP(CodeGenFileType, FileType) CGOPT(FramePointerKind, FramePointerUsage) -CGOPT(bool, EnableAIXExtendedAltivecABI) CGOPT(DenormalMode::DenormalModeKind, DenormalFPMath) CGOPT(DenormalMode::DenormalModeKind, DenormalFP32Math) CGOPT(FloatABI::ABIType, FloatABIForCalls) @@ -282,11 +281,6 @@ codegen::RegisterCodeGenFlags::RegisterCodeGenFlags() { cl::init(false)); CGBINDOPT(DontPlaceZerosInBSS); - static cl::opt<bool> EnableAIXExtendedAltivecABI( - "vec-extabi", cl::desc("Enable the AIX Extended Altivec ABI."), - cl::init(false)); - CGBINDOPT(EnableAIXExtendedAltivecABI); - static cl::opt<bool> EnableGuaranteedTailCallOpt( "tailcallopt", cl::desc( @@ -551,7 +545,6 @@ codegen::getBBSectionsMode(llvm::TargetOptions &Options) { TargetOptions codegen::InitTargetOptionsFromCodeGenFlags(const Triple &TheTriple) { TargetOptions Options; - Options.EnableAIXExtendedAltivecABI = getEnableAIXExtendedAltivecABI(); Options.NoZerosInBSS = getDontPlaceZerosInBSS(); Options.GuaranteedTailCallOpt = getEnableGuaranteedTailCallOpt(); Options.StackSymbolOrdering = getStackSymbolOrdering(); diff --git a/llvm/lib/Target/PowerPC/PPC.h b/llvm/lib/Target/PowerPC/PPC.h index 7fe80d5ba52f3..bd04ebb71b8f0 100644 --- a/llvm/lib/Target/PowerPC/PPC.h +++ b/llvm/lib/Target/PowerPC/PPC.h @@ -98,8 +98,14 @@ class ModulePass; createPPCInstructionSelector(const PPCTargetMachine &, const PPCSubtarget &, const PPCRegisterBankInfo &); - /// The PowerPC ABI variant. - enum PPCABI { PPC_ABI_UNKNOWN, PPC_ABI_ELFv1, PPC_ABI_ELFv2 }; + /// The PowerPC ABI variant. PPC_ABI_AIX_EXTABI is the AIX extended Altivec + /// ABI ("vec-extabi"). + enum PPCABI { + PPC_ABI_UNKNOWN, + PPC_ABI_ELFv1, + PPC_ABI_ELFv2, + PPC_ABI_AIX_EXTABI + }; namespace PPCII { diff --git a/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp b/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp index e78eb5239871f..97a8e28c601d0 100644 --- a/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp +++ b/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp @@ -2322,7 +2322,7 @@ uint16_t PPCAIXAsmPrinter::getNumberOfVRSaved() { // in the default ABI. const PPCSubtarget &Subtarget = MF->getSubtarget<PPCSubtarget>(); if (Subtarget.isAIXABI() && Subtarget.hasAltivec() && - TM.getAIXExtendedAltivecABI()) { + Subtarget.isAIXExtendedAltivecABI()) { const MachineRegisterInfo &MRI = MF->getRegInfo(); for (unsigned Reg = PPC::V20; Reg <= PPC::V31; ++Reg) if (MRI.isPhysRegModified(Reg)) diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index 07f018baed2ce..08641d10fd877 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -19015,8 +19015,7 @@ PPCTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, R.second = &PPC::CRRCRegClass; } // FIXME: This warning should ideally be emitted in the front end. - const auto &TM = getTargetMachine(); - if (Subtarget.isAIXABI() && !TM.getAIXExtendedAltivecABI()) { + if (Subtarget.isAIXABI() && !Subtarget.isAIXExtendedAltivecABI()) { if (((R.first >= PPC::V20 && R.first <= PPC::V31) || (R.first >= PPC::VF20 && R.first <= PPC::VF31)) && (R.second == &PPC::VSRCRegClass || R.second == &PPC::VSFRCRegClass)) diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp index ea96394f97ff3..f5d5d945947d5 100644 --- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp +++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp @@ -186,12 +186,12 @@ PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { if (Subtarget.hasVSX()) { if (Subtarget.pairedVectorMemops()) return CSR_64_AllRegs_VSRP_SaveList; - if (Subtarget.isAIXABI() && !TM.getAIXExtendedAltivecABI()) + if (Subtarget.isAIXABI() && !Subtarget.isAIXExtendedAltivecABI()) return CSR_64_AllRegs_AIX_Dflt_VSX_SaveList; return CSR_64_AllRegs_VSX_SaveList; } if (Subtarget.hasAltivec()) { - if (Subtarget.isAIXABI() && !TM.getAIXExtendedAltivecABI()) + if (Subtarget.isAIXABI() && !Subtarget.isAIXExtendedAltivecABI()) return CSR_64_AllRegs_AIX_Dflt_Altivec_SaveList; return CSR_64_AllRegs_Altivec_SaveList; } @@ -235,14 +235,14 @@ PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { if (TM.isPPC64()) { if (Subtarget.pairedVectorMemops()) { if (Subtarget.isAIXABI()) { - if (!TM.getAIXExtendedAltivecABI()) + if (!Subtarget.isAIXExtendedAltivecABI()) return SaveR2 ? CSR_PPC64_R2_SaveList : CSR_PPC64_SaveList; return SaveR2 ? CSR_AIX64_R2_VSRP_SaveList : CSR_AIX64_VSRP_SaveList; } return SaveR2 ? CSR_SVR464_R2_VSRP_SaveList : CSR_SVR464_VSRP_SaveList; } if (Subtarget.hasAltivec() && - (!Subtarget.isAIXABI() || TM.getAIXExtendedAltivecABI())) { + (!Subtarget.isAIXABI() || Subtarget.isAIXExtendedAltivecABI())) { return SaveR2 ? CSR_PPC64_R2_Altivec_SaveList : CSR_PPC64_Altivec_SaveList; } @@ -251,11 +251,11 @@ PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { // 32-bit targets. if (Subtarget.isAIXABI()) { if (Subtarget.pairedVectorMemops()) - return TM.getAIXExtendedAltivecABI() ? CSR_AIX32_VSRP_SaveList - : CSR_AIX32_SaveList; + return Subtarget.isAIXExtendedAltivecABI() ? CSR_AIX32_VSRP_SaveList + : CSR_AIX32_SaveList; if (Subtarget.hasAltivec()) - return TM.getAIXExtendedAltivecABI() ? CSR_AIX32_Altivec_SaveList - : CSR_AIX32_SaveList; + return Subtarget.isAIXExtendedAltivecABI() ? CSR_AIX32_Altivec_SaveList + : CSR_AIX32_SaveList; return CSR_AIX32_SaveList; } if (Subtarget.pairedVectorMemops()) @@ -278,12 +278,12 @@ PPCRegisterInfo::getCallPreservedMask(const MachineFunction &MF, if (Subtarget.hasVSX()) { if (Subtarget.pairedVectorMemops()) return CSR_64_AllRegs_VSRP_RegMask; - if (Subtarget.isAIXABI() && !TM.getAIXExtendedAltivecABI()) + if (Subtarget.isAIXABI() && !Subtarget.isAIXExtendedAltivecABI()) return CSR_64_AllRegs_AIX_Dflt_VSX_RegMask; return CSR_64_AllRegs_VSX_RegMask; } if (Subtarget.hasAltivec()) { - if (Subtarget.isAIXABI() && !TM.getAIXExtendedAltivecABI()) + if (Subtarget.isAIXABI() && !Subtarget.isAIXExtendedAltivecABI()) return CSR_64_AllRegs_AIX_Dflt_Altivec_RegMask; return CSR_64_AllRegs_Altivec_RegMask; } @@ -292,17 +292,18 @@ PPCRegisterInfo::getCallPreservedMask(const MachineFunction &MF, if (Subtarget.isAIXABI()) { if (Subtarget.pairedVectorMemops()) { - if (!TM.getAIXExtendedAltivecABI()) + if (!Subtarget.isAIXExtendedAltivecABI()) return TM.isPPC64() ? CSR_PPC64_RegMask : CSR_AIX32_RegMask; return TM.isPPC64() ? CSR_AIX64_VSRP_RegMask : CSR_AIX32_VSRP_RegMask; } - return TM.isPPC64() - ? ((Subtarget.hasAltivec() && TM.getAIXExtendedAltivecABI()) - ? CSR_PPC64_Altivec_RegMask - : CSR_PPC64_RegMask) - : ((Subtarget.hasAltivec() && TM.getAIXExtendedAltivecABI()) - ? CSR_AIX32_Altivec_RegMask - : CSR_AIX32_RegMask); + return TM.isPPC64() ? ((Subtarget.hasAltivec() && + Subtarget.isAIXExtendedAltivecABI()) + ? CSR_PPC64_Altivec_RegMask + : CSR_PPC64_RegMask) + : ((Subtarget.hasAltivec() && + Subtarget.isAIXExtendedAltivecABI()) + ? CSR_AIX32_Altivec_RegMask + : CSR_AIX32_RegMask); } if (CC == CallingConv::Cold) { @@ -416,7 +417,7 @@ BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const { markSuperRegs(Reserved, Reg); if (Subtarget.isAIXABI() && Subtarget.hasAltivec() && - !TM.getAIXExtendedAltivecABI()) { + !Subtarget.isAIXExtendedAltivecABI()) { // In the AIX default Altivec ABI, vector registers VR20-VR31 are reserved // and cannot be used. for (auto Reg : CSR_Altivec_SaveList) { @@ -655,7 +656,7 @@ unsigned PPCRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC, const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); // Vector registers VR20-VR31 are reserved and cannot be used in the default // Altivec ABI on AIX. - if (!TM.getAIXExtendedAltivecABI() && Subtarget.isAIXABI()) + if (!Subtarget.isAIXExtendedAltivecABI() && Subtarget.isAIXABI()) return 20 - DefaultSafety; } return 32 - DefaultSafety; @@ -663,7 +664,7 @@ unsigned PPCRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC, case PPC::VSSRCRegClassID: case PPC::VSRCRegClassID: { const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); - if (!TM.getAIXExtendedAltivecABI() && Subtarget.isAIXABI()) + if (!Subtarget.isAIXExtendedAltivecABI() && Subtarget.isAIXABI()) // Vector registers VR20-VR31 are reserved and cannot be used in the // default Altivec ABI on AIX. return 52 - DefaultSafety; diff --git a/llvm/lib/Target/PowerPC/PPCSubtarget.h b/llvm/lib/Target/PowerPC/PPCSubtarget.h index f303a3e7ee217..93f4ba2bb6b8d 100644 --- a/llvm/lib/Target/PowerPC/PPCSubtarget.h +++ b/llvm/lib/Target/PowerPC/PPCSubtarget.h @@ -211,6 +211,12 @@ class PPCSubtarget : public PPCGenSubtargetInfo { bool isSVR4ABI() const { return !isAIXABI(); } bool isELFv2ABI() const; + /// Returns true when the AIX extended Altivec ABI ("vec-extabi") is in + /// effect, allowing use of the nonvolatile vector registers. + bool isAIXExtendedAltivecABI() const { + return TargetABI == PPC_ABI_AIX_EXTABI; + } + bool is64BitELFABI() const { return isSVR4ABI() && isPPC64(); } bool is32BitELFABI() const { return isSVR4ABI() && !isPPC64(); } bool isUsingPCRelativeCalls() const; diff --git a/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp b/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp index ef86320bd5c87..8028f017d80f0 100644 --- a/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp +++ b/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp @@ -200,7 +200,7 @@ PPCABI PPCTargetMachine::computeABI(const Triple &TT, StringRef ABIName) { return PPC_ABI_ELFv2; if (TT.isOSAIX()) - return PPC_ABI_UNKNOWN; + return ABIName == "vec-extabi" ? PPC_ABI_AIX_EXTABI : PPC_ABI_UNKNOWN; switch (TT.getArch()) { case Triple::ppc64le: diff --git a/llvm/test/CodeGen/PowerPC/aix-alloca-r31.ll b/llvm/test/CodeGen/PowerPC/aix-alloca-r31.ll index ed2c91f1e69b2..e5fa1554c643a 100644 --- a/llvm/test/CodeGen/PowerPC/aix-alloca-r31.ll +++ b/llvm/test/CodeGen/PowerPC/aix-alloca-r31.ll @@ -1,10 +1,10 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs -mtriple powerpc-ibm-aix-xcoff -mcpu=pwr4 \ -; RUN: -mattr=+altivec -vec-extabi -xcoff-traceback-table=true < %s | \ +; RUN: -mattr=+altivec -target-abi=vec-extabi -xcoff-traceback-table=true < %s | \ ; RUN: FileCheck --check-prefix=CHECK-ASM32 %s ; RUN: llc -verify-machineinstrs -mtriple powerpc64-ibm-aix-xcoff --code-model=small -mcpu=pwr4 \ -; RUN: -mattr=+altivec -vec-extabi -xcoff-traceback-table=true < %s | \ +; RUN: -mattr=+altivec -target-abi=vec-extabi -xcoff-traceback-table=true < %s | \ ; RUN: FileCheck --check-prefix=CHECK-ASM64 %s @var = local_unnamed_addr global i32 0 diff --git a/llvm/test/CodeGen/PowerPC/aix-cc-altivec.ll b/llvm/test/CodeGen/PowerPC/aix-cc-altivec.ll index fe91db98e52d5..1e7daa814fcaa 100644 --- a/llvm/test/CodeGen/PowerPC/aix-cc-altivec.ll +++ b/llvm/test/CodeGen/PowerPC/aix-cc-altivec.ll @@ -1,6 +1,6 @@ -; RUN: llc < %s -mtriple powerpc64-ibm-aix-xcoff -vec-extabi -mcpu=pwr8 2>&1 +; RUN: llc < %s -mtriple powerpc64-ibm-aix-xcoff -target-abi=vec-extabi -mcpu=pwr8 2>&1 ; | FileCheck %s --check-prefix=ASM64 -; RUN: llc < %s -mtriple powerpc-ibm-aix-xcoff -vec-extabi -mcpu=pwr8 2>&1 +; RUN: llc < %s -mtriple powerpc-ibm-aix-xcoff -target-abi=vec-extabi -mcpu=pwr8 2>&1 ; | FileCheck %s --check-prefix=ASM32 @f1 = global float 0.000000e+00, align 4 diff --git a/llvm/test/CodeGen/PowerPC/aix-cc-ext-vec-abi.ll b/llvm/test/CodeGen/PowerPC/aix-cc-ext-vec-abi.ll index 5da25e081a16e..0a864b9e990f0 100644 --- a/llvm/test/CodeGen/PowerPC/aix-cc-ext-vec-abi.ll +++ b/llvm/test/CodeGen/PowerPC/aix-cc-ext-vec-abi.ll @@ -1,9 +1,9 @@ ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=+altivec -xcoff-traceback-table=false \ -; RUN: -vec-extabi -mtriple powerpc-ibm-aix-xcoff < %s | \ +; RUN: -target-abi=vec-extabi -mtriple powerpc-ibm-aix-xcoff < %s | \ ; RUN: FileCheck --check-prefixes=ASM32,ASM %s ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=+altivec -xcoff-traceback-table=false \ -; RUN: -vec-extabi -mtriple powerpc64-ibm-aix-xcoff --code-model=small < %s | \ +; RUN: -target-abi=vec-extabi -mtriple powerpc64-ibm-aix-xcoff --code-model=small < %s | \ ; RUN: FileCheck --check-prefixes=ASM64,ASM %s define dso_local <4 x i32> @vec_callee(<4 x i32> %vec1, <4 x i32> %vec2, <4 x i32> %vec3, <4 x i32> %vec4, <4 x i32> %vec5, <4 x i32> %vec6, <4 x i32> %vec7, <4 x i32> %vec8, <4 x i32> %vec9, <4 x i32> %vec10, <4 x i32> %vec11, <4 x i32> %vec12) { diff --git a/llvm/test/CodeGen/PowerPC/aix-csr-vector-extabi.ll b/llvm/test/CodeGen/PowerPC/aix-csr-vector-extabi.ll index 000492841d307..a0d5e99c990cb 100644 --- a/llvm/test/CodeGen/PowerPC/aix-csr-vector-extabi.ll +++ b/llvm/test/CodeGen/PowerPC/aix-csr-vector-extabi.ll @@ -1,16 +1,16 @@ -; RUN: llc -mtriple=powerpc-unknown-aix-xcoff -vec-extabi -verify-machineinstrs -mcpu=pwr7 \ +; RUN: llc -mtriple=powerpc-unknown-aix-xcoff -target-abi=vec-extabi -verify-machineinstrs -mcpu=pwr7 \ ; RUN: -mattr=+altivec -stop-after=prolog-epilog < %s | \ ; RUN: FileCheck --check-prefix=MIR32 %s -; RUN: llc -mtriple=powerpc-unknown-aix-xcoff -vec-extabi -verify-machineinstrs \ +; RUN: llc -mtriple=powerpc-unknown-aix-xcoff -target-abi=vec-extabi -verify-machineinstrs \ ; RUN: -mcpu=pwr7 -mattr=+altivec < %s | \ ; RUN: FileCheck --check-prefix=ASM32 %s -; RUN: llc -mtriple=powerpc64-unknown-aix-xcoff -vec-extabi -verify-machineinstrs \ +; RUN: llc -mtriple=powerpc64-unknown-aix-xcoff -target-abi=vec-extabi -verify-machineinstrs \ ; RUN: -mcpu=pwr7 -mattr=+altivec -stop-after=prolog-epilog < %s | \ ; RUN: FileCheck --check-prefix=MIR64 %s -; RUN: llc -mtriple=powerpc64-unknown-aix-xcoff -vec-extabi -verify-machineinstrs \ +; RUN: llc -mtriple=powerpc64-unknown-aix-xcoff -target-abi=vec-extabi -verify-machineinstrs \ ; RUN: -mcpu=pwr7 -mattr=+altivec < %s | \ ; RUN: FileCheck --check-prefix=ASM64 %s diff --git a/llvm/test/CodeGen/PowerPC/aix-dfltabi-rsrvd-reg.ll b/llvm/test/CodeGen/PowerPC/aix-dfltabi-rsrvd-reg.ll index 0173a88be7eec..61bd6919b2cc3 100644 --- a/llvm/test/CodeGen/PowerPC/aix-dfltabi-rsrvd-reg.ll +++ b/llvm/test/CodeGen/PowerPC/aix-dfltabi-rsrvd-reg.ll @@ -3,7 +3,7 @@ ; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mattr=+altivec \ ; RUN: -stop-after=machine-cp -mtriple powerpc64-ibm-aix-xcoff < %s | \ ; RUN: FileCheck %s --check-prefix=DFLABI -; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mattr=+altivec -vec-extabi\ +; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mattr=+altivec -target-abi=vec-extabi\ ; RUN: -stop-after=machine-cp -mtriple powerpc64-ibm-aix-xcoff < %s | \ ; RUN: FileCheck %s --check-prefix=EXTABI diff --git a/llvm/test/CodeGen/PowerPC/aix-emit-tracebacktable-clobber-register.ll b/llvm/test/CodeGen/PowerPC/aix-emit-tracebacktable-clobber-register.ll index 8e4e0d352e3f0..9ed665b924bc9 100644 --- a/llvm/test/CodeGen/PowerPC/aix-emit-tracebacktable-clobber-register.ll +++ b/llvm/test/CodeGen/PowerPC/aix-emit-tracebacktable-clobber-register.ll @@ -1,18 +1,18 @@ ; RUN: llc -verify-machineinstrs -mtriple powerpc-ibm-aix-xcoff -mcpu=pwr4 \ -; RUN: -mattr=+altivec -vec-extabi -xcoff-traceback-table=true < %s | \ +; RUN: -mattr=+altivec -target-abi=vec-extabi -xcoff-traceback-table=true < %s | \ ; RUN: FileCheck --check-prefixes=CHECK-ASM,COMMON %s ; RUN: llc -verify-machineinstrs -mtriple powerpc-ibm-aix-xcoff -function-sections \ -; RUN: -mcpu=pwr4 -mattr=+altivec -vec-extabi < %s | \ +; RUN: -mcpu=pwr4 -mattr=+altivec -target-abi=vec-extabi < %s | \ ; RUN: FileCheck --check-prefixes=CHECK-FUNC,COMMON %s ; RUN: llc -verify-machineinstrs -mtriple powerpc-ibm-aix-xcoff -mcpu=pwr4 \ -; RUN: -mattr=+altivec -vec-extabi -xcoff-traceback-table=true -filetype=obj -o %t.o < %s +; RUN: -mattr=+altivec -target-abi=vec-extabi -xcoff-traceback-table=true -filetype=obj -o %t.o < %s ; RUN: llvm-objdump -d --traceback-table --symbol-description %t.o | \ ; RUN: FileCheck --match-full-lines --strict-whitespace --check-prefixes=OBJ-DIS,NO-FUNC-SEC %s ; RUN: llc -verify-machineinstrs -mtriple powerpc-ibm-aix-xcoff -mcpu=pwr4 \ -; RUN: -mattr=+altivec -vec-extabi -xcoff-traceback-table=true -function-sections -filetype=obj -o %t_func.o < %s +; RUN: -mattr=+altivec -target-abi=vec-extabi -xcoff-traceback-table=true -function-sections -filetype=obj -o %t_func.o < %s ; RUN: llvm-objdump -d --traceback-table --symbol-description %t_func.o | \ ; RUN: FileCheck --match-full-lines --strict-whitespace --check-prefixes=OBJ-DIS,FUNC-SEC %s diff --git a/llvm/test/CodeGen/PowerPC/aix-emit-tracebacktable-vectorinfo.ll b/llvm/test/CodeGen/PowerPC/aix-emit-tracebacktable-vectorinfo.ll index f03a6c0dd4519..02f4f57c1a098 100644 --- a/llvm/test/CodeGen/PowerPC/aix-emit-tracebacktable-vectorinfo.ll +++ b/llvm/test/CodeGen/PowerPC/aix-emit-tracebacktable-vectorinfo.ll @@ -1,9 +1,9 @@ ; RUN: llc -verify-machineinstrs -mtriple powerpc-ibm-aix-xcoff -mcpu=pwr7 \ -; RUN: -mattr=+altivec -vec-extabi -xcoff-traceback-table=true < %s | \ +; RUN: -mattr=+altivec -target-abi=vec-extabi -xcoff-traceback-table=true < %s | \ ; RUN: FileCheck --check-prefixes=CHECK-ASM,COMMON %s ; RUN: llc -verify-machineinstrs -mtriple powerpc-ibm-aix-xcoff -function-sections \ -; RUN: -mcpu=pwr7 -mattr=+altivec -vec-extabi < %s | \ +; RUN: -mcpu=pwr7 -mattr=+altivec -target-abi=vec-extabi < %s | \ ; RUN: FileCheck --check-prefixes=CHECK-FUNC,COMMON %s ;; #include <altivec.h> diff --git a/llvm/test/CodeGen/PowerPC/aix-emit-tracebacktable-vectorinfo_hasvarg.ll b/llvm/test/CodeGen/PowerPC/aix-emit-tracebacktable-vectorinfo_hasvarg.ll index 26506f84f9ed0..82a44de9cfa49 100644 --- a/llvm/test/CodeGen/PowerPC/aix-emit-tracebacktable-vectorinfo_hasvarg.ll +++ b/llvm/test/CodeGen/PowerPC/aix-emit-tracebacktable-vectorinfo_hasvarg.ll @@ -1,5 +1,5 @@ ; RUN: llc -verify-machineinstrs -mtriple powerpc-ibm-aix-xcoff -mcpu=pwr7 \ -; RUN: -mattr=+altivec -vec-extabi -xcoff-traceback-table=true 2>&1 < %s | \ +; RUN: -mattr=+altivec -target-abi=vec-extabi -xcoff-traceback-table=true 2>&1 < %s | \ ; RUN: FileCheck --check-prefixes=CHECK-ASM %s ;; void f(vector float vf, ...) { diff --git a/llvm/test/CodeGen/PowerPC/aix-insert-extract.ll b/llvm/test/CodeGen/PowerPC/aix-insert-extract.ll index c3ee88cc31a0b..4a92fd99d8f72 100644 --- a/llvm/test/CodeGen/PowerPC/aix-insert-extract.ll +++ b/llvm/test/CodeGen/PowerPC/aix-insert-extract.ll @@ -1,6 +1,6 @@ -; RUN: llc -mcpu=pwr9 -mtriple=powerpc64-ibm-aix-xcoff -vec-extabi \ +; RUN: llc -mcpu=pwr9 -mtriple=powerpc64-ibm-aix-xcoff -target-abi=vec-extabi \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK-64 -; RUN: llc -mcpu=pwr9 -mtriple=powerpc-ibm-aix-xcoff -vec-extabi \ +; RUN: llc -mcpu=pwr9 -mtriple=powerpc-ibm-aix-xcoff -target-abi=vec-extabi \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK-32 define <4 x float> @_Z7testInsILj0ELj0EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) { diff --git a/llvm/test/CodeGen/PowerPC/aix-spills-for-eh.ll b/llvm/test/CodeGen/PowerPC/aix-spills-for-eh.ll index 73004e8758731..ec9d1e82f7fcb 100644 --- a/llvm/test/CodeGen/PowerPC/aix-spills-for-eh.ll +++ b/llvm/test/CodeGen/PowerPC/aix-spills-for-eh.ll @@ -1,9 +1,9 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mcpu=pwr9 -mattr=+altivec -verify-machineinstrs --vec-extabi \ +; RUN: llc -mcpu=pwr9 -mattr=+altivec -verify-machineinstrs -target-abi=vec-extabi \ ; RUN: -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \ ; RUN: -mtriple=powerpc-unknown-aix < %s | FileCheck %s --check-prefix 32BIT -; RUN: llc -mcpu=pwr9 -mattr=+altivec -verify-machineinstrs --vec-extabi \ +; RUN: llc -mcpu=pwr9 -mattr=+altivec -verify-machineinstrs -target-abi=vec-extabi \ ; RUN: -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \ ; RUN: -mtriple=powerpc64-unknown-aix < %s | FileCheck %s --check-prefix 64BIT diff --git a/llvm/test/CodeGen/PowerPC/aix-vec-arg-spills-callee.ll b/llvm/test/CodeGen/PowerPC/aix-vec-arg-spills-callee.ll index 81b3e71e53598..62a9c9a054954 100644 --- a/llvm/test/CodeGen/PowerPC/aix-vec-arg-spills-callee.ll +++ b/llvm/test/CodeGen/PowerPC/aix-vec-arg-spills-callee.ll @@ -1,16 +1,16 @@ ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=+altivec \ -; RUN: -vec-extabi -mtriple powerpc-ibm-aix-xcoff < %s | \ +; RUN: -target-abi=vec-extabi -mtriple powerpc-ibm-aix-xcoff < %s | \ ; RUN: FileCheck %s --check-prefix=32BIT -; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=+altivec -vec-extabi \ +; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=+altivec -target-abi=vec-extabi \ ; RUN: -stop-after=machine-cp -mtriple powerpc-ibm-aix-xcoff < %s | \ ; RUN: FileCheck %s --check-prefix=MIR32 ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=+altivec \ -; RUN: -vec-extabi -mtriple powerpc64-ibm-aix-xcoff < %s | \ +; RUN: -target-abi=vec-extabi -mtriple powerpc64-ibm-aix-xcoff < %s | \ ; RUN: FileCheck %s --check-prefix=64BIT -; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=+altivec -vec-extabi \ +; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=+altivec -target-abi=vec-extabi \ ; RUN: -stop-after=machine-cp -mtriple powerpc64-ibm-aix-xcoff < %s | \ ; RUN: FileCheck %s --check-prefix=MIR64 diff --git a/llvm/test/CodeGen/PowerPC/aix-vec-arg-spills-mir.ll b/llvm/test/CodeGen/PowerPC/aix-vec-arg-spills-mir.ll index 1127bcc64c354..83e189f086f15 100644 --- a/llvm/test/CodeGen/PowerPC/aix-vec-arg-spills-mir.ll +++ b/llvm/test/CodeGen/PowerPC/aix-vec-arg-spills-mir.ll @@ -1,9 +1,9 @@ ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=+altivec -vec-extabi \ +; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=+altivec -target-abi=vec-extabi \ ; RUN: -stop-after=machine-cp -mtriple powerpc-ibm-aix-xcoff < %s | \ ; RUN: FileCheck %s --check-prefix=MIR32 -; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=+altivec -vec-extabi \ +; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=+altivec -target-abi=vec-extabi \ ; RUN: -stop-after=machine-cp -mtriple powerpc64-ibm-aix-xcoff --code-model=small < %s | \ ; RUN: FileCheck %s --check-prefix=MIR64 diff --git a/llvm/test/CodeGen/PowerPC/aix-vec-arg-spills.ll b/llvm/test/CodeGen/PowerPC/aix-vec-arg-spills.ll index 1ae8abec2134d..87248f71eea20 100644 --- a/llvm/test/CodeGen/PowerPC/aix-vec-arg-spills.ll +++ b/llvm/test/CodeGen/PowerPC/aix-vec-arg-spills.ll @@ -1,10 +1,10 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=+altivec \ -; RUN: -vec-extabi -mtriple powerpc-ibm-aix-xcoff < %s | \ +; RUN: -target-abi=vec-extabi -mtriple powerpc-ibm-aix-xcoff < %s | \ ; RUN: FileCheck %s --check-prefix=32BIT ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=+altivec \ -; RUN: -vec-extabi -mtriple powerpc64-ibm-aix-xcoff --code-model=small < %s | \ +; RUN: -target-abi=vec-extabi -mtriple powerpc64-ibm-aix-xcoff --code-model=small < %s | \ ; RUN: FileCheck %s --check-prefix=64BIT %struct.Test = type { double, double, double, double } diff --git a/llvm/test/CodeGen/PowerPC/aix-vec_extract_p9.ll b/llvm/test/CodeGen/PowerPC/aix-vec_extract_p9.ll index 2fdb142776a20..79d0c73ccd119 100644 --- a/llvm/test/CodeGen/PowerPC/aix-vec_extract_p9.ll +++ b/llvm/test/CodeGen/PowerPC/aix-vec_extract_p9.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -verify-machineinstrs -mtriple=powerpc64-ibm-aix-xcoff -vec-extabi -mcpu=pwr9 < %s | FileCheck %s -check-prefix=CHECK-64 -; RUN: llc -verify-machineinstrs -mtriple=powerpc-ibm-aix-xcoff -vec-extabi -mcpu=pwr9 < %s | FileCheck %s -check-prefix=CHECK-32 +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-ibm-aix-xcoff -target-abi=vec-extabi -mcpu=pwr9 < %s | FileCheck %s -check-prefix=CHECK-64 +; RUN: llc -verify-machineinstrs -mtriple=powerpc-ibm-aix-xcoff -target-abi=vec-extabi -mcpu=pwr9 < %s | FileCheck %s -check-prefix=CHECK-32 define zeroext i8 @test1(<16 x i8> %a, i32 signext %index) { ; CHECK-64-LABEL: test1: diff --git a/llvm/test/CodeGen/PowerPC/aix-vec_extract_p9_2.ll b/llvm/test/CodeGen/PowerPC/aix-vec_extract_p9_2.ll index f73ac9b9a16e3..3cdd0f9affa57 100644 --- a/llvm/test/CodeGen/PowerPC/aix-vec_extract_p9_2.ll +++ b/llvm/test/CodeGen/PowerPC/aix-vec_extract_p9_2.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -verify-machineinstrs -mtriple=powerpc64-ibm-aix-xcoff -vec-extabi -mcpu=pwr9 < %s | FileCheck %s -check-prefix=CHECK-64 -; RUN: llc -verify-machineinstrs -mtriple=powerpc-ibm-aix-xcoff -vec-extabi -mcpu=pwr9 < %s | FileCheck %s -check-prefix=CHECK-32 +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-ibm-aix-xcoff -target-abi=vec-extabi -mcpu=pwr9 < %s | FileCheck %s -check-prefix=CHECK-64 +; RUN: llc -verify-machineinstrs -mtriple=powerpc-ibm-aix-xcoff -target-abi=vec-extabi -mcpu=pwr9 < %s | FileCheck %s -check-prefix=CHECK-32 define zeroext i8 @test_add1(<16 x i8> %a, i32 signext %index, i8 zeroext %c) { ; CHECK-64-LABEL: test_add1: diff --git a/llvm/test/CodeGen/PowerPC/aix-vec_insert_elt.ll b/llvm/test/CodeGen/PowerPC/aix-vec_insert_elt.ll index d339c92f270d1..6b39e0df5c345 100644 --- a/llvm/test/CodeGen/PowerPC/aix-vec_insert_elt.ll +++ b/llvm/test/CodeGen/PowerPC/aix-vec_insert_elt.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -verify-machineinstrs -mtriple=powerpc64-ibm-aix-xcoff -vec-extabi -mcpu=pwr9 < %s | FileCheck %s -check-prefix=CHECK-64 -; RUN: llc -verify-machineinstrs -mtriple=powerpc-ibm-aix-xcoff -vec-extabi -mcpu=pwr9 < %s | FileCheck %s -check-prefix=CHECK-32 -; RUN: llc -verify-machineinstrs -mtriple=powerpc64-ibm-aix-xcoff -vec-extabi -mcpu=pwr10 < %s | FileCheck %s -check-prefix=CHECK-64-P10 -; RUN: llc -verify-machineinstrs -mtriple=powerpc-ibm-aix-xcoff -vec-extabi -mcpu=pwr10 < %s | FileCheck %s -check-prefix=CHECK-32-P10 +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-ibm-aix-xcoff -target-abi=vec-extabi -mcpu=pwr9 < %s | FileCheck %s -check-prefix=CHECK-64 +; RUN: llc -verify-machineinstrs -mtriple=powerpc-ibm-aix-xcoff -target-abi=vec-extabi -mcpu=pwr9 < %s | FileCheck %s -check-prefix=CHECK-32 +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-ibm-aix-xcoff -target-abi=vec-extabi -mcpu=pwr10 < %s | FileCheck %s -check-prefix=CHECK-64-P10 +; RUN: llc -verify-machineinstrs -mtriple=powerpc-ibm-aix-xcoff -target-abi=vec-extabi -mcpu=pwr10 < %s | FileCheck %s -check-prefix=CHECK-32-P10 ; Byte indexed diff --git a/llvm/test/CodeGen/PowerPC/aix-vector-stack-caller.ll b/llvm/test/CodeGen/PowerPC/aix-vector-stack-caller.ll index 9404c72062ab6..be358eadde821 100644 --- a/llvm/test/CodeGen/PowerPC/aix-vector-stack-caller.ll +++ b/llvm/test/CodeGen/PowerPC/aix-vector-stack-caller.ll @@ -1,10 +1,10 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=+altivec \ -; RUN: -vec-extabi -mtriple powerpc-ibm-aix-xcoff < %s | \ +; RUN: -target-abi=vec-extabi -mtriple powerpc-ibm-aix-xcoff < %s | \ ; RUN: FileCheck %s --check-prefixes=32BIT,LITERAL ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=+altivec \ -; RUN: -vec-extabi -mtriple powerpc64-ibm-aix-xcoff --code-model=small < %s | \ +; RUN: -target-abi=vec-extabi -mtriple powerpc64-ibm-aix-xcoff --code-model=small < %s | \ ; RUN: FileCheck %s --check-prefixes=64BIT,LITERAL define dso_local i32 @vec_caller() { diff --git a/llvm/test/CodeGen/PowerPC/aix-vector-stack.ll b/llvm/test/CodeGen/PowerPC/aix-vector-stack.ll index 26cf459882f5b..b4f9f36c01e39 100644 --- a/llvm/test/CodeGen/PowerPC/aix-vector-stack.ll +++ b/llvm/test/CodeGen/PowerPC/aix-vector-stack.ll @@ -1,9 +1,9 @@ ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=+altivec \ -; RUN: -vec-extabi -mtriple powerpc-ibm-aix-xcoff < %s | \ +; RUN: -target-abi=vec-extabi -mtriple powerpc-ibm-aix-xcoff < %s | \ ; RUN: FileCheck %s --check-prefix=32BIT ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=+altivec \ -; RUN: -vec-extabi -mtriple powerpc64-ibm-aix-xcoff < %s | \ +; RUN: -target-abi=vec-extabi -mtriple powerpc64-ibm-aix-xcoff < %s | \ ; RUN: FileCheck %s --check-prefix=64BIT define dso_local <4 x i32> @vec_callee_stack(<4 x i32> %vr2, <4 x i32> %vr3, <4 x i32> %vr4, <4 x i32> %vr5, <4 x i32> %vr6, <4 x i32> %vr7, <4 x i32> %vr8, <4 x i32> %vr9, <4 x i32> %vr10, <4 x i32> %vr11, <4 x i32> %vr12, <4 x i32> %vr13, <4 x i32> %vSpill1, <4 x i32> %vSpill2) { diff --git a/llvm/test/CodeGen/PowerPC/aix-vector-vararg-caller.ll b/llvm/test/CodeGen/PowerPC/aix-vector-vararg-caller.ll index 2035c742a6bad..6199bcbfdca2d 100644 --- a/llvm/test/CodeGen/PowerPC/aix-vector-vararg-caller.ll +++ b/llvm/test/CodeGen/PowerPC/aix-vector-vararg-caller.ll @@ -1,9 +1,9 @@ ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -; RUN: llc -verify-machineinstrs -stop-before=ppc-vsx-copy -vec-extabi \ +; RUN: llc -verify-machineinstrs -stop-before=ppc-vsx-copy -target-abi=vec-extabi \ ; RUN: -mcpu=pwr7 -mtriple powerpc-ibm-aix-xcoff < %s | \ ; RUN: FileCheck --check-prefix=32BIT %s -; RUN: llc -verify-machineinstrs -stop-before=ppc-vsx-copy -vec-extabi \ +; RUN: llc -verify-machineinstrs -stop-before=ppc-vsx-copy -target-abi=vec-extabi \ ; RUN: -mcpu=pwr7 -mtriple powerpc64-ibm-aix-xcoff --code-model=small < %s | \ ; RUN: FileCheck --check-prefix=64BIT %s diff --git a/llvm/test/CodeGen/PowerPC/aix-vector-vararg-fixed-caller.ll b/llvm/test/CodeGen/PowerPC/aix-vector-vararg-fixed-caller.ll index 02c9d6dca192c..fb5dae3201897 100644 --- a/llvm/test/CodeGen/PowerPC/aix-vector-vararg-fixed-caller.ll +++ b/llvm/test/CodeGen/PowerPC/aix-vector-vararg-fixed-caller.ll @@ -1,9 +1,9 @@ ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -; RUN: llc -verify-machineinstrs -stop-before=ppc-vsx-copy -vec-extabi \ +; RUN: llc -verify-machineinstrs -stop-before=ppc-vsx-copy -target-abi=vec-extabi \ ; RUN: -mcpu=pwr7 -mtriple powerpc-ibm-aix-xcoff < %s | \ ; RUN: FileCheck --check-prefix=32BIT %s -; RUN: llc -verify-machineinstrs -stop-before=ppc-vsx-copy -vec-extabi \ +; RUN: llc -verify-machineinstrs -stop-before=ppc-vsx-copy -target-abi=vec-extabi \ ; RUN: -mcpu=pwr7 -mtriple powerpc64-ibm-aix-xcoff --code-model=small < %s | \ ; RUN: FileCheck --check-prefix=64BIT %s diff --git a/llvm/test/CodeGen/PowerPC/aix32-p8-scalar_vector_conversions.ll b/llvm/test/CodeGen/PowerPC/aix32-p8-scalar_vector_conversions.ll index cda3b4dac6d33..f398561af5546 100644 --- a/llvm/test/CodeGen/PowerPC/aix32-p8-scalar_vector_conversions.ll +++ b/llvm/test/CodeGen/PowerPC/aix32-p8-scalar_vector_conversions.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc < %s -mtriple=powerpc-ibm-aix-xcoff -verify-machineinstrs \ -; RUN: -mcpu=pwr8 -vec-extabi | FileCheck %s +; RUN: -mcpu=pwr8 -target-abi=vec-extabi | FileCheck %s ; The build[csilf] functions simply test the scalar_to_vector handling with ; direct moves. This corresponds to the "insertelement" instruction. Subsequent diff --git a/llvm/test/CodeGen/PowerPC/aix32-vector-pair-cc-spills.ll b/llvm/test/CodeGen/PowerPC/aix32-vector-pair-cc-spills.ll index 1ebcef002d6c5..58a634d5ac1ff 100644 --- a/llvm/test/CodeGen/PowerPC/aix32-vector-pair-cc-spills.ll +++ b/llvm/test/CodeGen/PowerPC/aix32-vector-pair-cc-spills.ll @@ -1,6 +1,6 @@ ; RUN: llc -O0 -mtriple=powerpc-ibm-aix-xcoff -mcpu=pwr10 -stop-after=prolog-epilog -verify-machineinstrs < %s | \ ; RUN: FileCheck --check-prefix=CHECK %s -; RUN: llc -O0 -mtriple=powerpc-ibm-aix-xcoff -mcpu=pwr10 -vec-extabi -stop-after=prolog-epilog -verify-machineinstrs < %s | \ +; RUN: llc -O0 -mtriple=powerpc-ibm-aix-xcoff -mcpu=pwr10 -target-abi=vec-extabi -stop-after=prolog-epilog -verify-machineinstrs < %s | \ ; RUN: FileCheck --check-prefix=CHECK-VEXT %s ; CHECK-LABEL: name: foo diff --git a/llvm/test/CodeGen/PowerPC/aix32-vector-vararg-callee-split.ll b/llvm/test/CodeGen/PowerPC/aix32-vector-vararg-callee-split.ll index 3e50d61a5d2fb..fc4d511c179a1 100644 --- a/llvm/test/CodeGen/PowerPC/aix32-vector-vararg-callee-split.ll +++ b/llvm/test/CodeGen/PowerPC/aix32-vector-vararg-callee-split.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -; RUN: llc -verify-machineinstrs -stop-before=ppc-vsx-copy -vec-extabi \ +; RUN: llc -verify-machineinstrs -stop-before=ppc-vsx-copy -target-abi=vec-extabi \ ; RUN: -mcpu=pwr7 -mtriple powerpc-ibm-aix-xcoff < %s | \ ; RUN: FileCheck %s diff --git a/llvm/test/CodeGen/PowerPC/aix32-vector-vararg-callee.ll b/llvm/test/CodeGen/PowerPC/aix32-vector-vararg-callee.ll index 600ad2e4e8c67..8ac4dc1c4d1fc 100644 --- a/llvm/test/CodeGen/PowerPC/aix32-vector-vararg-callee.ll +++ b/llvm/test/CodeGen/PowerPC/aix32-vector-vararg-callee.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -; RUN: llc -verify-machineinstrs -stop-before=ppc-vsx-copy -vec-extabi \ +; RUN: llc -verify-machineinstrs -stop-before=ppc-vsx-copy -target-abi=vec-extabi \ ; RUN: -mcpu=pwr7 -mtriple powerpc-ibm-aix-xcoff < %s | \ ; RUN: FileCheck %s diff --git a/llvm/test/CodeGen/PowerPC/aix32-vector-vararg-caller-split.ll b/llvm/test/CodeGen/PowerPC/aix32-vector-vararg-caller-split.ll index 9e50455a0b42a..d21e436ef5c41 100644 --- a/llvm/test/CodeGen/PowerPC/aix32-vector-vararg-caller-split.ll +++ b/llvm/test/CodeGen/PowerPC/aix32-vector-vararg-caller-split.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs -stop-before=ppc-vsx-copy -vec-extabi \ +; RUN: llc -verify-machineinstrs -stop-before=ppc-vsx-copy -target-abi=vec-extabi \ ; RUN: -mcpu=pwr7 -mtriple powerpc-ibm-aix-xcoff < %s 2>&1 | \ ; RUN: FileCheck %s diff --git a/llvm/test/CodeGen/PowerPC/aix32-vector-vararg-fixed-callee.ll b/llvm/test/CodeGen/PowerPC/aix32-vector-vararg-fixed-callee.ll index bd3076d64678a..572a0525a2407 100644 --- a/llvm/test/CodeGen/PowerPC/aix32-vector-vararg-fixed-callee.ll +++ b/llvm/test/CodeGen/PowerPC/aix32-vector-vararg-fixed-callee.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -; RUN: llc -verify-machineinstrs -stop-before=ppc-vsx-copy -vec-extabi \ +; RUN: llc -verify-machineinstrs -stop-before=ppc-vsx-copy -target-abi=vec-extabi \ ; RUN: -mcpu=pwr7 -mtriple powerpc-ibm-aix-xcoff < %s | \ ; RUN: FileCheck %s diff --git a/llvm/test/CodeGen/PowerPC/aix64-vector-pair-cc-spills.ll b/llvm/test/CodeGen/PowerPC/aix64-vector-pair-cc-spills.ll index 325927846ec23..4b7fdc6c37cb2 100644 --- a/llvm/test/CodeGen/PowerPC/aix64-vector-pair-cc-spills.ll +++ b/llvm/test/CodeGen/PowerPC/aix64-vector-pair-cc-spills.ll @@ -1,6 +1,6 @@ ; RUN: llc -O0 -mtriple=powerpc64-ibm-aix-xcoff -mcpu=pwr10 -stop-after=prolog-epilog -verify-machineinstrs < %s | \ ; RUN: FileCheck --check-prefix=CHECK %s -; RUN: llc -O0 -mtriple=powerpc64-ibm-aix-xcoff -mcpu=pwr10 -vec-extabi -stop-after=prolog-epilog -verify-machineinstrs < %s | \ +; RUN: llc -O0 -mtriple=powerpc64-ibm-aix-xcoff -mcpu=pwr10 -target-abi=vec-extabi -stop-after=prolog-epilog -verify-machineinstrs < %s | \ ; RUN: FileCheck --check-prefix=CHECK-VEXT %s ; CHECK-LABEL: name: foo diff --git a/llvm/test/CodeGen/PowerPC/aix64-vector-vararg-callee.ll b/llvm/test/CodeGen/PowerPC/aix64-vector-vararg-callee.ll index 434f35f33a902..d1c7f0d0e0eb2 100644 --- a/llvm/test/CodeGen/PowerPC/aix64-vector-vararg-callee.ll +++ b/llvm/test/CodeGen/PowerPC/aix64-vector-vararg-callee.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -; RUN: llc -verify-machineinstrs -stop-before=ppc-vsx-copy -vec-extabi \ +; RUN: llc -verify-machineinstrs -stop-before=ppc-vsx-copy -target-abi=vec-extabi \ ; RUN: -mcpu=pwr7 -mtriple powerpc64-ibm-aix-xcoff < %s | \ ; RUN: FileCheck %s diff --git a/llvm/test/CodeGen/PowerPC/aix64-vector-vararg-fixed-callee.ll b/llvm/test/CodeGen/PowerPC/aix64-vector-vararg-fixed-callee.ll index 63b9f5cc6bdf6..59eb45dea9507 100644 --- a/llvm/test/CodeGen/PowerPC/aix64-vector-vararg-fixed-callee.ll +++ b/llvm/test/CodeGen/PowerPC/aix64-vector-vararg-fixed-callee.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -; RUN: llc -verify-machineinstrs -stop-before=ppc-vsx-copy -vec-extabi \ +; RUN: llc -verify-machineinstrs -stop-before=ppc-vsx-copy -target-abi=vec-extabi \ ; RUN: -mcpu=pwr7 -mtriple powerpc64-ibm-aix-xcoff < %s | \ ; RUN: FileCheck %s diff --git a/llvm/test/CodeGen/PowerPC/aix64-virtual-call-no-spills.ll b/llvm/test/CodeGen/PowerPC/aix64-virtual-call-no-spills.ll index a314dd4f069d8..162c45ccf8d9a 100644 --- a/llvm/test/CodeGen/PowerPC/aix64-virtual-call-no-spills.ll +++ b/llvm/test/CodeGen/PowerPC/aix64-virtual-call-no-spills.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -O0 -mtriple=powerpc64-ibm-aix-xcoff -mcpu=pwr10 < %s | \ ; RUN: FileCheck --check-prefix=CHECK %s -; RUN: llc -O0 -mtriple=powerpc64-ibm-aix-xcoff -mcpu=pwr10 -vec-extabi < %s | \ +; RUN: llc -O0 -mtriple=powerpc64-ibm-aix-xcoff -mcpu=pwr10 -target-abi=vec-extabi < %s | \ ; RUN: FileCheck --check-prefix=CHECK-VEXT %s define dso_local noundef signext i32 @virtualCall(ptr noundef %b) #0 { diff --git a/llvm/test/CodeGen/PowerPC/bswap64.ll b/llvm/test/CodeGen/PowerPC/bswap64.ll index b16c9b434b0fd..753418b51b88b 100644 --- a/llvm/test/CodeGen/PowerPC/bswap64.ll +++ b/llvm/test/CodeGen/PowerPC/bswap64.ll @@ -6,7 +6,7 @@ ; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-unknown \ ; RUN: -mcpu=pwr9 | FileCheck %s --check-prefix=POWER-9 ; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-ibm-aix-xcoff \ -; RUN: -mcpu=pwr9 -vec-extabi | FileCheck %s --check-prefix=POWER-9 +; RUN: -mcpu=pwr9 -target-abi=vec-extabi | FileCheck %s --check-prefix=POWER-9 ; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-unknown \ ; RUN: -mcpu=pwr9 -mattr=-altivec | FileCheck %s --check-prefix=POWER-9-NO-ALTIVEC ; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-ibm-aix-xcoff \ diff --git a/llvm/test/CodeGen/PowerPC/builtins-ppc-p9-darn.ll b/llvm/test/CodeGen/PowerPC/builtins-ppc-p9-darn.ll index 1d508bd653609..27b8d5d342db5 100644 --- a/llvm/test/CodeGen/PowerPC/builtins-ppc-p9-darn.ll +++ b/llvm/test/CodeGen/PowerPC/builtins-ppc-p9-darn.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc < %s -verify-machineinstrs -mtriple powerpc64le -mcpu=pwr9 | FileCheck %s -; RUN: llc < %s -verify-machineinstrs -mtriple powerpc64-ibm-aix-xcoff -vec-extabi -mcpu=pwr9 | FileCheck %s +; RUN: llc < %s -verify-machineinstrs -mtriple powerpc64-ibm-aix-xcoff -target-abi=vec-extabi -mcpu=pwr9 | FileCheck %s ; RUN: opt < %s -passes="default<O3>" -S -mtriple powerpc64le -mcpu=pwr9 | FileCheck %s --check-prefix=OPT define i64 @raw() { diff --git a/llvm/test/CodeGen/PowerPC/cannonicalize-vector-shifts.ll b/llvm/test/CodeGen/PowerPC/cannonicalize-vector-shifts.ll index b0fbc16e1b812..e55f41f6b6cb9 100644 --- a/llvm/test/CodeGen/PowerPC/cannonicalize-vector-shifts.ll +++ b/llvm/test/CodeGen/PowerPC/cannonicalize-vector-shifts.ll @@ -3,9 +3,9 @@ ; RUN: llc -mcpu=pwr8 -mtriple=powerpc64-unknown-linux-gnu \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mcpu=pwr8 -vec-extabi -mtriple=powerpc64-ibm-aix-xcoff \ +; RUN: llc -mcpu=pwr8 -target-abi=vec-extabi -mtriple=powerpc64-ibm-aix-xcoff \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mcpu=pwr8 -vec-extabi -mtriple=powerpc-ibm-aix-xcoff \ +; RUN: llc -mcpu=pwr8 -target-abi=vec-extabi -mtriple=powerpc-ibm-aix-xcoff \ ; RUN: -verify-machineinstrs < %s | FileCheck %s define <4 x i32> @test1(<4 x i32> %a) { diff --git a/llvm/test/CodeGen/PowerPC/cmpb-ppc32.ll b/llvm/test/CodeGen/PowerPC/cmpb-ppc32.ll index af2904cad806c..9299b06569086 100644 --- a/llvm/test/CodeGen/PowerPC/cmpb-ppc32.ll +++ b/llvm/test/CodeGen/PowerPC/cmpb-ppc32.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs -mtriple powerpc-unknown-linux-gnu -mcpu=pwr7 < %s | FileCheck %s -; RUN: llc -verify-machineinstrs -mtriple powerpc-ibm-aix-xcoff -mcpu=pwr7 -vec-extabi < %s | FileCheck %s +; RUN: llc -verify-machineinstrs -mtriple powerpc-ibm-aix-xcoff -mcpu=pwr7 -target-abi=vec-extabi < %s | FileCheck %s ; Function Attrs: nounwind readnone define zeroext i16 @test16(i16 zeroext %x, i16 zeroext %y) #0 { diff --git a/llvm/test/CodeGen/PowerPC/cmpb.ll b/llvm/test/CodeGen/PowerPC/cmpb.ll index f32448023e712..c14d16fd7be0d 100644 --- a/llvm/test/CodeGen/PowerPC/cmpb.ll +++ b/llvm/test/CodeGen/PowerPC/cmpb.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs -mtriple powerpc64-unknown-linux-gnu -mcpu pwr7 < %s | FileCheck %s -; RUN: llc -verify-machineinstrs -mtriple powerpc64-ibm-aix-xcoff -mcpu pwr7 -vec-extabi < %s | FileCheck %s +; RUN: llc -verify-machineinstrs -mtriple powerpc64-ibm-aix-xcoff -mcpu pwr7 -target-abi=vec-extabi < %s | FileCheck %s ; Function Attrs: nounwind readnone define zeroext i16 @test16(i16 zeroext %x, i16 zeroext %y) #0 { diff --git a/llvm/test/CodeGen/PowerPC/constants-i64.ll b/llvm/test/CodeGen/PowerPC/constants-i64.ll index 0d7343d7572a4..0f7e4f0e94451 100644 --- a/llvm/test/CodeGen/PowerPC/constants-i64.ll +++ b/llvm/test/CodeGen/PowerPC/constants-i64.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs -mtriple powerpc64-unknown-linux-gnu -mcpu=ppc64 < %s | FileCheck %s -; RUN: llc -verify-machineinstrs -mtriple powerpc64-ibm-aix-xcoff -vec-extabi -mcpu=ppc64 < %s | FileCheck %s +; RUN: llc -verify-machineinstrs -mtriple powerpc64-ibm-aix-xcoff -target-abi=vec-extabi -mcpu=ppc64 < %s | FileCheck %s ; Function Attrs: nounwind readnone define i64 @cn1() #0 { diff --git a/llvm/test/CodeGen/PowerPC/fdiv.ll b/llvm/test/CodeGen/PowerPC/fdiv.ll index 3ea28ec73c2ac..2072e357f16da 100644 --- a/llvm/test/CodeGen/PowerPC/fdiv.ll +++ b/llvm/test/CodeGen/PowerPC/fdiv.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 | FileCheck %s -; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-ibm-aix-xcoff -mcpu=pwr8 -vec-extabi | FileCheck %s +; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-ibm-aix-xcoff -mcpu=pwr8 -target-abi=vec-extabi | FileCheck %s define dso_local float @foo_nosw(float %0, float %1) local_unnamed_addr { ; CHECK-LABEL: foo_nosw: diff --git a/llvm/test/CodeGen/PowerPC/fma-assoc.ll b/llvm/test/CodeGen/PowerPC/fma-assoc.ll index c2004f79219c0..8a3d5deaf3069 100644 --- a/llvm/test/CodeGen/PowerPC/fma-assoc.ll +++ b/llvm/test/CodeGen/PowerPC/fma-assoc.ll @@ -8,7 +8,7 @@ ; RUN: -mcpu=pwr7 | FileCheck -check-prefix=CHECK-VSX %s ; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-ibm-aix-xcoff \ ; RUN: -mattr=+vsx -disable-ppc-vsx-fma-mutation=false \ -; RUN: -mcpu=pwr7 -vec-extabi | FileCheck -check-prefix=CHECK-VSX %s +; RUN: -mcpu=pwr7 -target-abi=vec-extabi | FileCheck -check-prefix=CHECK-VSX %s ; RUN: llc -verify-machineinstrs < %s -mtriple=powerpcspe-linux-unknown-gnu \ ; RUN: | FileCheck -check-prefix=CHECK-SPE %s diff --git a/llvm/test/CodeGen/PowerPC/ftrunc-vec.ll b/llvm/test/CodeGen/PowerPC/ftrunc-vec.ll index b0faf1430b8fa..93d17ed87d0f7 100644 --- a/llvm/test/CodeGen/PowerPC/ftrunc-vec.ll +++ b/llvm/test/CodeGen/PowerPC/ftrunc-vec.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mcpu=pwr8 -mtriple=powerpc64le-unknown-unknown -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mcpu=pwr8 -mtriple=powerpc64-ibm-aix-xcoff -vec-extabi -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mcpu=pwr8 -mtriple=powerpc64-ibm-aix-xcoff -target-abi=vec-extabi -verify-machineinstrs < %s | FileCheck %s define <4 x float> @truncf32(<4 x float> %a) { ; CHECK-LABEL: truncf32: diff --git a/llvm/test/CodeGen/PowerPC/gpr-vsr-spill.ll b/llvm/test/CodeGen/PowerPC/gpr-vsr-spill.ll index 396a7e6c065a1..6f17e65a917e6 100644 --- a/llvm/test/CodeGen/PowerPC/gpr-vsr-spill.ll +++ b/llvm/test/CodeGen/PowerPC/gpr-vsr-spill.ll @@ -1,5 +1,5 @@ ; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu -ppc-enable-gpr-to-vsr-spills < %s | FileCheck %s -; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc64-ibm-aix-xcoff -ppc-enable-gpr-to-vsr-spills -vec-extabi < %s | FileCheck %s +; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc64-ibm-aix-xcoff -ppc-enable-gpr-to-vsr-spills -target-abi=vec-extabi < %s | FileCheck %s define signext i32 @foo(i32 signext %a, i32 signext %b) { entry: diff --git a/llvm/test/CodeGen/PowerPC/maddld.ll b/llvm/test/CodeGen/PowerPC/maddld.ll index 613f8fb55bdf4..fa6c97001f58d 100644 --- a/llvm/test/CodeGen/PowerPC/maddld.ll +++ b/llvm/test/CodeGen/PowerPC/maddld.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s --check-prefix=CHECK-P9 ; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s --check-prefix=CHECK-P8 -; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64-ibm-aix-xcoff -vec-extabi < %s | FileCheck %s --check-prefix=CHECK-P8 +; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64-ibm-aix-xcoff -target-abi=vec-extabi < %s | FileCheck %s --check-prefix=CHECK-P8 define signext i64 @maddld64(i64 signext %a, i64 signext %b) { ; CHECK-P9-LABEL: maddld64: diff --git a/llvm/test/CodeGen/PowerPC/mi-peephole-splat.ll b/llvm/test/CodeGen/PowerPC/mi-peephole-splat.ll index 04de67ee609f9..840c3080ded96 100644 --- a/llvm/test/CodeGen/PowerPC/mi-peephole-splat.ll +++ b/llvm/test/CodeGen/PowerPC/mi-peephole-splat.ll @@ -4,13 +4,13 @@ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-linux-gnu -mattr=+vsx < %s \ ; RUN: | FileCheck --check-prefix=CHECK-BE %s ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-ibm-aix-xcoff -mattr=+vsx \ -; RUN: -vec-extabi < %s | FileCheck --check-prefix=CHECK-BE %s +; RUN: -target-abi=vec-extabi < %s | FileCheck --check-prefix=CHECK-BE %s ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-linux-gnu -mcpu=pwr9 < %s \ ; RUN: | FileCheck --check-prefix=CHECK-P9LE %s ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-linux-gnu -mcpu=pwr9 < %s \ ; RUN: | FileCheck --check-prefix=CHECK-P9BE %s ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-ibm-aix-xcoff -mcpu=pwr9 \ -; RUN: -vec-extabi < %s | FileCheck --check-prefix=CHECK-BE %s +; RUN: -target-abi=vec-extabi < %s | FileCheck --check-prefix=CHECK-BE %s define double @splat_swap(<2 x double> %x, <2 x double> %y) nounwind { ; CHECK-LE-LABEL: splat_swap: diff --git a/llvm/test/CodeGen/PowerPC/mmaplus-intrinsics.ll b/llvm/test/CodeGen/PowerPC/mmaplus-intrinsics.ll index 7ff1bc17b77c3..ff74352553ad0 100644 --- a/llvm/test/CodeGen/PowerPC/mmaplus-intrinsics.ll +++ b/llvm/test/CodeGen/PowerPC/mmaplus-intrinsics.ll @@ -13,10 +13,10 @@ ; RUN: -mcpu=future -ppc-asm-full-reg-names \ ; RUN: -ppc-vsr-nums-as-vr -O0 < %s | FileCheck %s --check-prefix=CHECK-O0-BE ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-aix- \ -; RUN: -mcpu=future -vec-extabi \ +; RUN: -mcpu=future -target-abi=vec-extabi \ ; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=CHECK-AIX64 ; RUN: llc -verify-machineinstrs -mtriple=powerpc-aix- \ -; RUN: -mcpu=future -vec-extabi \ +; RUN: -mcpu=future -target-abi=vec-extabi \ ; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=CHECK-AIX32 ; TODO: This test is missing some of the tests from mma-intrinsics.ll because diff --git a/llvm/test/CodeGen/PowerPC/mulli.ll b/llvm/test/CodeGen/PowerPC/mulli.ll index ead4dd2e07cbe..843abce2a2062 100644 --- a/llvm/test/CodeGen/PowerPC/mulli.ll +++ b/llvm/test/CodeGen/PowerPC/mulli.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s -; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc64-ibm-aix-xcoff -vec-extabi < %s | FileCheck %s +; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc64-ibm-aix-xcoff -target-abi=vec-extabi < %s | FileCheck %s define i64 @test1(i64 %x) { ; CHECK-LABEL: test1: diff --git a/llvm/test/CodeGen/PowerPC/p10-handle-split-promote-vec.ll b/llvm/test/CodeGen/PowerPC/p10-handle-split-promote-vec.ll index 393fc872a35e0..1100c6d022066 100644 --- a/llvm/test/CodeGen/PowerPC/p10-handle-split-promote-vec.ll +++ b/llvm/test/CodeGen/PowerPC/p10-handle-split-promote-vec.ll @@ -2,7 +2,7 @@ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \ ; RUN: < %s | FileCheck %s -; RUN: llc -verify-machineinstrs -mtriple=powerpc64-ibm-aix --code-model=small -vec-extabi \ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-ibm-aix --code-model=small -target-abi=vec-extabi \ ; RUN: -mcpu=pwr10 < %s | FileCheck %s -check-prefix=CHECK-AIX define i32 @SplitPromoteVectorTest(i32 %Opc) align 2 { diff --git a/llvm/test/CodeGen/PowerPC/p8-scalar_vector_conversions.ll b/llvm/test/CodeGen/PowerPC/p8-scalar_vector_conversions.ll index 523be8321d425..75e051a99a1ce 100644 --- a/llvm/test/CodeGen/PowerPC/p8-scalar_vector_conversions.ll +++ b/llvm/test/CodeGen/PowerPC/p8-scalar_vector_conversions.ll @@ -5,7 +5,7 @@ ; RUN: llc < %s -ppc-vsr-nums-as-vr -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: -verify-machineinstrs -ppc-asm-full-reg-names -mcpu=pwr8 -relocation-model=pic \ ; RUN: | FileCheck %s -check-prefix=CHECK-LE -; RUN: llc < %s -vec-extabi -mtriple=powerpc64-ibm-aix-xcoff --code-model=small \ +; RUN: llc < %s -target-abi=vec-extabi -mtriple=powerpc64-ibm-aix-xcoff --code-model=small \ ; RUN: -verify-machineinstrs -mcpu=pwr8 \ ; RUN: | FileCheck %s -check-prefix=CHECK-AIX diff --git a/llvm/test/CodeGen/PowerPC/ppc64-rop-protection-aix.ll b/llvm/test/CodeGen/PowerPC/ppc64-rop-protection-aix.ll index 97187389a9d0b..5fa38d255dd29 100644 --- a/llvm/test/CodeGen/PowerPC/ppc64-rop-protection-aix.ll +++ b/llvm/test/CodeGen/PowerPC/ppc64-rop-protection-aix.ll @@ -1,39 +1,39 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-ibm-aix-xcoff \ -; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr -vec-extabi \ +; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr -target-abi=vec-extabi \ ; RUN: -mattr=+rop-protect < %s | FileCheck %s --check-prefix BE-P10 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-ibm-aix-xcoff \ -; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr -vec-extabi \ +; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr -target-abi=vec-extabi \ ; RUN: -mattr=+rop-protect < %s | FileCheck %s --check-prefix BE-P9 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-ibm-aix-xcoff \ -; RUN: -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr -vec-extabi \ +; RUN: -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr -target-abi=vec-extabi \ ; RUN: -mattr=+rop-protect < %s | FileCheck %s --check-prefix BE-P8 ; RUN: llc -verify-machineinstrs -mtriple=powerpc-ibm-aix-xcoff \ -; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr -vec-extabi \ +; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr -target-abi=vec-extabi \ ; RUN: -mattr=+rop-protect < %s | FileCheck %s --check-prefix BE-32BIT-P10 ; RUN: llc -verify-machineinstrs -mtriple=powerpc-ibm-aix-xcoff \ -; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr -vec-extabi \ +; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr -target-abi=vec-extabi \ ; RUN: -mattr=+rop-protect < %s | FileCheck %s --check-prefix BE-32BIT-P9 ; RUN: llc -verify-machineinstrs -mtriple=powerpc-ibm-aix-xcoff \ -; RUN: -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr -vec-extabi \ +; RUN: -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr -target-abi=vec-extabi \ ; RUN: -mattr=+rop-protect < %s | FileCheck %s --check-prefix BE-32BIT-P8 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-ibm-aix-xcoff \ -; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr -vec-extabi \ +; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr -target-abi=vec-extabi \ ; RUN: -mattr=+rop-protect -mattr=+privileged < %s | FileCheck %s --check-prefix BE-P10-PRIV ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-ibm-aix-xcoff \ -; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr -vec-extabi \ +; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr -target-abi=vec-extabi \ ; RUN: -mattr=+rop-protect -mattr=+privileged < %s | FileCheck %s --check-prefix BE-P9-PRIV ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-ibm-aix-xcoff \ -; RUN: -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr -vec-extabi \ +; RUN: -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr -target-abi=vec-extabi \ ; RUN: -mattr=+rop-protect -mattr=+privileged < %s | FileCheck %s --check-prefix BE-P8-PRIV ; RUN: llc -verify-machineinstrs -mtriple=powerpc-ibm-aix-xcoff \ -; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr -vec-extabi \ +; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr -target-abi=vec-extabi \ ; RUN: -mattr=+rop-protect -mattr=+privileged < %s | FileCheck %s --check-prefix BE-32BIT-P10-PRIV ; RUN: llc -verify-machineinstrs -mtriple=powerpc-ibm-aix-xcoff \ -; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr -vec-extabi \ +; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr -target-abi=vec-extabi \ ; RUN: -mattr=+rop-protect -mattr=+privileged < %s | FileCheck %s --check-prefix BE-32BIT-P9-PRIV ; RUN: llc -verify-machineinstrs -mtriple=powerpc-ibm-aix-xcoff \ -; RUN: -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr -vec-extabi \ +; RUN: -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr -target-abi=vec-extabi \ ; RUN: -mattr=+rop-protect -mattr=+privileged < %s | FileCheck %s --check-prefix BE-32BIT-P8-PRIV diff --git a/llvm/test/CodeGen/PowerPC/pr33093.ll b/llvm/test/CodeGen/PowerPC/pr33093.ll index 4992ae287b5a6..9f84ef88b28a5 100644 --- a/llvm/test/CodeGen/PowerPC/pr33093.ll +++ b/llvm/test/CodeGen/PowerPC/pr33093.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s ; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s -; RUN: llc -mtriple=powerpc64-ibm-aix-xcoff -mcpu=pwr8 -vec-extabi < %s | FileCheck %s +; RUN: llc -mtriple=powerpc64-ibm-aix-xcoff -mcpu=pwr8 -target-abi=vec-extabi < %s | FileCheck %s define zeroext i32 @ReverseBits(i32 zeroext %n) { ; CHECK-LABEL: ReverseBits: diff --git a/llvm/test/CodeGen/PowerPC/pre-inc-disable.ll b/llvm/test/CodeGen/PowerPC/pre-inc-disable.ll index a7eb0a6be0e71..b7aecc8d2dece 100644 --- a/llvm/test/CodeGen/PowerPC/pre-inc-disable.ll +++ b/llvm/test/CodeGen/PowerPC/pre-inc-disable.ll @@ -8,11 +8,11 @@ ; RUN: < %s | FileCheck %s --check-prefixes=P9BE ; RUN: llc -mcpu=pwr9 -O3 -verify-machineinstrs -ppc-vsr-nums-as-vr \ -; RUN: -mtriple=powerpc64-ibm-aix-xcoff --code-model=small -vec-extabi \ +; RUN: -mtriple=powerpc64-ibm-aix-xcoff --code-model=small -target-abi=vec-extabi \ ; RUN: < %s | FileCheck %s --check-prefixes=P9BE-AIX ; RUN: llc -mcpu=pwr9 -O3 -verify-machineinstrs -ppc-vsr-nums-as-vr \ -; RUN: -mtriple=powerpc-ibm-aix-xcoff -vec-extabi \ +; RUN: -mtriple=powerpc-ibm-aix-xcoff -target-abi=vec-extabi \ ; RUN: < %s | FileCheck %s --check-prefixes=P9BE-AIX32 define void @test64(ptr nocapture readonly %pix2, i32 signext %i_pix2) { diff --git a/llvm/test/CodeGen/PowerPC/setcc-to-sub.ll b/llvm/test/CodeGen/PowerPC/setcc-to-sub.ll index 20dcb8ccf4908..0308063d29e57 100644 --- a/llvm/test/CodeGen/PowerPC/setcc-to-sub.ll +++ b/llvm/test/CodeGen/PowerPC/setcc-to-sub.ll @@ -2,7 +2,7 @@ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: -mcpu=pwr8 < %s | FileCheck %s ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-ibm-aix-xcoff -mcpu=pwr8 \ -; RUN: < %s -vec-extabi | FileCheck %s +; RUN: < %s -target-abi=vec-extabi | FileCheck %s %class.PB2 = type { [1 x i32], ptr } %class.PB1 = type { [1 x i32], i64, i64, i32 } diff --git a/llvm/test/CodeGen/PowerPC/unal-vec-ldst.ll b/llvm/test/CodeGen/PowerPC/unal-vec-ldst.ll index b0ed395fc3a19..c7da322305db8 100644 --- a/llvm/test/CodeGen/PowerPC/unal-vec-ldst.ll +++ b/llvm/test/CodeGen/PowerPC/unal-vec-ldst.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple powerpc64-unknown-linux-gnu -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -verify-machineinstrs -vec-extabi < %s | FileCheck %s +; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -verify-machineinstrs -target-abi=vec-extabi < %s | FileCheck %s define <16 x i8> @test_l_v16i8(ptr %p) #0 { ; CHECK-LABEL: test_l_v16i8: diff --git a/llvm/test/CodeGen/PowerPC/vec-bswap.ll b/llvm/test/CodeGen/PowerPC/vec-bswap.ll index 27f750de96c6c..1a78481c39202 100644 --- a/llvm/test/CodeGen/PowerPC/vec-bswap.ll +++ b/llvm/test/CodeGen/PowerPC/vec-bswap.ll @@ -2,10 +2,10 @@ ; RUN: -verify-machineinstrs -ppc-asm-full-reg-names | FileCheck %s ; RUN: llc < %s -mtriple=powerpc64-ibm-aix-xcoff -mcpu=pwr9 \ -; RUN: -verify-machineinstrs -vec-extabi | \ +; RUN: -verify-machineinstrs -target-abi=vec-extabi | \ ; RUN: FileCheck %s --check-prefixes=AIX,AIX64 ; RUN: llc < %s -mtriple=powerpc-ibm-aix-xcoff -mcpu=pwr9 \ -; RUN: -verify-machineinstrs -vec-extabi | \ +; RUN: -verify-machineinstrs -target-abi=vec-extabi | \ ; RUN: FileCheck %s --check-prefixes=AIX,AIX32 define dso_local void @test(ptr %Arr, i32 signext %Len) { diff --git a/llvm/test/CodeGen/PowerPC/vec_clz.ll b/llvm/test/CodeGen/PowerPC/vec_clz.ll index da2c330ad92dd..514d5de029e8a 100644 --- a/llvm/test/CodeGen/PowerPC/vec_clz.ll +++ b/llvm/test/CodeGen/PowerPC/vec_clz.ll @@ -1,9 +1,9 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; Check the vctlz* instructions that were added in P8 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s -; RUN: llc -verify-machineinstrs -mtriple=powerpc64-ibm-aix-xcoff -vec-extabi -mcpu=pwr8 < %s | FileCheck %s +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-ibm-aix-xcoff -target-abi=vec-extabi -mcpu=pwr8 < %s | FileCheck %s ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s --check-prefix=CHECK-NOVSX -; RUN: llc -verify-machineinstrs -mtriple=powerpc64-ibm-aix-xcoff -vec-extabi -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s --check-prefix=CHECK-NOVSX +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-ibm-aix-xcoff -target-abi=vec-extabi -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s --check-prefix=CHECK-NOVSX declare <16 x i8> @llvm.ctlz.v16i8(<16 x i8>) nounwind readnone declare <8 x i16> @llvm.ctlz.v8i16(<8 x i16>) nounwind readnone diff --git a/llvm/test/CodeGen/PowerPC/vec_constants.ll b/llvm/test/CodeGen/PowerPC/vec_constants.ll index 07eae4cc3c1f8..07aa4b0670ecb 100644 --- a/llvm/test/CodeGen/PowerPC/vec_constants.ll +++ b/llvm/test/CodeGen/PowerPC/vec_constants.ll @@ -1,10 +1,10 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs -O0 -mcpu=pwr7 -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s --check-prefixes=CHECK,BE -; RUN: llc -verify-machineinstrs -O0 -mcpu=pwr7 -mtriple=powerpc64-ibm-aix-xcoff -vec-extabi < %s | FileCheck %s --check-prefixes=CHECK,BE +; RUN: llc -verify-machineinstrs -O0 -mcpu=pwr7 -mtriple=powerpc64-ibm-aix-xcoff -target-abi=vec-extabi < %s | FileCheck %s --check-prefixes=CHECK,BE ; RUN: llc -verify-machineinstrs -O0 -mcpu=pwr7 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s --check-prefixes=CHECK,LE ; RUN: llc -verify-machineinstrs -O0 -mcpu=pwr7 -mtriple=powerpc64-unknown-linux-gnu -use-constant-int-for-fixed-length-splat < %s | FileCheck %s --check-prefixes=CHECK,BE -; RUN: llc -verify-machineinstrs -O0 -mcpu=pwr7 -mtriple=powerpc64-ibm-aix-xcoff -vec-extabi -use-constant-int-for-fixed-length-splat < %s | FileCheck %s --check-prefixes=CHECK,BE +; RUN: llc -verify-machineinstrs -O0 -mcpu=pwr7 -mtriple=powerpc64-ibm-aix-xcoff -target-abi=vec-extabi -use-constant-int-for-fixed-length-splat < %s | FileCheck %s --check-prefixes=CHECK,BE ; RUN: llc -verify-machineinstrs -O0 -mcpu=pwr7 -mtriple=powerpc64le-unknown-linux-gnu -use-constant-int-for-fixed-length-splat < %s | FileCheck %s --check-prefixes=CHECK,LE define void @test1(ptr %P1, ptr %P2, ptr %P3) nounwind { diff --git a/llvm/test/CodeGen/PowerPC/vec_revb.ll b/llvm/test/CodeGen/PowerPC/vec_revb.ll index d68d91d922d6b..4a48b1ddc6d1c 100644 --- a/llvm/test/CodeGen/PowerPC/vec_revb.ll +++ b/llvm/test/CodeGen/PowerPC/vec_revb.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr9 < %s | FileCheck %s -; RUN: llc -verify-machineinstrs -mtriple=powerpc64-ibm-aix-xcoff -vec-extabi -mcpu=pwr9 < %s | FileCheck %s +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-ibm-aix-xcoff -target-abi=vec-extabi -mcpu=pwr9 < %s | FileCheck %s ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 < %s | FileCheck %s define <8 x i16> @testXXBRH(<8 x i16> %a) { diff --git a/llvm/test/CodeGen/PowerPC/vec_shuffle_p8vector.ll b/llvm/test/CodeGen/PowerPC/vec_shuffle_p8vector.ll index eb07a299a1c10..f7c2e21dffe2a 100644 --- a/llvm/test/CodeGen/PowerPC/vec_shuffle_p8vector.ll +++ b/llvm/test/CodeGen/PowerPC/vec_shuffle_p8vector.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64-unknown-linux-gnu -mattr=+power8-vector < %s | FileCheck %s -; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64-ibm-aix-xcoff --code-model=small -vec-extabi -mattr=+power8-vector < %s | FileCheck %s +; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64-ibm-aix-xcoff --code-model=small -target-abi=vec-extabi -mattr=+power8-vector < %s | FileCheck %s ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck -check-prefix=CHECK-PWR7 %s -; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple=powerpc64-ibm-aix-xcoff --code-model=small -vec-extabi < %s | FileCheck -check-prefix=CHECK-PWR7-AIX %s +; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple=powerpc64-ibm-aix-xcoff --code-model=small -target-abi=vec-extabi < %s | FileCheck -check-prefix=CHECK-PWR7-AIX %s define void @VPKUDUM_unary(ptr %A) { ; CHECK-LABEL: VPKUDUM_unary: diff --git a/llvm/test/CodeGen/PowerPC/vmladduhm.ll b/llvm/test/CodeGen/PowerPC/vmladduhm.ll index cbec43961c03c..b5faae5da3be8 100644 --- a/llvm/test/CodeGen/PowerPC/vmladduhm.ll +++ b/llvm/test/CodeGen/PowerPC/vmladduhm.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s -; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc64-ibm-aix-xcoff -vec-extabi < %s | FileCheck %s +; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc64-ibm-aix-xcoff -target-abi=vec-extabi < %s | FileCheck %s ; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s -; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64-ibm-aix-xcoff -vec-extabi < %s | FileCheck %s +; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64-ibm-aix-xcoff -target-abi=vec-extabi < %s | FileCheck %s define <8 x i16> @mul(<8 x i16> %m, <8 x i16> %n) { ; CHECK-LABEL: mul: ; CHECK: # %bb.0: # %entry diff --git a/llvm/test/CodeGen/PowerPC/xxpermdi_mnemonics.s b/llvm/test/CodeGen/PowerPC/xxpermdi_mnemonics.s index ec2e2646de8fd..def02b1ca83cf 100644 --- a/llvm/test/CodeGen/PowerPC/xxpermdi_mnemonics.s +++ b/llvm/test/CodeGen/PowerPC/xxpermdi_mnemonics.s @@ -1,9 +1,9 @@ -; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -mcpu=pwr8 --vec-extabi < %s | FileCheck --check-prefixes=CHECK,OLD %s -; RUN: llc -mtriple powerpc-ibm-aix-xcoff -mcpu=pwr8 --vec-extabi < %s | FileCheck --check-prefixes=CHECK,OLD %s +; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -mcpu=pwr8 -target-abi=vec-extabi < %s | FileCheck --check-prefixes=CHECK,OLD %s +; RUN: llc -mtriple powerpc-ibm-aix-xcoff -mcpu=pwr8 -target-abi=vec-extabi < %s | FileCheck --check-prefixes=CHECK,OLD %s ; RUN: llc -mtriple powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck --check-prefixes=CHECK,MODERN %s -; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -mcpu=pwr8 -mattr=+modern-aix-as --vec-extabi < %s | FileCheck --check-prefixes=CHECK,MODERN %s -; RUN: llc -mtriple powerpc-ibm-aix-xcoff -mcpu=pwr8 -mattr=+modern-aix-as --vec-extabi < %s | FileCheck --check-prefixes=CHECK,MODERN %s +; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -mcpu=pwr8 -mattr=+modern-aix-as -target-abi=vec-extabi < %s | FileCheck --check-prefixes=CHECK,MODERN %s +; RUN: llc -mtriple powerpc-ibm-aix-xcoff -mcpu=pwr8 -mattr=+modern-aix-as -target-abi=vec-extabi < %s | FileCheck --check-prefixes=CHECK,MODERN %s define <2 x double> @splat1(<2 x double> %A, <2 x double> %B) { entry: diff --git a/llvm/test/Transforms/LoopVectorize/PowerPC/massv-calls.ll b/llvm/test/Transforms/LoopVectorize/PowerPC/massv-calls.ll index 9ea453287b0a4..5ef21779de98a 100644 --- a/llvm/test/Transforms/LoopVectorize/PowerPC/massv-calls.ll +++ b/llvm/test/Transforms/LoopVectorize/PowerPC/massv-calls.ll @@ -1,5 +1,5 @@ ; RUN: opt -vector-library=MASSV -mtriple=powerpc64le-unknown-linux-gnu -passes=inject-tli-mappings,loop-vectorize -force-vector-interleave=1 -S < %s | FileCheck %s -; RUN: opt -vector-library=MASSV -vec-extabi -mattr=+altivec -mcpu=ppc64 -mtriple=powerpc64-ibm-aix-xcoff -passes=inject-tli-mappings,loop-vectorize -force-vector-interleave=1 -S < %s | FileCheck %s +; RUN: opt -vector-library=MASSV -target-abi=vec-extabi -mattr=+altivec -mcpu=ppc64 -mtriple=powerpc64-ibm-aix-xcoff -passes=inject-tli-mappings,loop-vectorize -force-vector-interleave=1 -S < %s | FileCheck %s declare double @cbrt(double) declare float @cbrtf(float) diff --git a/llvm/test/Transforms/PGOProfile/ppc-prevent-mma-types.ll b/llvm/test/Transforms/PGOProfile/ppc-prevent-mma-types.ll index 2cfeb2e8faf52..e0dae53379392 100644 --- a/llvm/test/Transforms/PGOProfile/ppc-prevent-mma-types.ll +++ b/llvm/test/Transforms/PGOProfile/ppc-prevent-mma-types.ll @@ -1,4 +1,4 @@ -; RUN: opt --vec-extabi=true -passes='default<O3>' -mcpu=pwr10 \ +; RUN: opt -target-abi=vec-extabi -passes='default<O3>' -mcpu=pwr10 \ ; RUN: -pgo-kind=pgo-instr-gen-pipeline -mtriple=powerpc-ibm-aix -S < %s | \ ; RUN: FileCheck %s ; RUN: opt -passes='default<O3>' -mcpu=pwr10 -pgo-kind=pgo-instr-gen-pipeline \ _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
