Author: beetrees Date: 2026-09-19T22:07:17Z New Revision: 4b19252104764e9e2ccd25c545eb6b99309a2444
URL: https://github.com/llvm/llvm-project/commit/4b19252104764e9e2ccd25c545eb6b99309a2444 DIFF: https://github.com/llvm/llvm-project/commit/4b19252104764e9e2ccd25c545eb6b99309a2444.diff LOG: Fix `fp128` reaching `llvm_unreachable` on 32-bit PowerPC (#216613) `fp128` is a legal type that is passed in vector registers when `vsx` is enabled on 32-bit PowerPC: the switch statement didn't account for that, causing an LLVM assertion. Fixes #213355 cc @folkertdev (cherry picked from commit 8d1b38f87103eb339224d1e6d397aad191f919e6) Added: llvm/test/CodeGen/PowerPC/ppc32-f128-abi.ll Modified: llvm/lib/Target/PowerPC/PPCISelLowering.cpp Removed: ################################################################################ diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index f6c844b6428ce..dc1bffd1cc8e1 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -4281,13 +4281,10 @@ SDValue PPCTargetLowering::LowerFormalArguments_32SVR4( case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: - RC = &PPC::VRRCRegClass; - break; case MVT::v4f32: - RC = &PPC::VRRCRegClass; - break; case MVT::v2f64: case MVT::v2i64: + case MVT::f128: RC = &PPC::VRRCRegClass; break; } diff --git a/llvm/test/CodeGen/PowerPC/ppc32-f128-abi.ll b/llvm/test/CodeGen/PowerPC/ppc32-f128-abi.ll new file mode 100644 index 0000000000000..967c39e551718 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/ppc32-f128-abi.ll @@ -0,0 +1,9 @@ +; RUN: llc -verify-machineinstrs -mattr=+vsx < %s | FileCheck %s +target triple = "powerpc-unknown-linux-gnu" + +; CHECK-LABEL: return_second: +; CHECK: vmr 2, 3 +; CHECK-NEXT: blr +define fp128 @return_second(fp128, fp128) { + ret fp128 %1 +} _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
