https://github.com/MrSidims updated https://github.com/llvm/llvm-project/pull/224910
>From e19c93b04ef40a732fbb95bbc82c6a26f44e5f09 Mon Sep 17 00:00:00 2001 From: Dmitry Sidorov <[email protected]> Date: Fri, 18 Sep 2026 17:39:52 +0200 Subject: [PATCH] [AMDGPU] Use a bf16 operand profile for v_fma_mix_bf16_t16 Assisted-by: Claude Code Opus 5 --- llvm/lib/Target/AMDGPU/VOP3PInstructions.td | 2 +- .../AMDGPU/mad-mix-bf16-t16-inline-imm.mir | 68 +++++++++++++++++++ 2 files changed, 69 insertions(+), 1 deletion(-) create mode 100644 llvm/test/CodeGen/AMDGPU/mad-mix-bf16-t16-inline-imm.mir diff --git a/llvm/lib/Target/AMDGPU/VOP3PInstructions.td b/llvm/lib/Target/AMDGPU/VOP3PInstructions.td index 714f7f7ece7b0..e9b6731b1623b 100644 --- a/llvm/lib/Target/AMDGPU/VOP3PInstructions.td +++ b/llvm/lib/Target/AMDGPU/VOP3PInstructions.td @@ -549,7 +549,7 @@ defm V_FMA_MIXHI_BF16 : VOP3_VOP3PInst<"v_fma_mixhi_bf16", VOP3P_Mix_Profile<VOP } // Pseudo true16 inst for v_fma_mixlo/hi_bf16 -defm V_FMA_MIX_BF16_t16 : VOP3_VOP3PInst_t16<"v_fma_mix_bf16_t16", VOP3P_Mix_Profile_t16<VOP_F16_F16_F16_F16, VOP3_OPSEL>>; +defm V_FMA_MIX_BF16_t16 : VOP3_VOP3PInst_t16<"v_fma_mix_bf16_t16", VOP3P_Mix_Profile_t16<VOP_BF16_BF16_BF16_BF16, VOP3_OPSEL>>; } // End FPDPRounding = 1 } // End isCommutable = 1 diff --git a/llvm/test/CodeGen/AMDGPU/mad-mix-bf16-t16-inline-imm.mir b/llvm/test/CodeGen/AMDGPU/mad-mix-bf16-t16-inline-imm.mir new file mode 100644 index 0000000000000..a6fd68df66b9b --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/mad-mix-bf16-t16-inline-imm.mir @@ -0,0 +1,68 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6 +# RUN: llc -mtriple=amdgpu12.50 -mattr=+real-true16 -run-pass=si-fold-operands -o - %s | FileCheck %s + +# Check that the bf16 encoding of 1.0 is recognized as an inline constant in +# each source of v_fma_mix_bf16_t16. + +--- +name: fold_bf16_one_into_src0 +tracksRegLiveness: true +body: | + bb.0: + liveins: $vgpr0, $vgpr1 + + ; CHECK-LABEL: name: fold_bf16_one_into_src0 + ; CHECK: liveins: $vgpr0, $vgpr1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; CHECK-NEXT: [[V_FMA_MIX_BF16_t16_:%[0-9]+]]:vgpr_16 = nofpexcept V_FMA_MIX_BF16_t16 4, 16256, 0, [[COPY]], 0, [[COPY1]], 0, 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: S_ENDPGM 0, implicit [[V_FMA_MIX_BF16_t16_]] + %0:vgpr_32 = COPY $vgpr0 + %1:vgpr_32 = COPY $vgpr1 + %2:sreg_32 = S_MOV_B32 16256 + %3:vgpr_16 = nofpexcept V_FMA_MIX_BF16_t16 0, %2, 0, %0, 0, %1, 0, 0, 0, implicit $mode, implicit $exec + S_ENDPGM 0, implicit %3 +... + +--- +name: fold_bf16_one_into_src1 +tracksRegLiveness: true +body: | + bb.0: + liveins: $vgpr0, $vgpr1 + + ; CHECK-LABEL: name: fold_bf16_one_into_src1 + ; CHECK: liveins: $vgpr0, $vgpr1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; CHECK-NEXT: [[V_FMA_MIX_BF16_t16_:%[0-9]+]]:vgpr_16 = nofpexcept V_FMA_MIX_BF16_t16 0, [[COPY]], 0, 16256, 0, [[COPY1]], 0, 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: S_ENDPGM 0, implicit [[V_FMA_MIX_BF16_t16_]] + %0:vgpr_32 = COPY $vgpr0 + %1:vgpr_32 = COPY $vgpr1 + %2:sreg_32 = S_MOV_B32 16256 + %3:vgpr_16 = nofpexcept V_FMA_MIX_BF16_t16 0, %0, 0, %2, 0, %1, 0, 0, 0, implicit $mode, implicit $exec + S_ENDPGM 0, implicit %3 +... + +--- +name: fold_bf16_one_into_src2 +tracksRegLiveness: true +body: | + bb.0: + liveins: $vgpr0, $vgpr1 + + ; CHECK-LABEL: name: fold_bf16_one_into_src2 + ; CHECK: liveins: $vgpr0, $vgpr1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; CHECK-NEXT: [[V_FMA_MIX_BF16_t16_:%[0-9]+]]:vgpr_16 = nofpexcept V_FMA_MIX_BF16_t16 0, [[COPY]], 0, [[COPY1]], 0, 16256, 0, 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: S_ENDPGM 0, implicit [[V_FMA_MIX_BF16_t16_]] + %0:vgpr_32 = COPY $vgpr0 + %1:vgpr_32 = COPY $vgpr1 + %2:sreg_32 = S_MOV_B32 16256 + %3:vgpr_16 = nofpexcept V_FMA_MIX_BF16_t16 0, %0, 0, %1, 0, %2, 0, 0, 0, implicit $mode, implicit $exec + S_ENDPGM 0, implicit %3 +... _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
