https://github.com/harrisonGPU updated https://github.com/llvm/llvm-project/pull/225003
>From feeabeafd5e0807b390b992165fd415c64a1a9ae Mon Sep 17 00:00:00 2001 From: Harrison Hao <[email protected]> Date: Mon, 21 Sep 2026 13:19:30 +0800 Subject: [PATCH] [AMDGPU][InstCombine] Fold zero dot operands to accumulator Fold AMDGPU dot intrinsics when either operand is zero. `dot(a, 0) = 0` and `dot(0, b) = 0`, so replace the intrinsic with its accumulator. This avoids unrelated clamp and add/sub reassociation cases. --- .../AMDGPU/AMDGPUInstCombineIntrinsic.cpp | 3 ++ .../InstCombine/AMDGPU/llvm.amdgcn.dot.ll | 45 +++++++------------ 2 files changed, 18 insertions(+), 30 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp index f6c08bdc58d3d..29221f1ec23cd 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp @@ -1983,6 +1983,9 @@ GCNTTIImpl::instCombineIntrinsic(InstCombiner &IC, IntrinsicInst &II) const { return &II; } + if (match(II.getArgOperand(1), m_Zero())) + return IC.replaceInstUsesWith(II, II.getArgOperand(2)); + if (!match(II.getArgOperand(3), m_Zero()) || !II.hasOneUse()) break; diff --git a/llvm/test/Transforms/InstCombine/AMDGPU/llvm.amdgcn.dot.ll b/llvm/test/Transforms/InstCombine/AMDGPU/llvm.amdgcn.dot.ll index 0675276902976..45c9cabbd5533 100644 --- a/llvm/test/Transforms/InstCombine/AMDGPU/llvm.amdgcn.dot.ll +++ b/llvm/test/Transforms/InstCombine/AMDGPU/llvm.amdgcn.dot.ll @@ -26,8 +26,7 @@ define i32 @sdot2_sub(<2 x i16> %a, <2 x i16> %b) { define i32 @sdot2_a_zero(<2 x i16> %b) { ; CHECK-LABEL: define i32 @sdot2_a_zero( ; CHECK-SAME: <2 x i16> [[B:%.*]]) { -; CHECK-NEXT: [[R:%.*]] = call i32 @llvm.amdgcn.sdot2(<2 x i16> [[B]], <2 x i16> zeroinitializer, i32 16, i1 false) -; CHECK-NEXT: ret i32 [[R]] +; CHECK-NEXT: ret i32 16 ; %dot = call i32 @llvm.amdgcn.sdot2(<2 x i16> zeroinitializer, <2 x i16> %b, i32 7, i1 false) %r = add i32 %dot, 9 @@ -37,8 +36,7 @@ define i32 @sdot2_a_zero(<2 x i16> %b) { define i32 @sdot2_const_lhs(<2 x i16> %b, i32 %acc) { ; CHECK-LABEL: define i32 @sdot2_const_lhs( ; CHECK-SAME: <2 x i16> [[B:%.*]], i32 [[ACC:%.*]]) { -; CHECK-NEXT: [[DOT:%.*]] = call i32 @llvm.amdgcn.sdot2(<2 x i16> [[B]], <2 x i16> zeroinitializer, i32 [[ACC]], i1 false) -; CHECK-NEXT: ret i32 [[DOT]] +; CHECK-NEXT: ret i32 [[ACC]] ; %dot = call i32 @llvm.amdgcn.sdot2(<2 x i16> zeroinitializer, <2 x i16> %b, i32 %acc, i1 false) ret i32 %dot @@ -47,8 +45,7 @@ define i32 @sdot2_const_lhs(<2 x i16> %b, i32 %acc) { define i32 @sdot2_b_zero(<2 x i16> %a) { ; CHECK-LABEL: define i32 @sdot2_b_zero( ; CHECK-SAME: <2 x i16> [[A:%.*]]) { -; CHECK-NEXT: [[R:%.*]] = call i32 @llvm.amdgcn.sdot2(<2 x i16> [[A]], <2 x i16> zeroinitializer, i32 16, i1 false) -; CHECK-NEXT: ret i32 [[R]] +; CHECK-NEXT: ret i32 16 ; %dot = call i32 @llvm.amdgcn.sdot2(<2 x i16> %a, <2 x i16> zeroinitializer, i32 7, i1 false) %r = add i32 %dot, 9 @@ -129,8 +126,7 @@ define i32 @udot2_sub(<2 x i16> %a, <2 x i16> %b) { define i32 @udot2_a_zero(<2 x i16> %b) { ; CHECK-LABEL: define i32 @udot2_a_zero( ; CHECK-SAME: <2 x i16> [[B:%.*]]) { -; CHECK-NEXT: [[R:%.*]] = call i32 @llvm.amdgcn.udot2(<2 x i16> [[B]], <2 x i16> zeroinitializer, i32 16, i1 false) -; CHECK-NEXT: ret i32 [[R]] +; CHECK-NEXT: ret i32 16 ; %dot = call i32 @llvm.amdgcn.udot2(<2 x i16> zeroinitializer, <2 x i16> %b, i32 7, i1 false) %r = add i32 %dot, 9 @@ -140,8 +136,7 @@ define i32 @udot2_a_zero(<2 x i16> %b) { define i32 @udot2_const_lhs(<2 x i16> %b, i32 %acc) { ; CHECK-LABEL: define i32 @udot2_const_lhs( ; CHECK-SAME: <2 x i16> [[B:%.*]], i32 [[ACC:%.*]]) { -; CHECK-NEXT: [[DOT:%.*]] = call i32 @llvm.amdgcn.udot2(<2 x i16> [[B]], <2 x i16> zeroinitializer, i32 [[ACC]], i1 false) -; CHECK-NEXT: ret i32 [[DOT]] +; CHECK-NEXT: ret i32 [[ACC]] ; %dot = call i32 @llvm.amdgcn.udot2(<2 x i16> zeroinitializer, <2 x i16> %b, i32 %acc, i1 false) ret i32 %dot @@ -150,8 +145,7 @@ define i32 @udot2_const_lhs(<2 x i16> %b, i32 %acc) { define i32 @udot2_b_zero(<2 x i16> %a) { ; CHECK-LABEL: define i32 @udot2_b_zero( ; CHECK-SAME: <2 x i16> [[A:%.*]]) { -; CHECK-NEXT: [[R:%.*]] = call i32 @llvm.amdgcn.udot2(<2 x i16> [[A]], <2 x i16> zeroinitializer, i32 16, i1 false) -; CHECK-NEXT: ret i32 [[R]] +; CHECK-NEXT: ret i32 16 ; %dot = call i32 @llvm.amdgcn.udot2(<2 x i16> %a, <2 x i16> zeroinitializer, i32 7, i1 false) %r = add i32 %dot, 9 @@ -217,8 +211,7 @@ define i32 @sdot4_sub(i32 %a, i32 %b) { define i32 @sdot4_a_zero(i32 %b) { ; CHECK-LABEL: define i32 @sdot4_a_zero( ; CHECK-SAME: i32 [[B:%.*]]) { -; CHECK-NEXT: [[R:%.*]] = call i32 @llvm.amdgcn.sdot4(i32 [[B]], i32 0, i32 16, i1 false) -; CHECK-NEXT: ret i32 [[R]] +; CHECK-NEXT: ret i32 16 ; %dot = call i32 @llvm.amdgcn.sdot4(i32 0, i32 %b, i32 7, i1 false) %r = add i32 %dot, 9 @@ -238,8 +231,7 @@ define i32 @sdot4_const_lhs(i32 %b, i32 %acc) { define i32 @sdot4_b_zero(i32 %a) { ; CHECK-LABEL: define i32 @sdot4_b_zero( ; CHECK-SAME: i32 [[A:%.*]]) { -; CHECK-NEXT: [[R:%.*]] = call i32 @llvm.amdgcn.sdot4(i32 [[A]], i32 0, i32 16, i1 false) -; CHECK-NEXT: ret i32 [[R]] +; CHECK-NEXT: ret i32 16 ; %dot = call i32 @llvm.amdgcn.sdot4(i32 %a, i32 0, i32 7, i1 false) %r = add i32 %dot, 9 @@ -367,8 +359,7 @@ define i32 @udot4_sub(i32 %a, i32 %b) { define i32 @udot4_a_zero(i32 %b) { ; CHECK-LABEL: define i32 @udot4_a_zero( ; CHECK-SAME: i32 [[B:%.*]]) { -; CHECK-NEXT: [[R:%.*]] = call i32 @llvm.amdgcn.udot4(i32 [[B]], i32 0, i32 16, i1 false) -; CHECK-NEXT: ret i32 [[R]] +; CHECK-NEXT: ret i32 16 ; %dot = call i32 @llvm.amdgcn.udot4(i32 0, i32 %b, i32 7, i1 false) %r = add i32 %dot, 9 @@ -388,8 +379,7 @@ define i32 @udot4_const_lhs(i32 %b, i32 %acc) { define i32 @udot4_b_zero(i32 %a) { ; CHECK-LABEL: define i32 @udot4_b_zero( ; CHECK-SAME: i32 [[A:%.*]]) { -; CHECK-NEXT: [[R:%.*]] = call i32 @llvm.amdgcn.udot4(i32 [[A]], i32 0, i32 16, i1 false) -; CHECK-NEXT: ret i32 [[R]] +; CHECK-NEXT: ret i32 16 ; %dot = call i32 @llvm.amdgcn.udot4(i32 %a, i32 0, i32 7, i1 false) %r = add i32 %dot, 9 @@ -444,8 +434,7 @@ define i32 @sdot8_sub(i32 %a, i32 %b) { define i32 @sdot8_a_zero(i32 %b) { ; CHECK-LABEL: define i32 @sdot8_a_zero( ; CHECK-SAME: i32 [[B:%.*]]) { -; CHECK-NEXT: [[R:%.*]] = call i32 @llvm.amdgcn.sdot8(i32 [[B]], i32 0, i32 16, i1 false) -; CHECK-NEXT: ret i32 [[R]] +; CHECK-NEXT: ret i32 16 ; %dot = call i32 @llvm.amdgcn.sdot8(i32 0, i32 %b, i32 7, i1 false) %r = add i32 %dot, 9 @@ -465,8 +454,7 @@ define i32 @sdot8_const_lhs(i32 %b, i32 %acc) { define i32 @sdot8_b_zero(i32 %a) { ; CHECK-LABEL: define i32 @sdot8_b_zero( ; CHECK-SAME: i32 [[A:%.*]]) { -; CHECK-NEXT: [[R:%.*]] = call i32 @llvm.amdgcn.sdot8(i32 [[A]], i32 0, i32 16, i1 false) -; CHECK-NEXT: ret i32 [[R]] +; CHECK-NEXT: ret i32 16 ; %dot = call i32 @llvm.amdgcn.sdot8(i32 %a, i32 0, i32 7, i1 false) %r = add i32 %dot, 9 @@ -521,8 +509,7 @@ define i32 @udot8_sub(i32 %a, i32 %b) { define i32 @udot8_a_zero(i32 %b) { ; CHECK-LABEL: define i32 @udot8_a_zero( ; CHECK-SAME: i32 [[B:%.*]]) { -; CHECK-NEXT: [[R:%.*]] = call i32 @llvm.amdgcn.udot8(i32 [[B]], i32 0, i32 16, i1 false) -; CHECK-NEXT: ret i32 [[R]] +; CHECK-NEXT: ret i32 16 ; %dot = call i32 @llvm.amdgcn.udot8(i32 0, i32 %b, i32 7, i1 false) %r = add i32 %dot, 9 @@ -532,8 +519,7 @@ define i32 @udot8_a_zero(i32 %b) { define i32 @udot8_const_lhs(i32 %b, i32 %acc) { ; CHECK-LABEL: define i32 @udot8_const_lhs( ; CHECK-SAME: i32 [[B:%.*]], i32 [[ACC:%.*]]) { -; CHECK-NEXT: [[DOT:%.*]] = call i32 @llvm.amdgcn.udot8(i32 [[B]], i32 0, i32 [[ACC]], i1 false) -; CHECK-NEXT: ret i32 [[DOT]] +; CHECK-NEXT: ret i32 [[ACC]] ; %dot = call i32 @llvm.amdgcn.udot8(i32 0, i32 %b, i32 %acc, i1 false) ret i32 %dot @@ -542,8 +528,7 @@ define i32 @udot8_const_lhs(i32 %b, i32 %acc) { define i32 @udot8_b_zero(i32 %a) { ; CHECK-LABEL: define i32 @udot8_b_zero( ; CHECK-SAME: i32 [[A:%.*]]) { -; CHECK-NEXT: [[R:%.*]] = call i32 @llvm.amdgcn.udot8(i32 [[A]], i32 0, i32 16, i1 false) -; CHECK-NEXT: ret i32 [[R]] +; CHECK-NEXT: ret i32 16 ; %dot = call i32 @llvm.amdgcn.udot8(i32 %a, i32 0, i32 7, i1 false) %r = add i32 %dot, 9 _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
