https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/225178
This was only maintained, never relied on. Part of staged LiveVariables removal. Co-authored-by: Claude (Claude-Opus-4.8) >From 22d549e681ea14023dccf5a1fe9ebb39bc288ac5 Mon Sep 17 00:00:00 2001 From: Matt Arsenault <[email protected]> Date: Wed, 9 Sep 2026 16:48:03 +0200 Subject: [PATCH] AMDGPU: Remove update-only LiveVariables maintenance from SILowerControlFlow This was only maintained, never relied on. Part of staged LiveVariables removal. Co-authored-by: Claude (Claude-Opus-4.8) --- llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp | 72 ++------------- ...wer-control-flow-live-variables-update.mir | 87 +++++++++++++++++++ ...ntrol-flow-live-variables-update.xfail.mir | 42 --------- 3 files changed, 92 insertions(+), 109 deletions(-) delete mode 100644 llvm/test/CodeGen/AMDGPU/lower-control-flow-live-variables-update.xfail.mir diff --git a/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp b/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp index 6c87ba5438f3d..67288d0c4f130 100644 --- a/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp +++ b/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp @@ -53,7 +53,6 @@ #include "AMDGPULaneMaskUtils.h" #include "GCNSubtarget.h" #include "llvm/CodeGen/LiveIntervals.h" -#include "llvm/CodeGen/LiveVariables.h" #include "llvm/CodeGen/MachineBlockFrequencyInfo.h" #include "llvm/CodeGen/MachineDominators.h" #include "llvm/CodeGen/MachineFunctionPass.h" @@ -76,7 +75,6 @@ class SILowerControlFlow { const SIRegisterInfo *TRI = nullptr; const SIInstrInfo *TII = nullptr; LiveIntervals *LIS = nullptr; - LiveVariables *LV = nullptr; MachineDominatorTree *MDT = nullptr; MachinePostDominatorTree *PDT = nullptr; MachineRegisterInfo *MRI = nullptr; @@ -133,10 +131,9 @@ class SILowerControlFlow { public: SILowerControlFlow(const GCNSubtarget *ST, LiveIntervals *LIS, - LiveVariables *LV, MachineDominatorTree *MDT, - MachinePostDominatorTree *PDT) - : LIS(LIS), LV(LV), MDT(MDT), PDT(PDT), - LMC(AMDGPU::LaneMaskConstants::get(*ST)) {} + MachineDominatorTree *MDT, MachinePostDominatorTree *PDT) + : LIS(LIS), MDT(MDT), PDT(PDT), LMC(AMDGPU::LaneMaskConstants::get(*ST)) { + } bool run(MachineFunction &MF); }; @@ -159,7 +156,6 @@ class SILowerControlFlowLegacy : public MachineFunctionPass { AU.addPreserved<MachinePostDominatorTreeWrapperPass>(); AU.addPreserved<SlotIndexesWrapperPass>(); AU.addPreserved<LiveIntervalsWrapperPass>(); - AU.addPreserved<LiveVariablesWrapperPass>(); AU.addPreserved<MachineRegisterClassInfoWrapperPass>(); AU.addPreserved<MachineBlockFrequencyInfoWrapperPass>(); MachineFunctionPass::getAnalysisUsage(AU); @@ -249,8 +245,6 @@ void SILowerControlFlow::emitIf(MachineInstr &MI) { MachineInstr *And = BuildMI(MBB, I, DL, TII->get(LMC.AndOpc), Tmp).addReg(CopyReg).add(Cond); - if (LV) - LV->replaceKillInstruction(Cond.getReg(), MI, *And); setImpSCCDefDead(*And, true); @@ -267,8 +261,6 @@ void SILowerControlFlow::emitIf(MachineInstr &MI) { MachineInstr *SetExec = BuildMI(MBB, I, DL, TII->get(LMC.MovTermOpc), LMC.ExecReg) .addReg(Tmp, RegState::Kill); - if (LV) - LV->getVarInfo(Tmp).Kills.push_back(SetExec); // Skip ahead to the unconditional branch in case there are other terminators // present. @@ -321,8 +313,6 @@ void SILowerControlFlow::emitElse(MachineInstr &MI) { MachineInstr *OrSaveExec = BuildMI(MBB, Start, DL, TII->get(LMC.OrSaveExecOpc), SaveReg) .add(MI.getOperand(1)); // Saved EXEC - if (LV) - LV->replaceKillInstruction(SrcReg, MI, *OrSaveExec); MachineBasicBlock *DestBB = MI.getOperand(2).getMBB(); @@ -392,8 +382,6 @@ void SILowerControlFlow::emitIfBreak(MachineInstr &MI) { And = BuildMI(MBB, &MI, DL, TII->get(LMC.AndOpc), AndReg) .addReg(LMC.ExecReg) .add(MI.getOperand(1)); - if (LV) - LV->replaceKillInstruction(MI.getOperand(1).getReg(), MI, *And); Or = BuildMI(MBB, &MI, DL, TII->get(LMC.OrOpc), Dst) .addReg(AndReg) .add(MI.getOperand(2)); @@ -401,11 +389,7 @@ void SILowerControlFlow::emitIfBreak(MachineInstr &MI) { Or = BuildMI(MBB, &MI, DL, TII->get(LMC.OrOpc), Dst) .add(MI.getOperand(1)) .add(MI.getOperand(2)); - if (LV) - LV->replaceKillInstruction(MI.getOperand(1).getReg(), MI, *Or); } - if (LV) - LV->replaceKillInstruction(MI.getOperand(2).getReg(), MI, *Or); if (LIS) { LIS->ReplaceMachineInstrInMaps(MI, *Or); @@ -428,8 +412,6 @@ void SILowerControlFlow::emitLoop(MachineInstr &MI) { BuildMI(MBB, &MI, DL, TII->get(LMC.AndN2TermOpc), LMC.ExecReg) .addReg(LMC.ExecReg) .add(MI.getOperand(0)); - if (LV) - LV->replaceKillInstruction(MI.getOperand(0).getReg(), MI, *AndN2); auto BranchPt = skipToUncondBrOrEnd(MBB, MI.getIterator()); MachineInstr *Branch = @@ -518,40 +500,6 @@ MachineBasicBlock *SILowerControlFlow::emitEndCf(MachineInstr &MI) { MachineInstr *NewMI = BuildMI(MBB, InsPt, DL, TII->get(Opcode), LMC.ExecReg) .addReg(LMC.ExecReg) .add(MI.getOperand(0)); - if (LV) { - LV->replaceKillInstruction(DataReg, MI, *NewMI); - - if (SplitBB != &MBB) { - // Track the set of registers defined in the original block so we don't - // accidentally add the original block to AliveBlocks. AliveBlocks only - // includes blocks which are live through, which excludes live outs and - // local defs. - DenseSet<Register> DefInOrigBlock; - - for (MachineBasicBlock *BlockPiece : {&MBB, SplitBB}) { - for (MachineInstr &X : *BlockPiece) { - for (MachineOperand &Op : X.all_defs()) { - if (Op.getReg().isVirtual()) - DefInOrigBlock.insert(Op.getReg()); - } - } - } - - for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) { - Register Reg = Register::index2VirtReg(i); - LiveVariables::VarInfo &VI = LV->getVarInfo(Reg); - - if (VI.AliveBlocks.test(MBB.getNumber())) - VI.AliveBlocks.set(SplitBB->getNumber()); - else { - for (MachineInstr *Kill : VI.Kills) { - if (Kill->getParent() == SplitBB && !DefInOrigBlock.contains(Reg)) - VI.AliveBlocks.set(MBB.getNumber()); - } - } - } - } - } LoweredEndCf.insert(NewMI); @@ -663,12 +611,7 @@ void SILowerControlFlow::optimizeEndCf() { LLVM_DEBUG(dbgs() << "Skip redundant "; MI->dump()); if (LIS) LIS->RemoveMachineInstrFromMaps(*MI); - Register Reg; - if (LV) - Reg = TII->getNamedOperand(*MI, AMDGPU::OpName::src1)->getReg(); MI->eraseFromParent(); - if (LV) - LV->recomputeForSingleDefVirtReg(Reg); removeMBBifRedundant(MBB); } } @@ -890,16 +833,13 @@ bool SILowerControlFlowLegacy::runOnMachineFunction(MachineFunction &MF) { // This doesn't actually need LiveIntervals, but we can preserve them. auto *LISWrapper = getAnalysisIfAvailable<LiveIntervalsWrapperPass>(); LiveIntervals *LIS = LISWrapper ? &LISWrapper->getLIS() : nullptr; - // This doesn't actually need LiveVariables, but we can preserve them. - auto *LVWrapper = getAnalysisIfAvailable<LiveVariablesWrapperPass>(); - LiveVariables *LV = LVWrapper ? &LVWrapper->getLV() : nullptr; auto *MDTWrapper = getAnalysisIfAvailable<MachineDominatorTreeWrapperPass>(); MachineDominatorTree *MDT = MDTWrapper ? &MDTWrapper->getDomTree() : nullptr; auto *PDTWrapper = getAnalysisIfAvailable<MachinePostDominatorTreeWrapperPass>(); MachinePostDominatorTree *PDT = PDTWrapper ? &PDTWrapper->getPostDomTree() : nullptr; - return SILowerControlFlow(ST, LIS, LV, MDT, PDT).run(MF); + return SILowerControlFlow(ST, LIS, MDT, PDT).run(MF); } PreservedAnalyses @@ -907,13 +847,12 @@ SILowerControlFlowPass::run(MachineFunction &MF, MachineFunctionAnalysisManager &MFAM) { const GCNSubtarget *ST = &MF.getSubtarget<GCNSubtarget>(); LiveIntervals *LIS = MFAM.getCachedResult<LiveIntervalsAnalysis>(MF); - LiveVariables *LV = MFAM.getCachedResult<LiveVariablesAnalysis>(MF); MachineDominatorTree *MDT = MFAM.getCachedResult<MachineDominatorTreeAnalysis>(MF); MachinePostDominatorTree *PDT = MFAM.getCachedResult<MachinePostDominatorTreeAnalysis>(MF); - bool Changed = SILowerControlFlow(ST, LIS, LV, MDT, PDT).run(MF); + bool Changed = SILowerControlFlow(ST, LIS, MDT, PDT).run(MF); if (!Changed) return PreservedAnalyses::all(); @@ -922,7 +861,6 @@ SILowerControlFlowPass::run(MachineFunction &MF, PA.preserve<MachinePostDominatorTreeAnalysis>(); PA.preserve<SlotIndexesAnalysis>(); PA.preserve<LiveIntervalsAnalysis>(); - PA.preserve<LiveVariablesAnalysis>(); PA.preserve<MachineBlockFrequencyAnalysis>(); return PA; } diff --git a/llvm/test/CodeGen/AMDGPU/lower-control-flow-live-variables-update.mir b/llvm/test/CodeGen/AMDGPU/lower-control-flow-live-variables-update.mir index 71aff1841d47b..f3f97eddcad08 100644 --- a/llvm/test/CodeGen/AMDGPU/lower-control-flow-live-variables-update.mir +++ b/llvm/test/CodeGen/AMDGPU/lower-control-flow-live-variables-update.mir @@ -260,3 +260,90 @@ body: | S_BRANCH %bb.2 ... + +# Same as +# live_variables_update_block_split_split_killed_def_before_si_end_cf, +# except the def before si_end_cf is live out of the block +--- +name: live_variables_update_block_split_split_def_before_si_end_cf_live_out +tracksRegLiveness: true +body: | + ; CHECK-LABEL: name: live_variables_update_block_split_split_def_before_si_end_cf_live_out + ; CHECK: bb.0: + ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.3(0x40000000) + ; CHECK-NEXT: liveins: $vgpr0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec + ; CHECK-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U32_e64 0, [[COPY]], implicit $exec + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[V_MOV_B32_e32_]] + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[V_MOV_B32_e32_]] + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec + ; CHECK-NEXT: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY3]], [[V_CMP_EQ_U32_e64_]], implicit-def dead $scc + ; CHECK-NEXT: [[S_XOR_B64_:%[0-9]+]]:sreg_64_xexec = S_XOR_B64 [[S_AND_B64_]], [[COPY3]], implicit-def dead $scc + ; CHECK-NEXT: $exec = S_MOV_B64_term [[S_AND_B64_]] + ; CHECK-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term [[S_XOR_B64_]], implicit $exec + ; CHECK-NEXT: S_CBRANCH_EXECZ %bb.1, implicit $exec + ; CHECK-NEXT: S_BRANCH %bb.3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1: + ; CHECK-NEXT: successors: %bb.4(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sreg_64_xexec = COPY [[S_MOV_B64_term]] + ; CHECK-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 1 + ; CHECK-NEXT: $exec = S_OR_B64_term $exec, [[COPY4]], implicit-def $scc + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.4: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[COPY1]] + ; CHECK-NEXT: [[V_ADD_U32_e32_:%[0-9]+]]:vgpr_32 = nsw V_ADD_U32_e32 1, [[COPY5]], implicit $exec + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2: + ; CHECK-NEXT: successors: %bb.3(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B64_]] + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[V_ADD_U32_e32_]] + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3: + ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.3(0x40000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY2]] + ; CHECK-NEXT: GLOBAL_STORE_DWORD undef %11:vreg_64, [[COPY6]], 0, 0, implicit $exec :: (volatile store (s32), addrspace 1) + ; CHECK-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY6]] + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY7]] + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY7]] + ; CHECK-NEXT: [[COPY8:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec + ; CHECK-NEXT: [[S_AND_B64_1:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY8]], [[V_CMP_EQ_U32_e64_]], implicit-def dead $scc + ; CHECK-NEXT: [[S_XOR_B64_1:%[0-9]+]]:sreg_64_xexec = S_XOR_B64 [[S_AND_B64_1]], [[COPY8]], implicit-def dead $scc + ; CHECK-NEXT: $exec = S_MOV_B64_term [[S_AND_B64_1]] + ; CHECK-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term [[S_XOR_B64_1]], implicit $exec + ; CHECK-NEXT: S_CBRANCH_EXECZ %bb.1, implicit $exec + ; CHECK-NEXT: S_BRANCH %bb.3 + bb.0: + liveins: $vgpr0 + + %0:vgpr_32 = COPY killed $vgpr0 + %1:vgpr_32 = V_MOV_B32_e32 0, implicit $exec + %2:sreg_64_xexec = V_CMP_EQ_U32_e64 0, killed %0, implicit $exec + %3:sreg_64_xexec = SI_IF %2, %bb.1, implicit-def $exec, implicit-def dead $scc, implicit $exec + S_BRANCH %bb.3 + + bb.1: + %4:sreg_64_xexec = PHI %5, %bb.3, %3, %bb.0 + %6:vgpr_32 = PHI %7, %bb.3, %1, %bb.0 + %8:sreg_64 = S_MOV_B64 1 + SI_END_CF killed %4, implicit-def $exec, implicit-def dead $scc, implicit $exec + %9:vgpr_32 = nsw V_ADD_U32_e32 1, killed %6, implicit $exec + + bb.2: + S_NOP 0, implicit killed %8 + + bb.3: + %10:vgpr_32 = PHI %9, %bb.2, %7, %bb.3, %1, %bb.0 + GLOBAL_STORE_DWORD undef %11:vreg_64, %10, 0, 0, implicit $exec :: (volatile store (s32), addrspace 1) + %7:vgpr_32 = COPY killed %10 + %5:sreg_64_xexec = SI_IF %2, %bb.1, implicit-def $exec, implicit-def dead $scc, implicit $exec + S_BRANCH %bb.3 + +... diff --git a/llvm/test/CodeGen/AMDGPU/lower-control-flow-live-variables-update.xfail.mir b/llvm/test/CodeGen/AMDGPU/lower-control-flow-live-variables-update.xfail.mir deleted file mode 100644 index 7a6fb07b598bb..0000000000000 --- a/llvm/test/CodeGen/AMDGPU/lower-control-flow-live-variables-update.xfail.mir +++ /dev/null @@ -1,42 +0,0 @@ -# RUN: not --crash llc -mtriple=amdgpu7.00-amd-amdhsa -start-before=livevars -stop-after=twoaddressinstruction -verify-machineinstrs -o - %s 2>&1 | FileCheck %s - -# CHECK: *** Bad machine code: LiveVariables: Block missing from AliveBlocks *** -# CHECK-NEXT: function: live_variables_update_block_split_split_def_before_si_end_cf_live_out -# CHECK-NEXT: basic block: %bb.4 -# CHECK-NEXT: Virtual register %8 must be live through the block. - - -# Same as -# live_variables_update_block_split_split_killed_def_before_si_end_cf, -# except the def before si_end_cf is live out of the block ---- -name: live_variables_update_block_split_split_def_before_si_end_cf_live_out -tracksRegLiveness: true -body: | - bb.0: - liveins: $vgpr0 - - %0:vgpr_32 = COPY killed $vgpr0 - %1:vgpr_32 = V_MOV_B32_e32 0, implicit $exec - %2:sreg_64_xexec = V_CMP_EQ_U32_e64 0, killed %0, implicit $exec - %3:sreg_64_xexec = SI_IF %2, %bb.1, implicit-def $exec, implicit-def dead $scc, implicit $exec - S_BRANCH %bb.3 - - bb.1: - %4:sreg_64_xexec = PHI %5, %bb.3, %3, %bb.0 - %6:vgpr_32 = PHI %7, %bb.3, %1, %bb.0 - %8:sreg_64 = S_MOV_B64 1 - SI_END_CF killed %4, implicit-def $exec, implicit-def dead $scc, implicit $exec - %9:vgpr_32 = nsw V_ADD_U32_e32 1, killed %6, implicit $exec - - bb.2: - S_NOP 0, implicit killed %8 - - bb.3: - %10:vgpr_32 = PHI %9, %bb.2, %7, %bb.3, %1, %bb.0 - GLOBAL_STORE_DWORD undef %11:vreg_64, %10, 0, 0, implicit $exec :: (volatile store (s32), addrspace 1) - %7:vgpr_32 = COPY killed %10 - %5:sreg_64_xexec = SI_IF %2, %bb.1, implicit-def $exec, implicit-def dead $scc, implicit $exec - S_BRANCH %bb.3 - -... _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
