================
@@ -3508,8 +3508,7 @@ bool RISCVTTIImpl::isLegalMaskedExpandLoad(Type *DataTy,
bool RISCVTTIImpl::isLegalMaskedCompressStore(Type *DataTy,
Align Alignment) const {
- auto *VTy = dyn_cast<VectorType>(DataTy);
- if (!VTy || VTy->isScalableTy())
+ if (!isa<VectorType>(DataTy))
return false;
if (!isLegalMaskedLoadStore(DataTy, Alignment))
----------------
lukel97 wrote:
Argh, then either we need to make the interfaces consistent and pass in a
vector type, to align with how ScalarizedMaskMemIntrin.cpp passes in the vector
type. Since only certain vector lengths need to be scalarized on RISC-V.
Or we need to somehow change the RISC-V backend so that any vector length is
legal. I think that should be possible but we will need to manually split the
intrinsic.
https://github.com/llvm/llvm-project/pull/225143
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