github-actions[bot] wrote:
<!--LLVM CODE FORMAT COMMENT: {clang-format}-->
:warning: C/C++ code formatter, clang-format found issues in your code.
:warning:
<details>
<summary>
You can test this locally with the following command:
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``````````bash
git-clang-format --diff origin/main HEAD --extensions cpp,h --
llvm/include/llvm/CodeGen/TargetRegisterInfo.h
llvm/lib/CodeGen/InlineSpiller.cpp llvm/lib/CodeGen/TargetRegisterInfo.cpp
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
llvm/lib/Target/AMDGPU/SIRegisterInfo.h --diff_from_common_commit
``````````
:warning:
The reproduction instructions above might return results for more than one PR
in a stack if you are using a stacked PR workflow. You can limit the results by
changing `origin/main` to the base branch/commit you want to compare against.
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View the diff from clang-format here.
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``````````diff
diff --git a/llvm/include/llvm/CodeGen/TargetRegisterInfo.h
b/llvm/include/llvm/CodeGen/TargetRegisterInfo.h
index effb67d86..d0e992a41 100644
--- a/llvm/include/llvm/CodeGen/TargetRegisterInfo.h
+++ b/llvm/include/llvm/CodeGen/TargetRegisterInfo.h
@@ -1095,7 +1095,7 @@ public:
virtual const TargetRegisterClass *
getConstrainedRegClassForReg(Register Reg,
- const MachineRegisterInfo &MRI) const {
+ const MachineRegisterInfo &MRI) const {
return nullptr;
}
diff --git a/llvm/lib/CodeGen/TargetRegisterInfo.cpp
b/llvm/lib/CodeGen/TargetRegisterInfo.cpp
index 98ca01035..ac83c1d50 100644
--- a/llvm/lib/CodeGen/TargetRegisterInfo.cpp
+++ b/llvm/lib/CodeGen/TargetRegisterInfo.cpp
@@ -497,7 +497,7 @@ TargetRegisterInfo::getRegSizeInBits(Register Reg,
unsigned
TargetRegisterInfo::getSubRegIdxFromLaneMask(LaneBitmask LaneMask) const {
- for (unsigned Idx = 1, E = getNumSubRegIndices(); Idx < E; ++Idx) {
+ for (unsigned Idx = 1, E = getNumSubRegIndices(); Idx < E; ++Idx) {
if (getSubRegIndexLaneMask(Idx) == LaneMask)
return Idx;
}
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
b/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
index e3866ea81..33a19bd4f 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
@@ -385,7 +385,7 @@ public:
const TargetRegisterClass *
getConstrainedRegClassForReg(Register Reg,
- const MachineRegisterInfo &MRI) const
override;
+ const MachineRegisterInfo &MRI) const override;
const TargetRegisterClass *getBoolRC() const {
return isWave32 ? &AMDGPU::SReg_32RegClass
``````````
</details>
https://github.com/llvm/llvm-project/pull/175002
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