https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/225178
>From 5ed6384975b87a5667da0d70fafb680c2252e5ea Mon Sep 17 00:00:00 2001 From: Matt Arsenault <[email protected]> Date: Wed, 9 Sep 2026 16:48:03 +0200 Subject: [PATCH] AMDGPU: Remove update-only LiveVariables maintenance from SILowerControlFlow This was only maintained, never relied on. Part of staged LiveVariables removal. Co-authored-by: Claude (Claude-Opus-4.8) --- llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp | 76 ++----------------- 1 file changed, 5 insertions(+), 71 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp b/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp index 8d7bd32c866c4..c54ac39b3444c 100644 --- a/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp +++ b/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp @@ -53,7 +53,6 @@ #include "AMDGPULaneMaskUtils.h" #include "GCNSubtarget.h" #include "llvm/CodeGen/LiveIntervals.h" -#include "llvm/CodeGen/LiveVariables.h" #include "llvm/CodeGen/MachineBlockFrequencyInfo.h" #include "llvm/CodeGen/MachineDominators.h" #include "llvm/CodeGen/MachineFunctionPass.h" @@ -76,7 +75,6 @@ class SILowerControlFlow { const SIRegisterInfo *TRI = nullptr; const SIInstrInfo *TII = nullptr; LiveIntervals *LIS = nullptr; - LiveVariables *LV = nullptr; MachineDominatorTree *MDT = nullptr; MachinePostDominatorTree *PDT = nullptr; MachineRegisterInfo *MRI = nullptr; @@ -133,10 +131,9 @@ class SILowerControlFlow { public: SILowerControlFlow(const GCNSubtarget *ST, LiveIntervals *LIS, - LiveVariables *LV, MachineDominatorTree *MDT, - MachinePostDominatorTree *PDT) - : LIS(LIS), LV(LV), MDT(MDT), PDT(PDT), - LMC(AMDGPU::LaneMaskConstants::get(*ST)) {} + MachineDominatorTree *MDT, MachinePostDominatorTree *PDT) + : LIS(LIS), MDT(MDT), PDT(PDT), LMC(AMDGPU::LaneMaskConstants::get(*ST)) { + } bool run(MachineFunction &MF); }; @@ -159,7 +156,6 @@ class SILowerControlFlowLegacy : public MachineFunctionPass { AU.addPreserved<MachinePostDominatorTreeWrapperPass>(); AU.addPreserved<SlotIndexesWrapperPass>(); AU.addPreserved<LiveIntervalsWrapperPass>(); - AU.addPreserved<LiveVariablesWrapperPass>(); AU.addPreserved<MachineRegisterClassInfoWrapperPass>(); AU.addPreserved<MachineBlockFrequencyInfoWrapperPass>(); MachineFunctionPass::getAnalysisUsage(AU); @@ -253,9 +249,6 @@ void SILowerControlFlow::emitIf(MachineInstr &MI) { BuildMI(MBB, I, DL, TII->get(LMC.AndOpc), Tmp).addReg(CopyReg).add(Cond); setImpSCCDefDead(*And); - if (LV) - LV->replaceKillInstruction(Cond.getReg(), MI, *And); - MachineInstr *Xor = nullptr; if (!SimpleIf) { Xor = BuildMI(MBB, I, DL, TII->get(LMC.XorOpc), SaveExecReg) @@ -269,8 +262,6 @@ void SILowerControlFlow::emitIf(MachineInstr &MI) { MachineInstr *SetExec = BuildMI(MBB, I, DL, TII->get(LMC.MovTermOpc), LMC.ExecReg) .addReg(Tmp, RegState::Kill); - if (LV) - LV->getVarInfo(Tmp).Kills.push_back(SetExec); // Skip ahead to the unconditional branch in case there are other terminators // present. @@ -324,8 +315,6 @@ void SILowerControlFlow::emitElse(MachineInstr &MI) { BuildMI(MBB, Start, DL, TII->get(LMC.OrSaveExecOpc), SaveReg) .add(MI.getOperand(1)); // Saved EXEC setImpSCCDefDead(*OrSaveExec, /*IsDead=*/true); - if (LV) - LV->replaceKillInstruction(SrcReg, MI, *OrSaveExec); MachineBasicBlock *DestBB = MI.getOperand(2).getMBB(); @@ -398,8 +387,6 @@ void SILowerControlFlow::emitIfBreak(MachineInstr &MI) { .addReg(LMC.ExecReg) .add(MI.getOperand(1)); setImpSCCDefDead(*And, /*IsDead=*/true); - if (LV) - LV->replaceKillInstruction(MI.getOperand(1).getReg(), MI, *And); Or = BuildMI(MBB, &MI, DL, TII->get(LMC.OrOpc), Dst) .addReg(AndReg) .add(MI.getOperand(2)); @@ -407,15 +394,10 @@ void SILowerControlFlow::emitIfBreak(MachineInstr &MI) { Or = BuildMI(MBB, &MI, DL, TII->get(LMC.OrOpc), Dst) .add(MI.getOperand(1)) .add(MI.getOperand(2)); - if (LV) - LV->replaceKillInstruction(MI.getOperand(1).getReg(), MI, *Or); } copySCCDefDead(*Or, MI.getOperand(3)); - if (LV) - LV->replaceKillInstruction(MI.getOperand(2).getReg(), MI, *Or); - if (LIS) { LIS->ReplaceMachineInstrInMaps(MI, *Or); if (And) { @@ -439,9 +421,6 @@ void SILowerControlFlow::emitLoop(MachineInstr &MI) { .add(MI.getOperand(0)); copySCCDefDead(*AndN2, MI.getOperand(3)); - if (LV) - LV->replaceKillInstruction(MI.getOperand(0).getReg(), MI, *AndN2); - auto BranchPt = skipToUncondBrOrEnd(MBB, MI.getIterator()); MachineInstr *Branch = BuildMI(MBB, BranchPt, DL, TII->get(AMDGPU::S_CBRANCH_EXECNZ)) @@ -531,41 +510,6 @@ MachineBasicBlock *SILowerControlFlow::emitEndCf(MachineInstr &MI) { .add(MI.getOperand(0)); copySCCDefDead(*NewMI, MI.getOperand(2)); - if (LV) { - LV->replaceKillInstruction(DataReg, MI, *NewMI); - - if (SplitBB != &MBB) { - // Track the set of registers defined in the original block so we don't - // accidentally add the original block to AliveBlocks. AliveBlocks only - // includes blocks which are live through, which excludes live outs and - // local defs. - DenseSet<Register> DefInOrigBlock; - - for (MachineBasicBlock *BlockPiece : {&MBB, SplitBB}) { - for (MachineInstr &X : *BlockPiece) { - for (MachineOperand &Op : X.all_defs()) { - if (Op.getReg().isVirtual()) - DefInOrigBlock.insert(Op.getReg()); - } - } - } - - for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) { - Register Reg = Register::index2VirtReg(i); - LiveVariables::VarInfo &VI = LV->getVarInfo(Reg); - - if (VI.AliveBlocks.test(MBB.getNumber())) - VI.AliveBlocks.set(SplitBB->getNumber()); - else { - for (MachineInstr *Kill : VI.Kills) { - if (Kill->getParent() == SplitBB && !DefInOrigBlock.contains(Reg)) - VI.AliveBlocks.set(MBB.getNumber()); - } - } - } - } - } - LoweredEndCf.insert(NewMI); if (LIS) @@ -676,12 +620,7 @@ void SILowerControlFlow::optimizeEndCf() { LLVM_DEBUG(dbgs() << "Skip redundant "; MI->dump()); if (LIS) LIS->RemoveMachineInstrFromMaps(*MI); - Register Reg; - if (LV) - Reg = TII->getNamedOperand(*MI, AMDGPU::OpName::src1)->getReg(); MI->eraseFromParent(); - if (LV) - LV->recomputeForSingleDefVirtReg(Reg); removeMBBifRedundant(MBB); } } @@ -903,16 +842,13 @@ bool SILowerControlFlowLegacy::runOnMachineFunction(MachineFunction &MF) { // This doesn't actually need LiveIntervals, but we can preserve them. auto *LISWrapper = getAnalysisIfAvailable<LiveIntervalsWrapperPass>(); LiveIntervals *LIS = LISWrapper ? &LISWrapper->getLIS() : nullptr; - // This doesn't actually need LiveVariables, but we can preserve them. - auto *LVWrapper = getAnalysisIfAvailable<LiveVariablesWrapperPass>(); - LiveVariables *LV = LVWrapper ? &LVWrapper->getLV() : nullptr; auto *MDTWrapper = getAnalysisIfAvailable<MachineDominatorTreeWrapperPass>(); MachineDominatorTree *MDT = MDTWrapper ? &MDTWrapper->getDomTree() : nullptr; auto *PDTWrapper = getAnalysisIfAvailable<MachinePostDominatorTreeWrapperPass>(); MachinePostDominatorTree *PDT = PDTWrapper ? &PDTWrapper->getPostDomTree() : nullptr; - return SILowerControlFlow(ST, LIS, LV, MDT, PDT).run(MF); + return SILowerControlFlow(ST, LIS, MDT, PDT).run(MF); } PreservedAnalyses @@ -920,13 +856,12 @@ SILowerControlFlowPass::run(MachineFunction &MF, MachineFunctionAnalysisManager &MFAM) { const GCNSubtarget *ST = &MF.getSubtarget<GCNSubtarget>(); LiveIntervals *LIS = MFAM.getCachedResult<LiveIntervalsAnalysis>(MF); - LiveVariables *LV = MFAM.getCachedResult<LiveVariablesAnalysis>(MF); MachineDominatorTree *MDT = MFAM.getCachedResult<MachineDominatorTreeAnalysis>(MF); MachinePostDominatorTree *PDT = MFAM.getCachedResult<MachinePostDominatorTreeAnalysis>(MF); - bool Changed = SILowerControlFlow(ST, LIS, LV, MDT, PDT).run(MF); + bool Changed = SILowerControlFlow(ST, LIS, MDT, PDT).run(MF); if (!Changed) return PreservedAnalyses::all(); @@ -935,7 +870,6 @@ SILowerControlFlowPass::run(MachineFunction &MF, PA.preserve<MachinePostDominatorTreeAnalysis>(); PA.preserve<SlotIndexesAnalysis>(); PA.preserve<LiveIntervalsAnalysis>(); - PA.preserve<LiveVariablesAnalysis>(); PA.preserve<MachineBlockFrequencyAnalysis>(); return PA; } _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
