https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/228165
>From 9be08732602c21293dc295f1eeb92df320a3a31d Mon Sep 17 00:00:00 2001 From: Matt Arsenault <[email protected]> Date: Thu, 1 Oct 2026 18:55:21 +0200 Subject: [PATCH] Targets: Remove redundant TRI arguments from InstrInfo helpers This is directly available in TargetInstrInfo. Co-authored-by: Claude Opus 5 <[email protected]> --- llvm/lib/Target/AArch64/AArch64InstrInfo.cpp | 14 ++++++-------- llvm/lib/Target/AArch64/AArch64InstrInfo.h | 3 +-- .../lib/Target/Hexagon/HexagonHardwareLoops.cpp | 4 ++-- llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp | 4 ++-- llvm/lib/Target/Hexagon/HexagonInstrInfo.h | 3 +-- llvm/lib/Target/Hexagon/HexagonOptAddrMode.cpp | 6 +++--- llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp | 2 +- .../Target/Hexagon/HexagonVLIWPacketizer.cpp | 4 ++-- llvm/lib/Target/Lanai/LanaiInstrInfo.cpp | 15 +++++++-------- llvm/lib/Target/Lanai/LanaiInstrInfo.h | 3 +-- llvm/lib/Target/PowerPC/PPCInstrInfo.cpp | 17 +++++++++-------- llvm/lib/Target/PowerPC/PPCInstrInfo.h | 3 +-- llvm/lib/Target/RISCV/RISCVInstrInfo.cpp | 10 ++++------ llvm/lib/Target/RISCV/RISCVInstrInfo.h | 3 +-- 14 files changed, 41 insertions(+), 50 deletions(-) diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp index 00ac9b0c687bfc..1d4d9c0dff1d4e 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp @@ -1626,7 +1626,6 @@ bool AArch64InstrInfo::isCoalescableExtInstr(const MachineInstr &MI, bool AArch64InstrInfo::areMemAccessesTriviallyDisjoint( const MachineInstr &MIa, const MachineInstr &MIb) const { - const TargetRegisterInfo *TRI = &getRegisterInfo(); const MachineOperand *BaseOpA = nullptr, *BaseOpB = nullptr; int64_t OffsetA = 0, OffsetB = 0; TypeSize WidthA(0, false), WidthB(0, false); @@ -1647,9 +1646,9 @@ bool AArch64InstrInfo::areMemAccessesTriviallyDisjoint( // If OffsetAIsScalable and OffsetBIsScalable are both true, they // are assumed to have the same scale (vscale). if (getMemOperandWithOffsetWidth(MIa, BaseOpA, OffsetA, OffsetAIsScalable, - WidthA, TRI) && + WidthA) && getMemOperandWithOffsetWidth(MIb, BaseOpB, OffsetB, OffsetBIsScalable, - WidthB, TRI)) { + WidthB)) { if (BaseOpA->isIdenticalTo(*BaseOpB) && OffsetAIsScalable == OffsetBIsScalable) { int LowOffset = OffsetA < OffsetB ? OffsetA : OffsetB; @@ -3690,7 +3689,7 @@ bool AArch64InstrInfo::getMemOperandsWithOffsetWidth( const MachineOperand *BaseOp; TypeSize WidthN(0, false); if (!getMemOperandWithOffsetWidth(LdSt, BaseOp, Offset, OffsetIsScalable, - WidthN, &RI)) + WidthN)) return false; // The maximum vscale is 16 under AArch64, return the maximal extent for the // vector. @@ -4696,8 +4695,7 @@ static bool isPostIndexLdStOpcode(unsigned Opcode) { bool AArch64InstrInfo::getMemOperandWithOffsetWidth( const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset, - bool &OffsetIsScalable, TypeSize &Width, - const TargetRegisterInfo *TRI) const { + bool &OffsetIsScalable, TypeSize &Width) const { assert(LdSt.mayLoadOrStore() && "Expected a memory operation."); // Handle only loads/stores with base register followed by immediate offset. if (LdSt.getNumExplicitOperands() == 3) { @@ -11268,8 +11266,8 @@ void AArch64InstrInfo::fixupPostOutline(MachineBasicBlock &MBB) const { // Is this a load or store with an immediate offset with SP as the base? if (!MI.mayLoadOrStore() || - !getMemOperandWithOffsetWidth(MI, Base, Offset, OffsetIsScalable, Width, - &RI) || + !getMemOperandWithOffsetWidth(MI, Base, Offset, OffsetIsScalable, + Width) || (Base->isReg() && Base->getReg() != AArch64::SP)) continue; diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.h b/llvm/lib/Target/AArch64/AArch64InstrInfo.h index 4654fce39b02e1..7efdc3b7026ff8 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.h +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.h @@ -335,8 +335,7 @@ class AArch64InstrInfo final : public AArch64GenInstrInfo { bool getMemOperandWithOffsetWidth(const MachineInstr &MI, const MachineOperand *&BaseOp, int64_t &Offset, bool &OffsetIsScalable, - TypeSize &Width, - const TargetRegisterInfo *TRI) const; + TypeSize &Width) const; /// Return the immediate offset of the base register in a load/store \p LdSt. MachineOperand &getMemOpBaseRegImmOfsOffsetOperand(MachineInstr &LdSt) const; diff --git a/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp b/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp index b1b02907b2fcba..263a01cd04f6bc 100644 --- a/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp +++ b/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp @@ -1375,7 +1375,7 @@ bool HexagonHardwareLoops::convertToHardwareLoop(MachineLoop *L, // if the immediate fits in the instructions. Otherwise, we need to // create a new virtual register. int64_t CountImm = TripCount->getImm(); - if (!TII->isValidOffset(LOOP_i, CountImm, TRI)) { + if (!TII->isValidOffset(LOOP_i, CountImm)) { Register CountReg = MRI->createVirtualRegister(&Hexagon::IntRegsRegClass); BuildMI(*Preheader, InsertPos, DL, TII->get(Hexagon::A2_tfrsi), CountReg) .addImm(CountImm); @@ -1931,7 +1931,7 @@ bool HexagonHardwareLoops::fixupInductionVariable(MachineLoop *L) { // the immediate to be constant-extended. There are some exceptions // though. Make sure the new combination will work. if (CmpImmOp->isImm() && !TII->isExtendable(*PredDef) && - !TII->isValidOffset(PredDef->getOpcode(), CmpImm, TRI, false)) + !TII->isValidOffset(PredDef->getOpcode(), CmpImm, false)) return false; // Make sure that the compare happens after the bump. Otherwise, diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp index e78bf6b7266632..cf21b390087472 100644 --- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp +++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp @@ -2785,7 +2785,7 @@ bool HexagonInstrInfo::isValidAutoIncImm(const EVT VT, int Offset) const { } bool HexagonInstrInfo::isValidOffset(unsigned Opcode, int Offset, - const TargetRegisterInfo *TRI, bool Extend) const { + bool Extend) const { // This function is to check whether the "Offset" is in the correct range of // the given "Opcode". If "Offset" is not in the correct range, "A2_addi" is // inserted to calculate the final address. Due to this reason, the function @@ -2848,7 +2848,7 @@ bool HexagonInstrInfo::isValidOffset(unsigned Opcode, int Offset, case Hexagon::V6_vgathermhq_pseudo: case Hexagon::V6_vgathermwq_pseudo: case Hexagon::V6_vgathermhwq_pseudo: { - unsigned VectorSize = TRI->getSpillSize(Hexagon::HvxVRRegClass); + unsigned VectorSize = RegInfo.getSpillSize(Hexagon::HvxVRRegClass); assert(isPowerOf2_32(VectorSize)); if (Offset & (VectorSize-1)) return false; diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.h b/llvm/lib/Target/Hexagon/HexagonInstrInfo.h index 5e5c93b2b4ccb8..fa40614b465651 100644 --- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.h +++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.h @@ -423,8 +423,7 @@ class HexagonInstrInfo : public HexagonGenInstrInfo { const MachineInstr &MI2) const; bool isHVXVec(const MachineInstr &MI) const; bool isValidAutoIncImm(const EVT VT, const int Offset) const; - bool isValidOffset(unsigned Opcode, int Offset, - const TargetRegisterInfo *TRI, bool Extend = true) const; + bool isValidOffset(unsigned Opcode, int Offset, bool Extend = true) const; bool isVecAcc(const MachineInstr &MI) const; bool isVecALU(const MachineInstr &MI) const; bool isVecUsableNextPacket(const MachineInstr &ProdMI, diff --git a/llvm/lib/Target/Hexagon/HexagonOptAddrMode.cpp b/llvm/lib/Target/Hexagon/HexagonOptAddrMode.cpp index 7a4b51ad110827..9d9a919c95f9ad 100644 --- a/llvm/lib/Target/Hexagon/HexagonOptAddrMode.cpp +++ b/llvm/lib/Target/Hexagon/HexagonOptAddrMode.cpp @@ -364,13 +364,13 @@ bool HexagonOptAddrMode::isValidOffset(MachineInstr *MI, int Offset) { case Hexagon::V6_vgathermhq_pseudo: case Hexagon::V6_vgathermwq_pseudo: case Hexagon::V6_vgathermhwq_pseudo: - return HII->isValidOffset(MI->getOpcode(), Offset, HRI, false); + return HII->isValidOffset(MI->getOpcode(), Offset, false); default: if (HII->getAddrMode(*MI) == HexagonII::BaseImmOffset) { // The immediates are mentioned in multiples of vector counts unsigned AlignMask = HII->getMemAccessSize(*MI) - 1; if ((AlignMask & Offset) == 0) - return HII->isValidOffset(MI->getOpcode(), Offset, HRI, false); + return HII->isValidOffset(MI->getOpcode(), Offset, false); } return false; } @@ -399,7 +399,7 @@ bool HexagonOptAddrMode::isValidOffset(MachineInstr *MI, int Offset) { if ((AlignMask & Offset) != 0) return false; - return HII->isValidOffset(MI->getOpcode(), Offset, HRI, false); + return HII->isValidOffset(MI->getOpcode(), Offset, false); } unsigned HexagonOptAddrMode::getBaseOpPosition(MachineInstr *MI) { diff --git a/llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp b/llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp index 8797a38ef07356..cbfb31ca6c62fb 100644 --- a/llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp +++ b/llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp @@ -290,7 +290,7 @@ bool HexagonRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, break; } - if (!HII.isValidOffset(Opc, RealOffset, this)) { + if (!HII.isValidOffset(Opc, RealOffset)) { // If the offset is not valid, calculate the address in a temporary // register and use it with offset 0. int InstOffset = 0; diff --git a/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp b/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp index 8026a8a177e59c..ae50cd17ccb7af 100644 --- a/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp +++ b/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp @@ -475,7 +475,7 @@ bool HexagonPacketizerList::useCallersSP(MachineInstr &MI) { unsigned FrameSize = MF.getFrameInfo().getStackSize(); MachineOperand &Off = MI.getOperand(1); int64_t NewOff = Off.getImm() - (FrameSize + HEXAGON_LRFP_SIZE); - if (HII->isValidOffset(Opc, NewOff, HRI)) { + if (HII->isValidOffset(Opc, NewOff)) { Off.setImm(NewOff); return true; } @@ -526,7 +526,7 @@ bool HexagonPacketizerList::updateOffset(SUnit *SUI, SUnit *SUJ) { return false; int64_t Offset = MI.getOperand(OPI).getImm(); - if (!HII->isValidOffset(MI.getOpcode(), Offset+Incr, HRI)) + if (!HII->isValidOffset(MI.getOpcode(), Offset + Incr)) return false; MI.getOperand(OPI).setImm(Offset + Incr); diff --git a/llvm/lib/Target/Lanai/LanaiInstrInfo.cpp b/llvm/lib/Target/Lanai/LanaiInstrInfo.cpp index 33773023f66645..5612e137b6a974 100644 --- a/llvm/lib/Target/Lanai/LanaiInstrInfo.cpp +++ b/llvm/lib/Target/Lanai/LanaiInstrInfo.cpp @@ -99,13 +99,12 @@ bool LanaiInstrInfo::areMemAccessesTriviallyDisjoint( // base registers are identical, and the offset of a lower memory access + // the width doesn't overlap the offset of a higher memory access, // then the memory accesses are different. - const TargetRegisterInfo *TRI = &getRegisterInfo(); const MachineOperand *BaseOpA = nullptr, *BaseOpB = nullptr; int64_t OffsetA = 0, OffsetB = 0; LocationSize WidthA = LocationSize::precise(0), WidthB = LocationSize::precise(0); - if (getMemOperandWithOffsetWidth(MIa, BaseOpA, OffsetA, WidthA, TRI) && - getMemOperandWithOffsetWidth(MIb, BaseOpB, OffsetB, WidthB, TRI)) { + if (getMemOperandWithOffsetWidth(MIa, BaseOpA, OffsetA, WidthA) && + getMemOperandWithOffsetWidth(MIb, BaseOpB, OffsetB, WidthB)) { if (BaseOpA->isIdenticalTo(*BaseOpB)) { int LowOffset = std::min(OffsetA, OffsetB); int HighOffset = std::max(OffsetA, OffsetB); @@ -735,9 +734,10 @@ Register LanaiInstrInfo::isStoreToStackSlot(const MachineInstr &MI, return 0; } -bool LanaiInstrInfo::getMemOperandWithOffsetWidth( - const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset, - LocationSize &Width, const TargetRegisterInfo * /*TRI*/) const { +bool LanaiInstrInfo::getMemOperandWithOffsetWidth(const MachineInstr &LdSt, + const MachineOperand *&BaseOp, + int64_t &Offset, + LocationSize &Width) const { // Handle only loads/stores with base register followed by immediate offset // and with add as ALU op. if (LdSt.getNumOperands() != 4) @@ -793,8 +793,7 @@ bool LanaiInstrInfo::getMemOperandsWithOffsetWidth( case Lanai::LDBz_RI: const MachineOperand *BaseOp; OffsetIsScalable = false; - if (!getMemOperandWithOffsetWidth(LdSt, BaseOp, Offset, Width, - &getRegisterInfo())) + if (!getMemOperandWithOffsetWidth(LdSt, BaseOp, Offset, Width)) return false; BaseOps.push_back(BaseOp); return true; diff --git a/llvm/lib/Target/Lanai/LanaiInstrInfo.h b/llvm/lib/Target/Lanai/LanaiInstrInfo.h index 2ac81edf49fadc..a0c5a7f360a4ce 100644 --- a/llvm/lib/Target/Lanai/LanaiInstrInfo.h +++ b/llvm/lib/Target/Lanai/LanaiInstrInfo.h @@ -77,8 +77,7 @@ class LanaiInstrInfo : public LanaiGenInstrInfo { bool getMemOperandWithOffsetWidth(const MachineInstr &LdSt, const MachineOperand *&BaseOp, - int64_t &Offset, LocationSize &Width, - const TargetRegisterInfo *TRI) const; + int64_t &Offset, LocationSize &Width) const; std::pair<unsigned, unsigned> decomposeMachineOperandsTargetFlags(unsigned TF) const override; diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp index e8935ceae4fb3f..67b8f481dfcadf 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp +++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp @@ -2894,7 +2894,7 @@ bool PPCInstrInfo::getMemOperandsWithOffsetWidth( int64_t &Offset, bool &OffsetIsScalable, LocationSize &Width) const { const MachineOperand *BaseOp; OffsetIsScalable = false; - if (!getMemOperandWithOffsetWidth(LdSt, BaseOp, Offset, Width, &RI)) + if (!getMemOperandWithOffsetWidth(LdSt, BaseOp, Offset, Width)) return false; BaseOps.push_back(BaseOp); return true; @@ -2984,8 +2984,8 @@ bool PPCInstrInfo::shouldClusterMemOps( LocationSize Width1 = LocationSize::precise(0), Width2 = LocationSize::precise(0); const MachineOperand *Base1 = nullptr, *Base2 = nullptr; - if (!getMemOperandWithOffsetWidth(FirstLdSt, Base1, Offset1, Width1, &RI) || - !getMemOperandWithOffsetWidth(SecondLdSt, Base2, Offset2, Width2, &RI) || + if (!getMemOperandWithOffsetWidth(FirstLdSt, Base1, Offset1, Width1) || + !getMemOperandWithOffsetWidth(SecondLdSt, Base2, Offset2, Width2) || Width1 != Width2) return false; @@ -5821,9 +5821,10 @@ MachineInstr *PPCInstrInfo::findLoopInstr( // Return true if get the base operand, byte offset of an instruction and the // memory width. Width is the size of memory that is being loaded/stored. -bool PPCInstrInfo::getMemOperandWithOffsetWidth( - const MachineInstr &LdSt, const MachineOperand *&BaseReg, int64_t &Offset, - LocationSize &Width, const TargetRegisterInfo *TRI) const { +bool PPCInstrInfo::getMemOperandWithOffsetWidth(const MachineInstr &LdSt, + const MachineOperand *&BaseReg, + int64_t &Offset, + LocationSize &Width) const { if (!LdSt.mayLoadOrStore() || LdSt.getNumExplicitOperands() != 3) return false; @@ -5859,8 +5860,8 @@ bool PPCInstrInfo::areMemAccessesTriviallyDisjoint( int64_t OffsetA = 0, OffsetB = 0; LocationSize WidthA = LocationSize::precise(0), WidthB = LocationSize::precise(0); - if (getMemOperandWithOffsetWidth(MIa, BaseOpA, OffsetA, WidthA, &RI) && - getMemOperandWithOffsetWidth(MIb, BaseOpB, OffsetB, WidthB, &RI)) { + if (getMemOperandWithOffsetWidth(MIa, BaseOpA, OffsetA, WidthA) && + getMemOperandWithOffsetWidth(MIb, BaseOpB, OffsetB, WidthB)) { if (BaseOpA->isIdenticalTo(*BaseOpB)) { int LowOffset = std::min(OffsetA, OffsetB); int HighOffset = std::max(OffsetA, OffsetB); diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.h b/llvm/lib/Target/PowerPC/PPCInstrInfo.h index d86cf04facaff1..55fee0b8e14188 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrInfo.h +++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.h @@ -669,8 +669,7 @@ class PPCInstrInfo : public PPCGenInstrInfo { /// loaded/stored (e.g. 1, 2, 4, 8). bool getMemOperandWithOffsetWidth(const MachineInstr &LdSt, const MachineOperand *&BaseOp, - int64_t &Offset, LocationSize &Width, - const TargetRegisterInfo *TRI) const; + int64_t &Offset, LocationSize &Width) const; bool optimizeCmpPostRA(MachineInstr &MI) const; diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp index 293a2cc2dc7dcf..ad76c6e5daebdd 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp @@ -3595,8 +3595,7 @@ bool RISCVInstrInfo::getMemOperandsWithOffsetWidth( } const MachineOperand *BaseOp; OffsetIsScalable = false; - if (!getMemOperandWithOffsetWidth(LdSt, BaseOp, Offset, Width, - &getRegisterInfo())) + if (!getMemOperandWithOffsetWidth(LdSt, BaseOp, Offset, Width)) return false; BaseOps.push_back(BaseOp); return true; @@ -3671,7 +3670,7 @@ bool RISCVInstrInfo::shouldClusterMemOps( // function) and set it as appropriate. bool RISCVInstrInfo::getMemOperandWithOffsetWidth( const MachineInstr &LdSt, const MachineOperand *&BaseReg, int64_t &Offset, - LocationSize &Width, const TargetRegisterInfo *TRI) const { + LocationSize &Width) const { if (!LdSt.mayLoadOrStore()) return false; @@ -3707,13 +3706,12 @@ bool RISCVInstrInfo::areMemAccessesTriviallyDisjoint( // base registers are identical, and the offset of a lower memory access + // the width doesn't overlap the offset of a higher memory access, // then the memory accesses are different. - const TargetRegisterInfo *TRI = STI.getRegisterInfo(); const MachineOperand *BaseOpA = nullptr, *BaseOpB = nullptr; int64_t OffsetA = 0, OffsetB = 0; LocationSize WidthA = LocationSize::precise(0), WidthB = LocationSize::precise(0); - if (getMemOperandWithOffsetWidth(MIa, BaseOpA, OffsetA, WidthA, TRI) && - getMemOperandWithOffsetWidth(MIb, BaseOpB, OffsetB, WidthB, TRI)) { + if (getMemOperandWithOffsetWidth(MIa, BaseOpA, OffsetA, WidthA) && + getMemOperandWithOffsetWidth(MIb, BaseOpB, OffsetB, WidthB)) { if (BaseOpA->isIdenticalTo(*BaseOpB)) { int LowOffset = std::min(OffsetA, OffsetB); int HighOffset = std::max(OffsetA, OffsetB); diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.h b/llvm/lib/Target/RISCV/RISCVInstrInfo.h index 7cfb7f70521b58..091a40a4cd379c 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.h +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.h @@ -216,8 +216,7 @@ class RISCVInstrInfo : public RISCVGenInstrInfo { bool getMemOperandWithOffsetWidth(const MachineInstr &LdSt, const MachineOperand *&BaseOp, - int64_t &Offset, LocationSize &Width, - const TargetRegisterInfo *TRI) const; + int64_t &Offset, LocationSize &Width) const; bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb) const override; _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
