llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-backend-risc-v Author: llvmbot <details> <summary>Changes</summary> Backport 58d59f460cd740c50f66f782a87fa2a29f52ff25 Requested by: @<!-- -->asb --- Full diff: https://github.com/llvm/llvm-project/pull/228565.diff 2 Files Affected: - (modified) llvm/lib/Target/RISCV/RISCVISelLowering.cpp (+4) - (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-buildvec-of-binop.ll (+34) ``````````diff diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index a14637055c36e..64ffee698c11b 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -21247,6 +21247,10 @@ static SDValue performINSERT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG, return SDValue(); if (!isa<ConstantSDNode>(InValRHS) && !isa<ConstantFPSDNode>(InValRHS)) return SDValue(); + // This INSERT_VECTOR_ELT involves an implicit truncation, and sinking + // truncates through binops is non-trivial. + if (InVal.getValueType() != VT.getVectorElementType()) + return SDValue(); // FIXME: Return failure if the RHS type doesn't match the LHS. Shifts may // have different LHS and RHS types. if (InVec.getOperand(0).getValueType() != InVec.getOperand(1).getValueType()) diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-buildvec-of-binop.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-buildvec-of-binop.ll index a1ade4139fe51..0fb5ea38098a9 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-buildvec-of-binop.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-buildvec-of-binop.ll @@ -624,3 +624,37 @@ entry: %3 = insertelement <2 x i32> %2, i32 %1, i64 1 ret <2 x i32> %3 } + +; The scalar lshrs are performed on i32 and then implicitly truncated by the +; insert_vector_elt, so they must not be combined into a vector lshr on the i8 +; elements, which would truncate before the shift instead of after it. +define <8 x i8> @insert_elt_of_trunc_op(i32 %a) { +; CHECK-LABEL: insert_elt_of_trunc_op: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma +; CHECK-NEXT: vid.v v8 +; CHECK-NEXT: vmv.v.x v9, a0 +; CHECK-NEXT: vadd.vi v8, v8, 2 +; CHECK-NEXT: srli a1, a0, 8 +; CHECK-NEXT: vsrl.vv v8, v9, v8 +; CHECK-NEXT: vmv.s.x v9, a1 +; CHECK-NEXT: srli a0, a0, 9 +; CHECK-NEXT: vsetivli zero, 7, e8, mf2, tu, ma +; CHECK-NEXT: vslideup.vi v8, v9, 6 +; CHECK-NEXT: vmv.s.x v9, a0 +; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma +; CHECK-NEXT: vslideup.vi v8, v9, 7 +; CHECK-NEXT: ret +entry: + %b = trunc i32 %a to i8 + %s8 = lshr i32 %a, 8 + %s9 = lshr i32 %a, 9 + %t8 = trunc i32 %s8 to i8 + %t9 = trunc i32 %s9 to i8 + %v0 = insertelement <8 x i8> poison, i8 %b, i64 0 + %v1 = shufflevector <8 x i8> %v0, <8 x i8> poison, <8 x i32> zeroinitializer + %v2 = lshr <8 x i8> %v1, <i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 poison, i8 poison> + %v3 = insertelement <8 x i8> %v2, i8 %t8, i64 6 + %v4 = insertelement <8 x i8> %v3, i8 %t9, i64 7 + ret <8 x i8> %v4 +} `````````` </details> https://github.com/llvm/llvm-project/pull/228565 _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
