https://github.com/llvmbot created https://github.com/llvm/llvm-project/pull/228913
Backport 9870703 Requested by: @folkertdev >From b1cbbe2118f2e283599079c0269663260d3a5a3d Mon Sep 17 00:00:00 2001 From: Folkert de Vries <[email protected]> Date: Sun, 4 Oct 2026 17:43:37 +0200 Subject: [PATCH] [Loongarch] fix int to float conversion on non-MVT vector types (#228896) fixes https://github.com/llvm/llvm-project/issues/228894 The code added in https://github.com/llvm/llvm-project/pull/202496 can construct an invalid MVT (e.g. a 5-element vector, which is not something any architecture has a specific register for). So, instead use an `EVT` which is less restrictive. (cherry picked from commit 9870703eb8e7fe5799abe68d0b8fee29e5bf504d) --- .../LoongArch/LoongArchISelLowering.cpp | 2 +- .../LoongArch/lasx/ir-instruction/sitofp.ll | 31 ++++++++++ .../LoongArch/lasx/ir-instruction/uitofp.ll | 31 ++++++++++ .../LoongArch/lsx/ir-instruction/sitofp.ll | 54 ++++++++++++++++++ .../LoongArch/lsx/ir-instruction/uitofp.ll | 56 ++++++++++++++++++- 5 files changed, 171 insertions(+), 3 deletions(-) diff --git a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp index 4a6bd1e2aa96a..675fa046a7011 100644 --- a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp +++ b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp @@ -8200,7 +8200,7 @@ static SDValue ExtendSrcToDst(SDNode *N, SelectionDAG &DAG, unsigned ExtendOp) { return SDValue(); MVT WidenEltVT = MVT::getIntegerVT(DstEltBits); - MVT WidenSrcVT = MVT::getVectorVT(WidenEltVT, DstElts); + EVT WidenSrcVT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, DstElts); SDValue Extend = DAG.getNode(ExtendOp, DL, WidenSrcVT, Src); return DAG.getNode(N->getOpcode(), DL, VT, Extend); diff --git a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/sitofp.ll b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/sitofp.ll index b0cbc6e34192c..94410e2f4cf66 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/sitofp.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/sitofp.ll @@ -190,3 +190,34 @@ define <4 x double> @sitofp_v16i8_v4f64(<16 x i8> %a) { %shuf = shufflevector <16 x double> %cvt, <16 x double> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3> ret <4 x double> %shuf } + +define <5 x double> @sitofp_v5i32_v5f64(<5 x i32> %a) { +; CHECK-LABEL: sitofp_v5i32_v5f64: +; CHECK: # %bb.0: +; CHECK-NEXT: xvpermi.q $xr1, $xr0, 1 +; CHECK-NEXT: vext2xv.d.w $xr1, $xr1 +; CHECK-NEXT: xvffint.d.l $xr1, $xr1 +; CHECK-NEXT: vext2xv.d.w $xr0, $xr0 +; CHECK-NEXT: xvffint.d.l $xr0, $xr0 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: xvstelm.d $xr1, $a0, 32, 0 +; CHECK-NEXT: ret + %v = sitofp <5 x i32> %a to <5 x double> + ret <5 x double> %v +} + +define <7 x double> @sitofp_v7i32_v7f64(<7 x i32> %a) { +; CHECK-LABEL: sitofp_v7i32_v7f64: +; CHECK: # %bb.0: +; CHECK-NEXT: xvpermi.q $xr1, $xr0, 1 +; CHECK-NEXT: vext2xv.d.w $xr1, $xr1 +; CHECK-NEXT: xvffint.d.l $xr1, $xr1 +; CHECK-NEXT: vext2xv.d.w $xr0, $xr0 +; CHECK-NEXT: xvffint.d.l $xr0, $xr0 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: xvstelm.d $xr1, $a0, 48, 2 +; CHECK-NEXT: vst $vr1, $a0, 32 +; CHECK-NEXT: ret + %v = sitofp <7 x i32> %a to <7 x double> + ret <7 x double> %v +} diff --git a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/uitofp.ll b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/uitofp.ll index 340e45dbfdb84..e6f4db627709c 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/uitofp.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/uitofp.ll @@ -117,3 +117,34 @@ define <4 x double> @uitofp_v16i8_v4f64(<16 x i8> %a) { %shuf = shufflevector <16 x double> %cvt, <16 x double> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3> ret <4 x double> %shuf } + +define <5 x double> @uitofp_v5i32_v5f64(<5 x i32> %a) { +; CHECK-LABEL: uitofp_v5i32_v5f64: +; CHECK: # %bb.0: +; CHECK-NEXT: xvpermi.q $xr1, $xr0, 1 +; CHECK-NEXT: vext2xv.du.wu $xr1, $xr1 +; CHECK-NEXT: xvffint.d.l $xr1, $xr1 +; CHECK-NEXT: vext2xv.du.wu $xr0, $xr0 +; CHECK-NEXT: xvffint.d.l $xr0, $xr0 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: xvstelm.d $xr1, $a0, 32, 0 +; CHECK-NEXT: ret + %v = uitofp <5 x i32> %a to <5 x double> + ret <5 x double> %v +} + +define <7 x double> @uitofp_v7i32_v7f64(<7 x i32> %a) { +; CHECK-LABEL: uitofp_v7i32_v7f64: +; CHECK: # %bb.0: +; CHECK-NEXT: xvpermi.q $xr1, $xr0, 1 +; CHECK-NEXT: vext2xv.du.wu $xr1, $xr1 +; CHECK-NEXT: xvffint.d.l $xr1, $xr1 +; CHECK-NEXT: vext2xv.du.wu $xr0, $xr0 +; CHECK-NEXT: xvffint.d.l $xr0, $xr0 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: xvstelm.d $xr1, $a0, 48, 2 +; CHECK-NEXT: vst $vr1, $a0, 32 +; CHECK-NEXT: ret + %v = uitofp <7 x i32> %a to <7 x double> + ret <7 x double> %v +} diff --git a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/sitofp.ll b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/sitofp.ll index a3b5a17622114..d6177d5ca0969 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/sitofp.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/sitofp.ll @@ -226,3 +226,57 @@ define <4 x double> @sitofp_v16i8_v4f64(<16 x i8> %a) { %shuf = shufflevector <16 x double> %cvt, <16 x double> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3> ret <4 x double> %shuf } + +define <5 x double> @sitofp_v5i32_v5f64(<5 x i32> %a) { +; LA32-LABEL: sitofp_v5i32_v5f64: +; LA32: # %bb.0: +; LA32-NEXT: ld.w $a2, $a1, 16 +; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 0 +; LA32-NEXT: ld.w $a2, $a1, 0 +; LA32-NEXT: ld.w $a3, $a1, 4 +; LA32-NEXT: ld.w $a4, $a1, 8 +; LA32-NEXT: ld.w $a1, $a1, 12 +; LA32-NEXT: vinsgr2vr.w $vr1, $a2, 0 +; LA32-NEXT: vinsgr2vr.w $vr1, $a3, 1 +; LA32-NEXT: vinsgr2vr.w $vr1, $a4, 2 +; LA32-NEXT: vinsgr2vr.w $vr1, $a1, 3 +; LA32-NEXT: vslti.w $vr2, $vr1, 0 +; LA32-NEXT: vilvl.w $vr3, $vr2, $vr1 +; LA32-NEXT: vffint.d.l $vr3, $vr3 +; LA32-NEXT: vilvh.w $vr1, $vr2, $vr1 +; LA32-NEXT: vffint.d.l $vr1, $vr1 +; LA32-NEXT: vslti.w $vr2, $vr0, 0 +; LA32-NEXT: vilvl.w $vr0, $vr2, $vr0 +; LA32-NEXT: vffint.d.l $vr0, $vr0 +; LA32-NEXT: vstelm.d $vr0, $a0, 32, 0 +; LA32-NEXT: vst $vr1, $a0, 16 +; LA32-NEXT: vst $vr3, $a0, 0 +; LA32-NEXT: ret +; +; LA64-LABEL: sitofp_v5i32_v5f64: +; LA64: # %bb.0: +; LA64-NEXT: ld.w $a2, $a1, 32 +; LA64-NEXT: vinsgr2vr.w $vr0, $a2, 0 +; LA64-NEXT: ld.w $a2, $a1, 0 +; LA64-NEXT: ld.w $a3, $a1, 8 +; LA64-NEXT: ld.w $a4, $a1, 16 +; LA64-NEXT: ld.w $a1, $a1, 24 +; LA64-NEXT: vinsgr2vr.w $vr1, $a2, 0 +; LA64-NEXT: vinsgr2vr.w $vr1, $a3, 1 +; LA64-NEXT: vinsgr2vr.w $vr1, $a4, 2 +; LA64-NEXT: vinsgr2vr.w $vr1, $a1, 3 +; LA64-NEXT: vslti.w $vr2, $vr1, 0 +; LA64-NEXT: vilvl.w $vr3, $vr2, $vr1 +; LA64-NEXT: vffint.d.l $vr3, $vr3 +; LA64-NEXT: vilvh.w $vr1, $vr2, $vr1 +; LA64-NEXT: vffint.d.l $vr1, $vr1 +; LA64-NEXT: vslti.w $vr2, $vr0, 0 +; LA64-NEXT: vilvl.w $vr0, $vr2, $vr0 +; LA64-NEXT: vffint.d.l $vr0, $vr0 +; LA64-NEXT: vstelm.d $vr0, $a0, 32, 0 +; LA64-NEXT: vst $vr1, $a0, 16 +; LA64-NEXT: vst $vr3, $a0, 0 +; LA64-NEXT: ret + %v = sitofp <5 x i32> %a to <5 x double> + ret <5 x double> %v +} diff --git a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/uitofp.ll b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/uitofp.ll index 6d7a1b1554563..dd526904af415 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/uitofp.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/uitofp.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3 -; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s -; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA32 +; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA64 define void @uitofp_v4i32_v4f32(ptr %res, ptr %in){ ; CHECK-LABEL: uitofp_v4i32_v4f32: @@ -87,3 +87,55 @@ define <4 x double> @uitofp_v16i8_v4f64(<16 x i8> %a) { %shuf = shufflevector <16 x double> %cvt, <16 x double> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3> ret <4 x double> %shuf } + +define <5 x double> @uitofp_v5i32_v5f64(<5 x i32> %a) { +; LA32-LABEL: uitofp_v5i32_v5f64: +; LA32: # %bb.0: +; LA32-NEXT: ld.w $a2, $a1, 16 +; LA32-NEXT: ld.w $a3, $a1, 0 +; LA32-NEXT: ld.w $a4, $a1, 4 +; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 0 +; LA32-NEXT: vinsgr2vr.w $vr1, $a3, 0 +; LA32-NEXT: vinsgr2vr.w $vr1, $a4, 1 +; LA32-NEXT: ld.w $a2, $a1, 12 +; LA32-NEXT: ld.w $a1, $a1, 8 +; LA32-NEXT: vrepli.b $vr2, 0 +; LA32-NEXT: vilvl.w $vr1, $vr2, $vr1 +; LA32-NEXT: vffint.d.lu $vr1, $vr1 +; LA32-NEXT: vinsgr2vr.w $vr3, $a1, 0 +; LA32-NEXT: vinsgr2vr.w $vr3, $a2, 1 +; LA32-NEXT: vilvl.w $vr3, $vr2, $vr3 +; LA32-NEXT: vffint.d.lu $vr3, $vr3 +; LA32-NEXT: vilvl.w $vr0, $vr2, $vr0 +; LA32-NEXT: vffint.d.lu $vr0, $vr0 +; LA32-NEXT: vstelm.d $vr0, $a0, 32, 0 +; LA32-NEXT: vst $vr3, $a0, 16 +; LA32-NEXT: vst $vr1, $a0, 0 +; LA32-NEXT: ret +; +; LA64-LABEL: uitofp_v5i32_v5f64: +; LA64: # %bb.0: +; LA64-NEXT: ld.w $a2, $a1, 32 +; LA64-NEXT: ld.w $a3, $a1, 0 +; LA64-NEXT: ld.w $a4, $a1, 8 +; LA64-NEXT: vinsgr2vr.w $vr0, $a2, 0 +; LA64-NEXT: vinsgr2vr.w $vr1, $a3, 0 +; LA64-NEXT: vinsgr2vr.w $vr1, $a4, 1 +; LA64-NEXT: ld.w $a2, $a1, 24 +; LA64-NEXT: ld.w $a1, $a1, 16 +; LA64-NEXT: vrepli.b $vr2, 0 +; LA64-NEXT: vilvl.w $vr1, $vr2, $vr1 +; LA64-NEXT: vffint.d.lu $vr1, $vr1 +; LA64-NEXT: vinsgr2vr.w $vr3, $a1, 0 +; LA64-NEXT: vinsgr2vr.w $vr3, $a2, 1 +; LA64-NEXT: vilvl.w $vr3, $vr2, $vr3 +; LA64-NEXT: vffint.d.lu $vr3, $vr3 +; LA64-NEXT: vilvl.w $vr0, $vr2, $vr0 +; LA64-NEXT: vffint.d.lu $vr0, $vr0 +; LA64-NEXT: vstelm.d $vr0, $a0, 32, 0 +; LA64-NEXT: vst $vr3, $a0, 16 +; LA64-NEXT: vst $vr1, $a0, 0 +; LA64-NEXT: ret + %v = uitofp <5 x i32> %a to <5 x double> + ret <5 x double> %v +} _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
