https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/229063
>From f52f9915aa7cb44ff2a93be5a2cdc916d8fa3ec1 Mon Sep 17 00:00:00 2001 From: Matt Arsenault <[email protected]> Date: Mon, 5 Oct 2026 14:01:49 +0200 Subject: [PATCH] SystemZ: Don't convert AND to RISBG if CC is live The RISBG-type replacements either don't define CC or set it with different semantics, so the conversion dropped or clobbered a CC value that was still used. Co-authored-by: Claude Opus 5.5 <[email protected]> --- llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp | 2 + .../twoaddr-risbg-cc-liveintervals.mir | 59 +++++++++++++++++++ 2 files changed, 61 insertions(+) diff --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp b/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp index bef2937bf1ba4..fd7160a00ff83 100644 --- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp +++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp @@ -1089,6 +1089,8 @@ SystemZInstrInfo::convertToThreeAddress(MachineInstr &MI, // Try to convert an AND into an RISBG-type instruction. // TODO: It might be beneficial to select RISBG and shorten to AND instead. if (LogicOp And = interpretAndImmediate(MI.getOpcode())) { + if (!MI.registerDefIsDead(SystemZ::CC, /*TRI=*/nullptr)) + return nullptr; uint64_t Imm = MI.getOperand(2).getImm() << And.ImmLSB; // AND IMMEDIATE leaves the other bits of the register unchanged. Imm |= allOnes(And.RegSize) & ~(allOnes(And.ImmSize) << And.ImmLSB); diff --git a/llvm/test/CodeGen/SystemZ/twoaddr-risbg-cc-liveintervals.mir b/llvm/test/CodeGen/SystemZ/twoaddr-risbg-cc-liveintervals.mir index 4e789263173d6..575dd2a0760a9 100644 --- a/llvm/test/CodeGen/SystemZ/twoaddr-risbg-cc-liveintervals.mir +++ b/llvm/test/CodeGen/SystemZ/twoaddr-risbg-cc-liveintervals.mir @@ -88,3 +88,62 @@ body: | $r3d = COPY %1 Return implicit $r2d, implicit $r3d ... + +# Don't convert if CC is live out of the AND. +--- +name: and_32_live_cc +tracksRegLiveness: true +body: | + bb.0: + liveins: $r2d, $r3l, $r4l, $r5l + + ; Z196-LABEL: name: and_32_live_cc + ; Z196: liveins: $r2d, $r3l, $r4l, $r5l + ; Z196-NEXT: {{ $}} + ; Z196-NEXT: [[COPY:%[0-9]+]]:gr64bit = COPY $r2d + ; Z196-NEXT: [[COPY1:%[0-9]+]]:grx32bit = COPY $r3l + ; Z196-NEXT: [[COPY2:%[0-9]+]]:gr32bit = COPY $r4l + ; Z196-NEXT: [[COPY3:%[0-9]+]]:gr32bit = COPY $r5l + ; Z196-NEXT: dead [[LOCGR:%[0-9]+]]:gr64bit = LOCGR undef [[LOCGR]], [[COPY]], 15, 8, implicit undef $cc + ; Z196-NEXT: [[COPY4:%[0-9]+]]:gr64bit = COPY [[COPY]] + ; Z196-NEXT: dead [[COPY4:%[0-9]+]]:gr64bit = LOCGR [[COPY4]], undef %5:gr64bit, 15, 8, implicit undef $cc + ; Z196-NEXT: [[COPY5:%[0-9]+]]:grx32bit = COPY [[COPY1]] + ; Z196-NEXT: [[COPY5:%[0-9]+]]:grx32bit = NIFMux [[COPY5]], 1, implicit-def $cc + ; Z196-NEXT: [[COPY6:%[0-9]+]]:gr32bit = COPY [[COPY2]] + ; Z196-NEXT: [[COPY6:%[0-9]+]]:gr32bit = LOCR [[COPY6]], [[COPY3]], 15, 8, implicit $cc + ; Z196-NEXT: $r2l = COPY [[COPY5]] + ; Z196-NEXT: $r3l = COPY [[COPY1]] + ; Z196-NEXT: $r4l = COPY [[COPY6]] + ; Z196-NEXT: Return implicit $r2l, implicit $r3l, implicit $r4l + ; + ; ZEC12-LABEL: name: and_32_live_cc + ; ZEC12: liveins: $r2d, $r3l, $r4l, $r5l + ; ZEC12-NEXT: {{ $}} + ; ZEC12-NEXT: [[COPY:%[0-9]+]]:gr64bit = COPY $r2d + ; ZEC12-NEXT: [[COPY1:%[0-9]+]]:grx32bit = COPY $r3l + ; ZEC12-NEXT: [[COPY2:%[0-9]+]]:gr32bit = COPY $r4l + ; ZEC12-NEXT: [[COPY3:%[0-9]+]]:gr32bit = COPY $r5l + ; ZEC12-NEXT: dead [[LOCGR:%[0-9]+]]:gr64bit = LOCGR undef [[LOCGR]], [[COPY]], 15, 8, implicit undef $cc + ; ZEC12-NEXT: [[COPY4:%[0-9]+]]:gr64bit = COPY [[COPY]] + ; ZEC12-NEXT: dead [[COPY4:%[0-9]+]]:gr64bit = LOCGR [[COPY4]], undef %5:gr64bit, 15, 8, implicit undef $cc + ; ZEC12-NEXT: [[COPY5:%[0-9]+]]:grx32bit = COPY [[COPY1]] + ; ZEC12-NEXT: [[COPY5:%[0-9]+]]:grx32bit = NIFMux [[COPY5]], 1, implicit-def $cc + ; ZEC12-NEXT: [[COPY6:%[0-9]+]]:gr32bit = COPY [[COPY2]] + ; ZEC12-NEXT: [[COPY6:%[0-9]+]]:gr32bit = LOCR [[COPY6]], [[COPY3]], 15, 8, implicit $cc + ; ZEC12-NEXT: $r2l = COPY [[COPY5]] + ; ZEC12-NEXT: $r3l = COPY [[COPY1]] + ; ZEC12-NEXT: $r4l = COPY [[COPY6]] + ; ZEC12-NEXT: Return implicit $r2l, implicit $r3l, implicit $r4l + %0:gr64bit = COPY $r2d + %1:grx32bit = COPY $r3l + %2:gr32bit = COPY $r4l + %3:gr32bit = COPY $r5l + %4:gr64bit = LOCGR %0, undef %5:gr64bit, 15, 8, implicit undef $cc + %6:gr64bit = LOCGR undef %5, %0, 15, 8, implicit undef $cc + %7:grx32bit = NIFMux %1, 1, implicit-def $cc + %8:gr32bit = LOCR %2, %3, 15, 8, implicit killed $cc + $r2l = COPY %7 + $r3l = COPY %1 + $r4l = COPY %8 + Return implicit $r2l, implicit $r3l, implicit $r4l +... _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
