Author: Simon Pilgrim Date: 2026-10-06T09:38:43+02:00 New Revision: c06551266dbf86caca71c9b1a199bcf2c7aa287e
URL: https://github.com/llvm/llvm-project/commit/c06551266dbf86caca71c9b1a199bcf2c7aa287e DIFF: https://github.com/llvm/llvm-project/commit/c06551266dbf86caca71c9b1a199bcf2c7aa287e.diff LOG: [X86] combineConcatVectorOps - ensure all suboperand concatenation types are simple (#228522) Fixes #228264 (cherry picked from commit 2d91fec6daa9f64add1dcef41454b5066a208731) Added: Modified: llvm/lib/Target/X86/X86ISelLowering.cpp llvm/test/CodeGen/X86/vector-trunc.ll Removed: ################################################################################ diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 9804cd78a8e69..8b48e9c8b0eca 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -60369,16 +60369,18 @@ static SDValue combineConcatVectorOps(const SDLoc &DL, MVT VT, // Attempt to peek through bitcasts and concat the original subvectors. EVT SubVT = peekThroughBitcasts(Subs[0]).getValueType(); if (SubVT.isSimple() && SubVT.isVector()) { - MVT ConcatVT = - MVT::getVectorVT(SubVT.getSimpleVT().getScalarType(), - SubVT.getVectorElementCount() * Subs.size()); - for (SDValue &Sub : Subs) - Sub = DAG.getBitcast(SubVT, Sub); - if (SDValue ConcatSrc = combineConcatVectorOps(DL, ConcatVT, Subs, DAG, - Subtarget, Depth + 1)) - return DAG.getBitcast(VT, ConcatSrc); - return DAG.getBitcast( - VT, DAG.getNode(ISD::CONCAT_VECTORS, DL, ConcatVT, Subs)); + EVT ConcatVT = EVT::getVectorVT( + *DAG.getContext(), SubVT.getSimpleVT().getScalarType(), + SubVT.getVectorElementCount() * Subs.size()); + if (ConcatVT.isSimple()) { + for (SDValue &Sub : Subs) + Sub = DAG.getBitcast(SubVT, Sub); + if (SDValue ConcatSrc = combineConcatVectorOps( + DL, ConcatVT.getSimpleVT(), Subs, DAG, Subtarget, Depth + 1)) + return DAG.getBitcast(VT, ConcatSrc); + return DAG.getBitcast( + VT, DAG.getNode(ISD::CONCAT_VECTORS, DL, ConcatVT, Subs)); + } } return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Subs); }; diff --git a/llvm/test/CodeGen/X86/vector-trunc.ll b/llvm/test/CodeGen/X86/vector-trunc.ll index 5dfb37f5ca40b..c5f678d211383 100644 --- a/llvm/test/CodeGen/X86/vector-trunc.ll +++ b/llvm/test/CodeGen/X86/vector-trunc.ll @@ -2072,6 +2072,55 @@ entry: } declare i16 @llvm.vector.reduce.add.v16i16(<16 x i16>) +define <4 x i64> @PR228264(<2 x i128> %a, <2 x i128> %b) { +; SSE-LABEL: PR228264: +; SSE: # %bb.0: +; SSE-NEXT: movq %r8, %xmm0 +; SSE-NEXT: movq {{.*#+}} xmm1 = mem[0],zero +; SSE-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0] +; SSE-NEXT: movq %rdx, %xmm2 +; SSE-NEXT: movq %rdi, %xmm1 +; SSE-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0] +; SSE-NEXT: retq +; +; AVX1-LABEL: PR228264: +; AVX1: # %bb.0: +; AVX1-NEXT: vmovq %rdx, %xmm0 +; AVX1-NEXT: vmovq %rdi, %xmm1 +; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0] +; AVX1-NEXT: vmovq %r8, %xmm1 +; AVX1-NEXT: vmovq {{.*#+}} xmm2 = mem[0],zero +; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0] +; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 +; AVX1-NEXT: retq +; +; AVX2-LABEL: PR228264: +; AVX2: # %bb.0: +; AVX2-NEXT: vmovq %rdx, %xmm0 +; AVX2-NEXT: vmovq %rdi, %xmm1 +; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0] +; AVX2-NEXT: vmovq %r8, %xmm1 +; AVX2-NEXT: vmovq {{.*#+}} xmm2 = mem[0],zero +; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0] +; AVX2-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm0 +; AVX2-NEXT: retq +; +; AVX512-LABEL: PR228264: +; AVX512: # %bb.0: +; AVX512-NEXT: vmovq %rdx, %xmm0 +; AVX512-NEXT: vmovq %rdi, %xmm1 +; AVX512-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0] +; AVX512-NEXT: vmovq %r8, %xmm1 +; AVX512-NEXT: vmovq {{.*#+}} xmm2 = mem[0],zero +; AVX512-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0] +; AVX512-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm0 +; AVX512-NEXT: retq + %lo_b = trunc <2 x i128> %b to <2 x i64> + %lo_a = trunc <2 x i128> %a to <2 x i64> + %result = shufflevector <2 x i64> %lo_b, <2 x i64> %lo_a, <4 x i32> <i32 0, i32 1, i32 2, i32 3> + ret <4 x i64> %result +} + ; Store merging must not infinitely fight store splitting. define void @store_merge_split(<8 x i32> %w1, <8 x i32> %w2, i64 %idx, ptr %p) align 2 { _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
