https://github.com/lukel97 updated https://github.com/llvm/llvm-project/pull/230056
>From 35b7694d964c1c6f89c56fcaf68cb88b49f4c2e1 Mon Sep 17 00:00:00 2001 From: Luke Lau <[email protected]> Date: Thu, 8 Oct 2026 11:41:21 +0100 Subject: [PATCH 1/3] [DAG] Explicitly truncate splat operand in get_active_lane_mask expansion x86 can't handle the implicit truncation of build_vector operands so the whilewr_8 test case crashes after expanding get_active_lane_mask (stemming from llvm.loop.dependence.war.mask). Fix it by explicitly truncating it. --- .../CodeGen/SelectionDAG/TargetLowering.cpp | 1 + llvm/test/CodeGen/X86/alias_mask.ll | 26 +++++++++++++++++++ 2 files changed, 27 insertions(+) create mode 100644 llvm/test/CodeGen/X86/alias_mask.ll diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp index 55f695a2d0d46f..95f4a094e01463 100644 --- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp @@ -11522,6 +11522,7 @@ SDValue TargetLowering::expandGetActiveLaneMask(SDNode *N, DL, OpVT); End = DAG.getNode(ISD::USUBSAT, DL, OpVT, End, Start); End = DAG.getNode(ISD::UMIN, DL, OpVT, End, Max); + End = DAG.getZExtOrTrunc(End, DL, StepVector.getValueType().getScalarType()); // cmp <0, 1, 2, 3...>, End SDValue EndV = DAG.getSplat(StepVector.getValueType(), DL, End); diff --git a/llvm/test/CodeGen/X86/alias_mask.ll b/llvm/test/CodeGen/X86/alias_mask.ll new file mode 100644 index 00000000000000..c092643f80a8c6 --- /dev/null +++ b/llvm/test/CodeGen/X86/alias_mask.ll @@ -0,0 +1,26 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 +; RUN: llc -mtriple=x86_64 < %s | FileCheck %s + +define <16 x i1> @whilewr_8(i64 %a, i64 %b) { +; CHECK-LABEL: whilewr_8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: subq %rdi, %rsi +; CHECK-NEXT: movq $-1, %rax +; CHECK-NEXT: cmovaq %rsi, %rax +; CHECK-NEXT: cmpq $255, %rax +; CHECK-NEXT: movl $255, %ecx +; CHECK-NEXT: cmovbq %rax, %rcx +; CHECK-NEXT: movd %ecx, %xmm0 +; CHECK-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] +; CHECK-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,0,0,0,4,5,6,7] +; CHECK-NEXT: pshufd {{.*#+}} xmm1 = xmm0[0,1,0,1] +; CHECK-NEXT: movdqa {{.*#+}} xmm0 = [0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15] +; CHECK-NEXT: pmaxub %xmm0, %xmm1 +; CHECK-NEXT: pcmpeqb %xmm0, %xmm1 +; CHECK-NEXT: pcmpeqd %xmm0, %xmm0 +; CHECK-NEXT: pxor %xmm1, %xmm0 +; CHECK-NEXT: retq +entry: + %0 = call <16 x i1> @llvm.loop.dependence.war.mask.v16i1.i64(i64 %a, i64 %b, i64 1) + ret <16 x i1> %0 +} >From 63e1060ae9ea744626db7c02dce2aa1da26501dc Mon Sep 17 00:00:00 2001 From: Luke Lau <[email protected]> Date: Thu, 8 Oct 2026 22:39:42 +0100 Subject: [PATCH 2/3] Use mask-beforefirst to test expansion --- llvm/test/CodeGen/X86/alias_mask.ll | 26 -- llvm/test/CodeGen/X86/mask-beforefirst.ll | 310 +++++++++++++++++++++- 2 files changed, 301 insertions(+), 35 deletions(-) delete mode 100644 llvm/test/CodeGen/X86/alias_mask.ll diff --git a/llvm/test/CodeGen/X86/alias_mask.ll b/llvm/test/CodeGen/X86/alias_mask.ll deleted file mode 100644 index c092643f80a8c6..00000000000000 --- a/llvm/test/CodeGen/X86/alias_mask.ll +++ /dev/null @@ -1,26 +0,0 @@ -; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 -; RUN: llc -mtriple=x86_64 < %s | FileCheck %s - -define <16 x i1> @whilewr_8(i64 %a, i64 %b) { -; CHECK-LABEL: whilewr_8: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: subq %rdi, %rsi -; CHECK-NEXT: movq $-1, %rax -; CHECK-NEXT: cmovaq %rsi, %rax -; CHECK-NEXT: cmpq $255, %rax -; CHECK-NEXT: movl $255, %ecx -; CHECK-NEXT: cmovbq %rax, %rcx -; CHECK-NEXT: movd %ecx, %xmm0 -; CHECK-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] -; CHECK-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,0,0,0,4,5,6,7] -; CHECK-NEXT: pshufd {{.*#+}} xmm1 = xmm0[0,1,0,1] -; CHECK-NEXT: movdqa {{.*#+}} xmm0 = [0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15] -; CHECK-NEXT: pmaxub %xmm0, %xmm1 -; CHECK-NEXT: pcmpeqb %xmm0, %xmm1 -; CHECK-NEXT: pcmpeqd %xmm0, %xmm0 -; CHECK-NEXT: pxor %xmm1, %xmm0 -; CHECK-NEXT: retq -entry: - %0 = call <16 x i1> @llvm.loop.dependence.war.mask.v16i1.i64(i64 %a, i64 %b, i64 1) - ret <16 x i1> %0 -} diff --git a/llvm/test/CodeGen/X86/mask-beforefirst.ll b/llvm/test/CodeGen/X86/mask-beforefirst.ll index 000674d6974b8d..35b472eed82424 100644 --- a/llvm/test/CodeGen/X86/mask-beforefirst.ll +++ b/llvm/test/CodeGen/X86/mask-beforefirst.ll @@ -1,6 +1,292 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 -; RUN: llc < %s -mtriple=x86_64 | FileCheck %s --check-prefix=SSE2 -; RUN: llc < %s -mtriple=x86_64 -mattr=+avx512f | FileCheck %s --check-prefix=AVX512 +; RUN: llc < %s -mtriple=x86_64 -mcpu=x86-64 | FileCheck %s --check-prefixes=SSE2 +; RUN: llc < %s -mtriple=x86_64 -mcpu=x86-64-v2 | FileCheck %s --check-prefixes=SSE42 +; RUN: llc < %s -mtriple=x86_64 -mcpu=x86-64-v3 | FileCheck %s --check-prefixes=AVX2 +; TODO: Fix crash on AVX512 +; llc < %s -mtriple=x86_64 -mcpu=x86-64-v4 | FileCheck %s --check-prefixes=AVX512 + +define <16 x i1> @v16i1(<16 x i1> %m) { +; SSE2-LABEL: v16i1: +; SSE2: # %bb.0: +; SSE2-NEXT: psllw $7, %xmm0 +; SSE2-NEXT: pxor %xmm1, %xmm1 +; SSE2-NEXT: pcmpgtb %xmm0, %xmm1 +; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 +; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm1[2,3,2,3] +; SSE2-NEXT: pmaxub %xmm1, %xmm0 +; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,1,1] +; SSE2-NEXT: pmaxub %xmm0, %xmm1 +; SSE2-NEXT: movdqa %xmm1, %xmm0 +; SSE2-NEXT: psrld $16, %xmm0 +; SSE2-NEXT: pmaxub %xmm1, %xmm0 +; SSE2-NEXT: movdqa %xmm0, %xmm1 +; SSE2-NEXT: psrlw $8, %xmm1 +; SSE2-NEXT: pmaxub %xmm0, %xmm1 +; SSE2-NEXT: movd %xmm1, %eax +; SSE2-NEXT: movb $16, %cl +; SSE2-NEXT: subb %al, %cl +; SSE2-NEXT: movzbl %cl, %eax +; SSE2-NEXT: movd %eax, %xmm0 +; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] +; SSE2-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,0,0,0,4,5,6,7] +; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[0,1,0,1] +; SSE2-NEXT: movdqa {{.*#+}} xmm0 = [0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15] +; SSE2-NEXT: pmaxub %xmm0, %xmm1 +; SSE2-NEXT: pcmpeqb %xmm0, %xmm1 +; SSE2-NEXT: pcmpeqd %xmm0, %xmm0 +; SSE2-NEXT: pxor %xmm1, %xmm0 +; SSE2-NEXT: retq +; +; SSE42-LABEL: v16i1: +; SSE42: # %bb.0: +; SSE42-NEXT: psllw $7, %xmm0 +; SSE42-NEXT: pxor %xmm1, %xmm1 +; SSE42-NEXT: pxor %xmm2, %xmm2 +; SSE42-NEXT: pcmpgtb %xmm0, %xmm2 +; SSE42-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2 +; SSE42-NEXT: pcmpeqd %xmm3, %xmm3 +; SSE42-NEXT: pxor %xmm3, %xmm2 +; SSE42-NEXT: movdqa %xmm2, %xmm0 +; SSE42-NEXT: psrlw $8, %xmm0 +; SSE42-NEXT: pminub %xmm2, %xmm0 +; SSE42-NEXT: phminposuw %xmm0, %xmm0 +; SSE42-NEXT: movd %xmm0, %eax +; SSE42-NEXT: addb $17, %al +; SSE42-NEXT: movzbl %al, %eax +; SSE42-NEXT: movd %eax, %xmm0 +; SSE42-NEXT: pshufb %xmm1, %xmm0 +; SSE42-NEXT: movdqa {{.*#+}} xmm1 = [0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15] +; SSE42-NEXT: pmaxub %xmm1, %xmm0 +; SSE42-NEXT: pcmpeqb %xmm1, %xmm0 +; SSE42-NEXT: pxor %xmm3, %xmm0 +; SSE42-NEXT: retq +; +; AVX2-LABEL: v16i1: +; AVX2: # %bb.0: +; AVX2-NEXT: vpsllw $7, %xmm0, %xmm0 +; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1 +; AVX2-NEXT: vpcmpgtb %xmm0, %xmm1, %xmm0 +; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 +; AVX2-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1 +; AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm0 +; AVX2-NEXT: vpsrlw $8, %xmm0, %xmm2 +; AVX2-NEXT: vpminub %xmm2, %xmm0, %xmm0 +; AVX2-NEXT: vphminposuw %xmm0, %xmm0 +; AVX2-NEXT: vmovd %xmm0, %eax +; AVX2-NEXT: addb $17, %al +; AVX2-NEXT: vmovd %eax, %xmm0 +; AVX2-NEXT: vpbroadcastb %xmm0, %xmm0 +; AVX2-NEXT: vmovdqa {{.*#+}} xmm2 = [0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15] +; AVX2-NEXT: vpmaxub %xmm2, %xmm0, %xmm0 +; AVX2-NEXT: vpcmpeqb %xmm2, %xmm0, %xmm0 +; AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm0 +; AVX2-NEXT: retq + %x = call <16 x i1> @llvm.mask.beforefirst(<16 x i1> %m) + ret <16 x i1> %x +} + +define <8 x i1> @v8i1(<8 x i1> %m) { +; SSE2-LABEL: v8i1: +; SSE2: # %bb.0: +; SSE2-NEXT: psllw $15, %xmm0 +; SSE2-NEXT: psraw $15, %xmm0 +; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 +; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,2,3] +; SSE2-NEXT: psubusw %xmm0, %xmm1 +; SSE2-NEXT: paddw %xmm0, %xmm1 +; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,1,1] +; SSE2-NEXT: psubusw %xmm1, %xmm0 +; SSE2-NEXT: paddw %xmm1, %xmm0 +; SSE2-NEXT: pextrw $1, %xmm0, %eax +; SSE2-NEXT: movd %xmm0, %ecx +; SSE2-NEXT: cmpw %ax, %cx +; SSE2-NEXT: cmoval %ecx, %eax +; SSE2-NEXT: movl $8, %ecx +; SSE2-NEXT: subl %eax, %ecx +; SSE2-NEXT: movd %ecx, %xmm0 +; SSE2-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,0,0,0,4,5,6,7] +; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1] +; SSE2-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 +; SSE2-NEXT: pcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 +; SSE2-NEXT: retq +; +; SSE42-LABEL: v8i1: +; SSE42: # %bb.0: +; SSE42-NEXT: psllw $15, %xmm0 +; SSE42-NEXT: psraw $15, %xmm0 +; SSE42-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 +; SSE42-NEXT: pcmpeqd %xmm1, %xmm1 +; SSE42-NEXT: pxor %xmm1, %xmm0 +; SSE42-NEXT: phminposuw %xmm0, %xmm0 +; SSE42-NEXT: movd %xmm0, %eax +; SSE42-NEXT: addl $9, %eax +; SSE42-NEXT: movd %eax, %xmm0 +; SSE42-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,0,0,0,4,5,6,7] +; SSE42-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1] +; SSE42-NEXT: movdqa {{.*#+}} xmm2 = [0,1,2,3,4,5,6,7] +; SSE42-NEXT: pmaxuw %xmm2, %xmm0 +; SSE42-NEXT: pcmpeqw %xmm2, %xmm0 +; SSE42-NEXT: pxor %xmm1, %xmm0 +; SSE42-NEXT: retq +; +; AVX2-LABEL: v8i1: +; AVX2: # %bb.0: +; AVX2-NEXT: vpsllw $15, %xmm0, %xmm0 +; AVX2-NEXT: vpsraw $15, %xmm0, %xmm0 +; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 +; AVX2-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1 +; AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm0 +; AVX2-NEXT: vphminposuw %xmm0, %xmm0 +; AVX2-NEXT: vmovd %xmm0, %eax +; AVX2-NEXT: addl $9, %eax +; AVX2-NEXT: vmovd %eax, %xmm0 +; AVX2-NEXT: vpbroadcastw %xmm0, %xmm0 +; AVX2-NEXT: vmovdqa {{.*#+}} xmm2 = [0,1,2,3,4,5,6,7] +; AVX2-NEXT: vpmaxuw %xmm2, %xmm0, %xmm0 +; AVX2-NEXT: vpcmpeqw %xmm2, %xmm0, %xmm0 +; AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm0 +; AVX2-NEXT: retq + %x = call <8 x i1> @llvm.mask.beforefirst(<8 x i1> %m) + ret <8 x i1> %x +} + +define <4 x i1> @v4i1(<4 x i1> %m) { +; SSE2-LABEL: v4i1: +; SSE2: # %bb.0: +; SSE2-NEXT: pslld $31, %xmm0 +; SSE2-NEXT: psrad $31, %xmm0 +; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 +; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483648,2147483648,2147483648,2147483648] +; SSE2-NEXT: movdqa %xmm0, %xmm2 +; SSE2-NEXT: por %xmm1, %xmm2 +; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm0[2,3,2,3] +; SSE2-NEXT: movdqa %xmm3, %xmm4 +; SSE2-NEXT: por %xmm1, %xmm4 +; SSE2-NEXT: pcmpgtd %xmm4, %xmm2 +; SSE2-NEXT: pand %xmm2, %xmm0 +; SSE2-NEXT: pandn %xmm3, %xmm2 +; SSE2-NEXT: por %xmm0, %xmm2 +; SSE2-NEXT: movd %xmm2, %eax +; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm2[1,1,1,1] +; SSE2-NEXT: movd %xmm0, %ecx +; SSE2-NEXT: cmpl %ecx, %eax +; SSE2-NEXT: cmoval %eax, %ecx +; SSE2-NEXT: movl $4, %eax +; SSE2-NEXT: subl %ecx, %eax +; SSE2-NEXT: movd %eax, %xmm0 +; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,0,0,0] +; SSE2-NEXT: pxor %xmm1, %xmm0 +; SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 +; SSE2-NEXT: retq +; +; SSE42-LABEL: v4i1: +; SSE42: # %bb.0: +; SSE42-NEXT: pslld $31, %xmm0 +; SSE42-NEXT: psrad $31, %xmm0 +; SSE42-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 +; SSE42-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,2,3] +; SSE42-NEXT: pmaxud %xmm0, %xmm1 +; SSE42-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,1,1] +; SSE42-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,0,0] +; SSE42-NEXT: pmaxud %xmm0, %xmm1 +; SSE42-NEXT: movdqa {{.*#+}} xmm2 = [4,4,4,4] +; SSE42-NEXT: psubd %xmm1, %xmm2 +; SSE42-NEXT: movdqa {{.*#+}} xmm0 = [0,1,2,3] +; SSE42-NEXT: pmaxud %xmm0, %xmm2 +; SSE42-NEXT: pcmpeqd %xmm0, %xmm2 +; SSE42-NEXT: pcmpeqd %xmm0, %xmm0 +; SSE42-NEXT: pxor %xmm2, %xmm0 +; SSE42-NEXT: retq +; +; AVX2-LABEL: v4i1: +; AVX2: # %bb.0: +; AVX2-NEXT: vpslld $31, %xmm0, %xmm0 +; AVX2-NEXT: vpsrad $31, %xmm0, %xmm0 +; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 +; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3] +; AVX2-NEXT: vpmaxud %xmm1, %xmm0, %xmm0 +; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,1,1] +; AVX2-NEXT: vpmaxud %xmm1, %xmm0, %xmm0 +; AVX2-NEXT: vmovd %xmm0, %eax +; AVX2-NEXT: movl $4, %ecx +; AVX2-NEXT: subl %eax, %ecx +; AVX2-NEXT: vmovd %ecx, %xmm0 +; AVX2-NEXT: vpbroadcastd %xmm0, %xmm0 +; AVX2-NEXT: vmovdqa {{.*#+}} xmm1 = [0,1,2,3] +; AVX2-NEXT: vpmaxud %xmm1, %xmm0, %xmm0 +; AVX2-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0 +; AVX2-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1 +; AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm0 +; AVX2-NEXT: retq + %x = call <4 x i1> @llvm.mask.beforefirst(<4 x i1> %m) + ret <4 x i1> %x +} + +define <2 x i1> @v2i1(<2 x i1> %m) { +; SSE2-LABEL: v2i1: +; SSE2: # %bb.0: +; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,0,2,2] +; SSE2-NEXT: pslld $31, %xmm0 +; SSE2-NEXT: psrad $31, %xmm0 +; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 +; SSE2-NEXT: movd %xmm0, %eax +; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,2,3] +; SSE2-NEXT: movd %xmm0, %ecx +; SSE2-NEXT: cmpq %rcx, %rax +; SSE2-NEXT: cmovaq %rax, %rcx +; SSE2-NEXT: movl $2, %eax +; SSE2-NEXT: subq %rcx, %rax +; SSE2-NEXT: movq %rax, %xmm0 +; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1] +; SSE2-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 +; SSE2-NEXT: movdqa %xmm0, %xmm1 +; SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 +; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3] +; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm1[0,0,2,2] +; SSE2-NEXT: pcmpeqd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2 +; SSE2-NEXT: pand %xmm0, %xmm2 +; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,3,3] +; SSE2-NEXT: por %xmm2, %xmm0 +; SSE2-NEXT: retq +; +; SSE42-LABEL: v2i1: +; SSE42: # %bb.0: +; SSE42-NEXT: psllq $63, %xmm0 +; SSE42-NEXT: pxor %xmm1, %xmm1 +; SSE42-NEXT: pcmpgtq %xmm0, %xmm1 +; SSE42-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 +; SSE42-NEXT: pextrq $1, %xmm1, %rax +; SSE42-NEXT: movd %xmm1, %ecx +; SSE42-NEXT: cmpq %rax, %rcx +; SSE42-NEXT: cmovaq %rcx, %rax +; SSE42-NEXT: movl $2, %ecx +; SSE42-NEXT: subq %rax, %rcx +; SSE42-NEXT: movq %rcx, %xmm0 +; SSE42-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1] +; SSE42-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 +; SSE42-NEXT: pcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 +; SSE42-NEXT: retq +; +; AVX2-LABEL: v2i1: +; AVX2: # %bb.0: +; AVX2-NEXT: vpsllq $63, %xmm0, %xmm0 +; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1 +; AVX2-NEXT: vpcmpgtq %xmm0, %xmm1, %xmm0 +; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 +; AVX2-NEXT: vpextrq $1, %xmm0, %rax +; AVX2-NEXT: vmovd %xmm0, %ecx +; AVX2-NEXT: cmpq %rax, %rcx +; AVX2-NEXT: cmovaq %rcx, %rax +; AVX2-NEXT: movl $2, %ecx +; AVX2-NEXT: subq %rax, %rcx +; AVX2-NEXT: vmovq %rcx, %xmm0 +; AVX2-NEXT: vpbroadcastq %xmm0, %xmm0 +; AVX2-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 +; AVX2-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 +; AVX2-NEXT: retq + %x = call <2 x i1> @llvm.mask.beforefirst(<2 x i1> %m) + ret <2 x i1> %x +} define <1 x i1> @v1i1(<1 x i1> %m) { ; SSE2-LABEL: v1i1: @@ -10,13 +296,19 @@ define <1 x i1> @v1i1(<1 x i1> %m) { ; SSE2-NEXT: # kill: def $al killed $al killed $eax ; SSE2-NEXT: retq ; -; AVX512-LABEL: v1i1: -; AVX512: # %bb.0: -; AVX512-NEXT: kmovw %edi, %k0 -; AVX512-NEXT: knotw %k0, %k0 -; AVX512-NEXT: kmovw %k0, %eax -; AVX512-NEXT: # kill: def $al killed $al killed $eax -; AVX512-NEXT: retq +; SSE42-LABEL: v1i1: +; SSE42: # %bb.0: +; SSE42-NEXT: movl %edi, %eax +; SSE42-NEXT: xorb $1, %al +; SSE42-NEXT: # kill: def $al killed $al killed $eax +; SSE42-NEXT: retq +; +; AVX2-LABEL: v1i1: +; AVX2: # %bb.0: +; AVX2-NEXT: movl %edi, %eax +; AVX2-NEXT: xorb $1, %al +; AVX2-NEXT: # kill: def $al killed $al killed $eax +; AVX2-NEXT: retq %x = call <1 x i1> @llvm.mask.beforefirst(<1 x i1> %m) ret <1 x i1> %x } >From 6f339909afc5f3364dc35d2db0d6b68003bc28a8 Mon Sep 17 00:00:00 2001 From: Luke Lau <[email protected]> Date: Fri, 9 Oct 2026 13:59:50 +0100 Subject: [PATCH 3/3] Don't use mask types in arguments or return --- llvm/test/CodeGen/X86/mask-beforefirst.ll | 387 ++++++++++++---------- 1 file changed, 207 insertions(+), 180 deletions(-) diff --git a/llvm/test/CodeGen/X86/mask-beforefirst.ll b/llvm/test/CodeGen/X86/mask-beforefirst.ll index 35b472eed82424..86b49b7c0cbfc2 100644 --- a/llvm/test/CodeGen/X86/mask-beforefirst.ll +++ b/llvm/test/CodeGen/X86/mask-beforefirst.ll @@ -5,258 +5,282 @@ ; TODO: Fix crash on AVX512 ; llc < %s -mtriple=x86_64 -mcpu=x86-64-v4 | FileCheck %s --check-prefixes=AVX512 -define <16 x i1> @v16i1(<16 x i1> %m) { +define <16 x i8> @v16i1(<16 x i8> %a0, <16 x i8> %a1) { ; SSE2-LABEL: v16i1: ; SSE2: # %bb.0: -; SSE2-NEXT: psllw $7, %xmm0 -; SSE2-NEXT: pxor %xmm1, %xmm1 -; SSE2-NEXT: pcmpgtb %xmm0, %xmm1 -; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 -; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm1[2,3,2,3] -; SSE2-NEXT: pmaxub %xmm1, %xmm0 -; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,1,1] -; SSE2-NEXT: pmaxub %xmm0, %xmm1 -; SSE2-NEXT: movdqa %xmm1, %xmm0 -; SSE2-NEXT: psrld $16, %xmm0 -; SSE2-NEXT: pmaxub %xmm1, %xmm0 -; SSE2-NEXT: movdqa %xmm0, %xmm1 -; SSE2-NEXT: psrlw $8, %xmm1 -; SSE2-NEXT: pmaxub %xmm0, %xmm1 -; SSE2-NEXT: movd %xmm1, %eax +; SSE2-NEXT: movdqa %xmm0, %xmm2 +; SSE2-NEXT: pcmpgtb %xmm1, %xmm2 +; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2 +; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm2[2,3,2,3] +; SSE2-NEXT: pmaxub %xmm2, %xmm3 +; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm3[1,1,1,1] +; SSE2-NEXT: pmaxub %xmm3, %xmm2 +; SSE2-NEXT: movdqa %xmm2, %xmm3 +; SSE2-NEXT: psrld $16, %xmm3 +; SSE2-NEXT: pmaxub %xmm2, %xmm3 +; SSE2-NEXT: movdqa %xmm3, %xmm2 +; SSE2-NEXT: psrlw $8, %xmm2 +; SSE2-NEXT: pmaxub %xmm3, %xmm2 +; SSE2-NEXT: movd %xmm2, %eax ; SSE2-NEXT: movb $16, %cl ; SSE2-NEXT: subb %al, %cl ; SSE2-NEXT: movzbl %cl, %eax -; SSE2-NEXT: movd %eax, %xmm0 -; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] -; SSE2-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,0,0,0,4,5,6,7] -; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[0,1,0,1] -; SSE2-NEXT: movdqa {{.*#+}} xmm0 = [0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15] -; SSE2-NEXT: pmaxub %xmm0, %xmm1 -; SSE2-NEXT: pcmpeqb %xmm0, %xmm1 -; SSE2-NEXT: pcmpeqd %xmm0, %xmm0 -; SSE2-NEXT: pxor %xmm1, %xmm0 +; SSE2-NEXT: movd %eax, %xmm2 +; SSE2-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] +; SSE2-NEXT: pshuflw {{.*#+}} xmm2 = xmm2[0,0,0,0,4,5,6,7] +; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,1,0,1] +; SSE2-NEXT: movdqa {{.*#+}} xmm3 = [0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15] +; SSE2-NEXT: pmaxub %xmm3, %xmm2 +; SSE2-NEXT: pcmpeqb %xmm3, %xmm2 +; SSE2-NEXT: pcmpeqd %xmm3, %xmm3 +; SSE2-NEXT: pxor %xmm2, %xmm3 +; SSE2-NEXT: pxor %xmm2, %xmm2 +; SSE2-NEXT: pcmpgtb %xmm3, %xmm2 +; SSE2-NEXT: pand %xmm2, %xmm0 +; SSE2-NEXT: pandn %xmm1, %xmm2 +; SSE2-NEXT: por %xmm2, %xmm0 ; SSE2-NEXT: retq ; ; SSE42-LABEL: v16i1: ; SSE42: # %bb.0: -; SSE42-NEXT: psllw $7, %xmm0 -; SSE42-NEXT: pxor %xmm1, %xmm1 -; SSE42-NEXT: pxor %xmm2, %xmm2 -; SSE42-NEXT: pcmpgtb %xmm0, %xmm2 -; SSE42-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2 +; SSE42-NEXT: movdqa %xmm0, %xmm2 +; SSE42-NEXT: pcmpgtb %xmm1, %xmm0 +; SSE42-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; SSE42-NEXT: pcmpeqd %xmm3, %xmm3 -; SSE42-NEXT: pxor %xmm3, %xmm2 -; SSE42-NEXT: movdqa %xmm2, %xmm0 +; SSE42-NEXT: pxor %xmm0, %xmm3 +; SSE42-NEXT: movdqa %xmm3, %xmm0 ; SSE42-NEXT: psrlw $8, %xmm0 -; SSE42-NEXT: pminub %xmm2, %xmm0 +; SSE42-NEXT: pminub %xmm3, %xmm0 ; SSE42-NEXT: phminposuw %xmm0, %xmm0 ; SSE42-NEXT: movd %xmm0, %eax ; SSE42-NEXT: addb $17, %al ; SSE42-NEXT: movzbl %al, %eax ; SSE42-NEXT: movd %eax, %xmm0 -; SSE42-NEXT: pshufb %xmm1, %xmm0 -; SSE42-NEXT: movdqa {{.*#+}} xmm1 = [0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15] -; SSE42-NEXT: pmaxub %xmm1, %xmm0 -; SSE42-NEXT: pcmpeqb %xmm1, %xmm0 -; SSE42-NEXT: pxor %xmm3, %xmm0 +; SSE42-NEXT: pxor %xmm3, %xmm3 +; SSE42-NEXT: pshufb %xmm3, %xmm0 +; SSE42-NEXT: movdqa {{.*#+}} xmm3 = [0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15] +; SSE42-NEXT: pmaxub %xmm3, %xmm0 +; SSE42-NEXT: pcmpeqb %xmm3, %xmm0 +; SSE42-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 +; SSE42-NEXT: pblendvb %xmm0, %xmm2, %xmm1 +; SSE42-NEXT: movdqa %xmm1, %xmm0 ; SSE42-NEXT: retq ; ; AVX2-LABEL: v16i1: ; AVX2: # %bb.0: -; AVX2-NEXT: vpsllw $7, %xmm0, %xmm0 -; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1 -; AVX2-NEXT: vpcmpgtb %xmm0, %xmm1, %xmm0 -; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 -; AVX2-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1 -; AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm0 -; AVX2-NEXT: vpsrlw $8, %xmm0, %xmm2 -; AVX2-NEXT: vpminub %xmm2, %xmm0, %xmm0 -; AVX2-NEXT: vphminposuw %xmm0, %xmm0 -; AVX2-NEXT: vmovd %xmm0, %eax +; AVX2-NEXT: vpcmpgtb %xmm1, %xmm0, %xmm2 +; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2 +; AVX2-NEXT: vpcmpeqd %xmm3, %xmm3, %xmm3 +; AVX2-NEXT: vpxor %xmm3, %xmm2, %xmm2 +; AVX2-NEXT: vpsrlw $8, %xmm2, %xmm3 +; AVX2-NEXT: vpminub %xmm3, %xmm2, %xmm2 +; AVX2-NEXT: vphminposuw %xmm2, %xmm2 +; AVX2-NEXT: vmovd %xmm2, %eax ; AVX2-NEXT: addb $17, %al -; AVX2-NEXT: vmovd %eax, %xmm0 -; AVX2-NEXT: vpbroadcastb %xmm0, %xmm0 -; AVX2-NEXT: vmovdqa {{.*#+}} xmm2 = [0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15] -; AVX2-NEXT: vpmaxub %xmm2, %xmm0, %xmm0 -; AVX2-NEXT: vpcmpeqb %xmm2, %xmm0, %xmm0 -; AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm0 +; AVX2-NEXT: vmovd %eax, %xmm2 +; AVX2-NEXT: vpbroadcastb %xmm2, %xmm2 +; AVX2-NEXT: vmovdqa {{.*#+}} xmm3 = [0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15] +; AVX2-NEXT: vpmaxub %xmm3, %xmm2, %xmm2 +; AVX2-NEXT: vpcmpeqb %xmm3, %xmm2, %xmm2 +; AVX2-NEXT: vpandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2 +; AVX2-NEXT: vpblendvb %xmm2, %xmm0, %xmm1, %xmm0 ; AVX2-NEXT: retq + %m = icmp sgt <16 x i8> %a0, %a1 %x = call <16 x i1> @llvm.mask.beforefirst(<16 x i1> %m) - ret <16 x i1> %x + %r = select <16 x i1> %x, <16 x i8> %a0, <16 x i8> %a1 + ret <16 x i8> %r } -define <8 x i1> @v8i1(<8 x i1> %m) { +define <8 x i16> @v8i1(<8 x i16> %a0, <8 x i16> %a1) { ; SSE2-LABEL: v8i1: ; SSE2: # %bb.0: -; SSE2-NEXT: psllw $15, %xmm0 -; SSE2-NEXT: psraw $15, %xmm0 -; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 -; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,2,3] -; SSE2-NEXT: psubusw %xmm0, %xmm1 -; SSE2-NEXT: paddw %xmm0, %xmm1 -; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,1,1] -; SSE2-NEXT: psubusw %xmm1, %xmm0 -; SSE2-NEXT: paddw %xmm1, %xmm0 -; SSE2-NEXT: pextrw $1, %xmm0, %eax -; SSE2-NEXT: movd %xmm0, %ecx +; SSE2-NEXT: movdqa %xmm0, %xmm2 +; SSE2-NEXT: pcmpgtw %xmm1, %xmm2 +; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2 +; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm2[2,3,2,3] +; SSE2-NEXT: psubusw %xmm2, %xmm3 +; SSE2-NEXT: paddw %xmm2, %xmm3 +; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm3[1,1,1,1] +; SSE2-NEXT: psubusw %xmm3, %xmm2 +; SSE2-NEXT: paddw %xmm3, %xmm2 +; SSE2-NEXT: pextrw $1, %xmm2, %eax +; SSE2-NEXT: movd %xmm2, %ecx ; SSE2-NEXT: cmpw %ax, %cx ; SSE2-NEXT: cmoval %ecx, %eax ; SSE2-NEXT: movl $8, %ecx ; SSE2-NEXT: subl %eax, %ecx -; SSE2-NEXT: movd %ecx, %xmm0 -; SSE2-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,0,0,0,4,5,6,7] -; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1] -; SSE2-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 -; SSE2-NEXT: pcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 +; SSE2-NEXT: movd %ecx, %xmm2 +; SSE2-NEXT: pshuflw {{.*#+}} xmm2 = xmm2[0,0,0,0,4,5,6,7] +; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,1,0,1] +; SSE2-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2 +; SSE2-NEXT: pcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2 +; SSE2-NEXT: pand %xmm2, %xmm0 +; SSE2-NEXT: pandn %xmm1, %xmm2 +; SSE2-NEXT: por %xmm2, %xmm0 ; SSE2-NEXT: retq ; ; SSE42-LABEL: v8i1: ; SSE42: # %bb.0: -; SSE42-NEXT: psllw $15, %xmm0 -; SSE42-NEXT: psraw $15, %xmm0 +; SSE42-NEXT: movdqa %xmm0, %xmm2 +; SSE42-NEXT: pcmpgtw %xmm1, %xmm0 ; SSE42-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 -; SSE42-NEXT: pcmpeqd %xmm1, %xmm1 -; SSE42-NEXT: pxor %xmm1, %xmm0 -; SSE42-NEXT: phminposuw %xmm0, %xmm0 +; SSE42-NEXT: pcmpeqd %xmm3, %xmm3 +; SSE42-NEXT: pxor %xmm0, %xmm3 +; SSE42-NEXT: phminposuw %xmm3, %xmm0 ; SSE42-NEXT: movd %xmm0, %eax ; SSE42-NEXT: addl $9, %eax ; SSE42-NEXT: movd %eax, %xmm0 ; SSE42-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,0,0,0,4,5,6,7] ; SSE42-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1] -; SSE42-NEXT: movdqa {{.*#+}} xmm2 = [0,1,2,3,4,5,6,7] -; SSE42-NEXT: pmaxuw %xmm2, %xmm0 -; SSE42-NEXT: pcmpeqw %xmm2, %xmm0 -; SSE42-NEXT: pxor %xmm1, %xmm0 +; SSE42-NEXT: movdqa {{.*#+}} xmm3 = [0,1,2,3,4,5,6,7] +; SSE42-NEXT: pmaxuw %xmm3, %xmm0 +; SSE42-NEXT: pcmpeqw %xmm3, %xmm0 +; SSE42-NEXT: pblendvb %xmm0, %xmm1, %xmm2 +; SSE42-NEXT: movdqa %xmm2, %xmm0 ; SSE42-NEXT: retq ; ; AVX2-LABEL: v8i1: ; AVX2: # %bb.0: -; AVX2-NEXT: vpsllw $15, %xmm0, %xmm0 -; AVX2-NEXT: vpsraw $15, %xmm0, %xmm0 -; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 -; AVX2-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1 -; AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm0 -; AVX2-NEXT: vphminposuw %xmm0, %xmm0 -; AVX2-NEXT: vmovd %xmm0, %eax +; AVX2-NEXT: vpcmpgtw %xmm1, %xmm0, %xmm2 +; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2 +; AVX2-NEXT: vpcmpeqd %xmm3, %xmm3, %xmm3 +; AVX2-NEXT: vpxor %xmm3, %xmm2, %xmm2 +; AVX2-NEXT: vphminposuw %xmm2, %xmm2 +; AVX2-NEXT: vmovd %xmm2, %eax ; AVX2-NEXT: addl $9, %eax -; AVX2-NEXT: vmovd %eax, %xmm0 -; AVX2-NEXT: vpbroadcastw %xmm0, %xmm0 -; AVX2-NEXT: vmovdqa {{.*#+}} xmm2 = [0,1,2,3,4,5,6,7] -; AVX2-NEXT: vpmaxuw %xmm2, %xmm0, %xmm0 -; AVX2-NEXT: vpcmpeqw %xmm2, %xmm0, %xmm0 -; AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm0 +; AVX2-NEXT: vmovd %eax, %xmm2 +; AVX2-NEXT: vpbroadcastw %xmm2, %xmm2 +; AVX2-NEXT: vmovdqa {{.*#+}} xmm3 = [0,1,2,3,4,5,6,7] +; AVX2-NEXT: vpmaxuw %xmm3, %xmm2, %xmm2 +; AVX2-NEXT: vpcmpeqw %xmm3, %xmm2, %xmm2 +; AVX2-NEXT: vpblendvb %xmm2, %xmm1, %xmm0, %xmm0 ; AVX2-NEXT: retq + %m = icmp sgt <8 x i16> %a0, %a1 %x = call <8 x i1> @llvm.mask.beforefirst(<8 x i1> %m) - ret <8 x i1> %x + %r = select <8 x i1> %x, <8 x i16> %a0, <8 x i16> %a1 + ret <8 x i16> %r } -define <4 x i1> @v4i1(<4 x i1> %m) { +define <4 x i32> @v4i1(<4 x i32> %a0, <4 x i32> %a1) { ; SSE2-LABEL: v4i1: ; SSE2: # %bb.0: -; SSE2-NEXT: pslld $31, %xmm0 -; SSE2-NEXT: psrad $31, %xmm0 -; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 -; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483648,2147483648,2147483648,2147483648] ; SSE2-NEXT: movdqa %xmm0, %xmm2 -; SSE2-NEXT: por %xmm1, %xmm2 -; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm0[2,3,2,3] -; SSE2-NEXT: movdqa %xmm3, %xmm4 -; SSE2-NEXT: por %xmm1, %xmm4 -; SSE2-NEXT: pcmpgtd %xmm4, %xmm2 -; SSE2-NEXT: pand %xmm2, %xmm0 -; SSE2-NEXT: pandn %xmm3, %xmm2 -; SSE2-NEXT: por %xmm0, %xmm2 -; SSE2-NEXT: movd %xmm2, %eax -; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm2[1,1,1,1] -; SSE2-NEXT: movd %xmm0, %ecx +; SSE2-NEXT: pcmpgtd %xmm1, %xmm2 +; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2 +; SSE2-NEXT: movdqa {{.*#+}} xmm3 = [2147483648,2147483648,2147483648,2147483648] +; SSE2-NEXT: movdqa %xmm2, %xmm4 +; SSE2-NEXT: por %xmm3, %xmm4 +; SSE2-NEXT: pshufd {{.*#+}} xmm5 = xmm2[2,3,2,3] +; SSE2-NEXT: movdqa %xmm5, %xmm6 +; SSE2-NEXT: por %xmm3, %xmm6 +; SSE2-NEXT: pcmpgtd %xmm6, %xmm4 +; SSE2-NEXT: pand %xmm4, %xmm2 +; SSE2-NEXT: pandn %xmm5, %xmm4 +; SSE2-NEXT: por %xmm2, %xmm4 +; SSE2-NEXT: movd %xmm4, %eax +; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm4[1,1,1,1] +; SSE2-NEXT: movd %xmm2, %ecx ; SSE2-NEXT: cmpl %ecx, %eax ; SSE2-NEXT: cmoval %eax, %ecx ; SSE2-NEXT: movl $4, %eax ; SSE2-NEXT: subl %ecx, %eax -; SSE2-NEXT: movd %eax, %xmm0 -; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,0,0,0] -; SSE2-NEXT: pxor %xmm1, %xmm0 -; SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 +; SSE2-NEXT: movd %eax, %xmm2 +; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,0,0,0] +; SSE2-NEXT: pxor %xmm3, %xmm2 +; SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2 +; SSE2-NEXT: pand %xmm2, %xmm0 +; SSE2-NEXT: pandn %xmm1, %xmm2 +; SSE2-NEXT: por %xmm2, %xmm0 ; SSE2-NEXT: retq ; ; SSE42-LABEL: v4i1: ; SSE42: # %bb.0: -; SSE42-NEXT: pslld $31, %xmm0 -; SSE42-NEXT: psrad $31, %xmm0 +; SSE42-NEXT: movdqa %xmm0, %xmm2 +; SSE42-NEXT: pcmpgtd %xmm1, %xmm0 ; SSE42-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 -; SSE42-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,2,3] -; SSE42-NEXT: pmaxud %xmm0, %xmm1 -; SSE42-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,1,1] -; SSE42-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,0,0] -; SSE42-NEXT: pmaxud %xmm0, %xmm1 -; SSE42-NEXT: movdqa {{.*#+}} xmm2 = [4,4,4,4] -; SSE42-NEXT: psubd %xmm1, %xmm2 -; SSE42-NEXT: movdqa {{.*#+}} xmm0 = [0,1,2,3] -; SSE42-NEXT: pmaxud %xmm0, %xmm2 -; SSE42-NEXT: pcmpeqd %xmm0, %xmm2 -; SSE42-NEXT: pcmpeqd %xmm0, %xmm0 -; SSE42-NEXT: pxor %xmm2, %xmm0 +; SSE42-NEXT: pshufd {{.*#+}} xmm3 = xmm0[2,3,2,3] +; SSE42-NEXT: pmaxud %xmm0, %xmm3 +; SSE42-NEXT: pshufd {{.*#+}} xmm0 = xmm3[1,1,1,1] +; SSE42-NEXT: pshufd {{.*#+}} xmm3 = xmm3[0,0,0,0] +; SSE42-NEXT: pmaxud %xmm0, %xmm3 +; SSE42-NEXT: movdqa {{.*#+}} xmm0 = [4,4,4,4] +; SSE42-NEXT: psubd %xmm3, %xmm0 +; SSE42-NEXT: movdqa {{.*#+}} xmm3 = [0,1,2,3] +; SSE42-NEXT: pmaxud %xmm3, %xmm0 +; SSE42-NEXT: pcmpeqd %xmm3, %xmm0 +; SSE42-NEXT: blendvps %xmm0, %xmm1, %xmm2 +; SSE42-NEXT: movaps %xmm2, %xmm0 ; SSE42-NEXT: retq ; ; AVX2-LABEL: v4i1: ; AVX2: # %bb.0: -; AVX2-NEXT: vpslld $31, %xmm0, %xmm0 -; AVX2-NEXT: vpsrad $31, %xmm0, %xmm0 -; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 -; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3] -; AVX2-NEXT: vpmaxud %xmm1, %xmm0, %xmm0 -; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,1,1] -; AVX2-NEXT: vpmaxud %xmm1, %xmm0, %xmm0 -; AVX2-NEXT: vmovd %xmm0, %eax +; AVX2-NEXT: vpcmpgtd %xmm1, %xmm0, %xmm2 +; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2 +; AVX2-NEXT: vpshufd {{.*#+}} xmm3 = xmm2[2,3,2,3] +; AVX2-NEXT: vpmaxud %xmm3, %xmm2, %xmm2 +; AVX2-NEXT: vpshufd {{.*#+}} xmm3 = xmm2[1,1,1,1] +; AVX2-NEXT: vpmaxud %xmm3, %xmm2, %xmm2 +; AVX2-NEXT: vmovd %xmm2, %eax ; AVX2-NEXT: movl $4, %ecx ; AVX2-NEXT: subl %eax, %ecx -; AVX2-NEXT: vmovd %ecx, %xmm0 -; AVX2-NEXT: vpbroadcastd %xmm0, %xmm0 -; AVX2-NEXT: vmovdqa {{.*#+}} xmm1 = [0,1,2,3] -; AVX2-NEXT: vpmaxud %xmm1, %xmm0, %xmm0 -; AVX2-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0 -; AVX2-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1 -; AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm0 +; AVX2-NEXT: vmovd %ecx, %xmm2 +; AVX2-NEXT: vpbroadcastd %xmm2, %xmm2 +; AVX2-NEXT: vmovdqa {{.*#+}} xmm3 = [0,1,2,3] +; AVX2-NEXT: vpmaxud %xmm3, %xmm2, %xmm2 +; AVX2-NEXT: vpcmpeqd %xmm3, %xmm2, %xmm2 +; AVX2-NEXT: vblendvps %xmm2, %xmm1, %xmm0, %xmm0 ; AVX2-NEXT: retq + %m = icmp sgt <4 x i32> %a0, %a1 %x = call <4 x i1> @llvm.mask.beforefirst(<4 x i1> %m) - ret <4 x i1> %x + %r = select <4 x i1> %x, <4 x i32> %a0, <4 x i32> %a1 + ret <4 x i32> %r } -define <2 x i1> @v2i1(<2 x i1> %m) { +define <2 x i64> @v2i1(<2 x i64> %a0, <2 x i64> %a1) { ; SSE2-LABEL: v2i1: ; SSE2: # %bb.0: -; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,0,2,2] -; SSE2-NEXT: pslld $31, %xmm0 -; SSE2-NEXT: psrad $31, %xmm0 -; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 -; SSE2-NEXT: movd %xmm0, %eax -; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,2,3] -; SSE2-NEXT: movd %xmm0, %ecx +; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648] +; SSE2-NEXT: movdqa %xmm1, %xmm3 +; SSE2-NEXT: pxor %xmm2, %xmm3 +; SSE2-NEXT: pxor %xmm0, %xmm2 +; SSE2-NEXT: movdqa %xmm2, %xmm4 +; SSE2-NEXT: pcmpgtd %xmm3, %xmm4 +; SSE2-NEXT: pshufd {{.*#+}} xmm5 = xmm4[0,0,2,2] +; SSE2-NEXT: pcmpeqd %xmm3, %xmm2 +; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3] +; SSE2-NEXT: pand %xmm5, %xmm2 +; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm4[1,1,3,3] +; SSE2-NEXT: por %xmm2, %xmm3 +; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3 +; SSE2-NEXT: movd %xmm3, %eax +; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm3[2,3,2,3] +; SSE2-NEXT: movd %xmm2, %ecx ; SSE2-NEXT: cmpq %rcx, %rax ; SSE2-NEXT: cmovaq %rax, %rcx ; SSE2-NEXT: movl $2, %eax ; SSE2-NEXT: subq %rcx, %rax -; SSE2-NEXT: movq %rax, %xmm0 -; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1] -; SSE2-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 -; SSE2-NEXT: movdqa %xmm0, %xmm1 -; SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 -; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3] -; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm1[0,0,2,2] -; SSE2-NEXT: pcmpeqd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2 -; SSE2-NEXT: pand %xmm0, %xmm2 -; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,3,3] +; SSE2-NEXT: movq %rax, %xmm2 +; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,1,0,1] +; SSE2-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2 +; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm2[1,1,3,3] +; SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2 +; SSE2-NEXT: pcmpeqd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3 +; SSE2-NEXT: pand %xmm2, %xmm3 +; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm3[0,0,2,2] +; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3] +; SSE2-NEXT: por %xmm3, %xmm2 +; SSE2-NEXT: pand %xmm2, %xmm0 +; SSE2-NEXT: pandn %xmm1, %xmm2 ; SSE2-NEXT: por %xmm2, %xmm0 ; SSE2-NEXT: retq ; ; SSE42-LABEL: v2i1: ; SSE42: # %bb.0: -; SSE42-NEXT: psllq $63, %xmm0 -; SSE42-NEXT: pxor %xmm1, %xmm1 -; SSE42-NEXT: pcmpgtq %xmm0, %xmm1 -; SSE42-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 -; SSE42-NEXT: pextrq $1, %xmm1, %rax -; SSE42-NEXT: movd %xmm1, %ecx +; SSE42-NEXT: movdqa %xmm0, %xmm2 +; SSE42-NEXT: pcmpgtq %xmm1, %xmm0 +; SSE42-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 +; SSE42-NEXT: pextrq $1, %xmm0, %rax +; SSE42-NEXT: movd %xmm0, %ecx ; SSE42-NEXT: cmpq %rax, %rcx ; SSE42-NEXT: cmovaq %rcx, %rax ; SSE42-NEXT: movl $2, %ecx @@ -265,27 +289,30 @@ define <2 x i1> @v2i1(<2 x i1> %m) { ; SSE42-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1] ; SSE42-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; SSE42-NEXT: pcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 +; SSE42-NEXT: blendvpd %xmm0, %xmm2, %xmm1 +; SSE42-NEXT: movapd %xmm1, %xmm0 ; SSE42-NEXT: retq ; ; AVX2-LABEL: v2i1: ; AVX2: # %bb.0: -; AVX2-NEXT: vpsllq $63, %xmm0, %xmm0 -; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1 -; AVX2-NEXT: vpcmpgtq %xmm0, %xmm1, %xmm0 -; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 -; AVX2-NEXT: vpextrq $1, %xmm0, %rax -; AVX2-NEXT: vmovd %xmm0, %ecx +; AVX2-NEXT: vpcmpgtq %xmm1, %xmm0, %xmm2 +; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2 +; AVX2-NEXT: vpextrq $1, %xmm2, %rax +; AVX2-NEXT: vmovd %xmm2, %ecx ; AVX2-NEXT: cmpq %rax, %rcx ; AVX2-NEXT: cmovaq %rcx, %rax ; AVX2-NEXT: movl $2, %ecx ; AVX2-NEXT: subq %rax, %rcx -; AVX2-NEXT: vmovq %rcx, %xmm0 -; AVX2-NEXT: vpbroadcastq %xmm0, %xmm0 -; AVX2-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 -; AVX2-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 +; AVX2-NEXT: vmovq %rcx, %xmm2 +; AVX2-NEXT: vpbroadcastq %xmm2, %xmm2 +; AVX2-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2 +; AVX2-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2 +; AVX2-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0 ; AVX2-NEXT: retq + %m = icmp sgt <2 x i64> %a0, %a1 %x = call <2 x i1> @llvm.mask.beforefirst(<2 x i1> %m) - ret <2 x i1> %x + %r = select <2 x i1> %x, <2 x i64> %a0, <2 x i64> %a1 + ret <2 x i64> %r } define <1 x i1> @v1i1(<1 x i1> %m) { _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
