https://llvm.org/bugs/show_bug.cgi?id=25685
Bug ID: 25685
Summary: [ppc] bad scheduling for special register access
instructions
Product: libraries
Version: trunk
Hardware: PC
OS: Linux
Status: NEW
Severity: normal
Priority: P
Component: Backend: PowerPC
Assignee: [email protected]
Reporter: [email protected]
CC: [email protected]
Classification: Unclassified
This is a very common instruction sequence.
One example is Perl_sv_setsv_flags from perlbench. On power8, llvm generated
Perl_sv_setsv_flags consumes 4.26% of run time, gcc generated function consumes
3.5% of run time.
perf annotate shows following instructions and cycles of llvm generated code:
│ 00000000100c67d0 <Perl_sv_setsv_flags>:
│ addis r2,r12,26
│ addi r2,r2,31576
4.95 │ mfcr r12
4.18 │ mflr r0
0.07 │ std r31,-8(r1)
│ std r0,16(r1)
0.02 │ stw r12,8(r1)
...
The two instructions mfcr/mflr consume many time, these are slow instructions,
but the results are used immediately, causes stalling.
For comparison following is gcc generated code:
│ 00000000100d02f0 <Perl_sv_setsv_flags>:
│ addis r2,r12,24
│ addi r2,r2,21112
1.63 │ mflr r0
│ cmpld cr7,r4,r3
1.57 │ std r30,-16(r1)
0.01 │ std r31,-8(r1)
1.66 │ mfocrf r12,8
│ std r26,-48(r1)
│ std r27,-40(r1)
0.02 │ mr r31,r3
│ mr r30,r4
│ std r28,-32(r1)
2.64 │ std r29,-24(r1)
│ stw r12,8(r1)
│ std r0,16(r1)
...
It has much better scheduling of mflr/mfocrf and corresponding usage
instructions.
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