https://llvm.org/bugs/show_bug.cgi?id=25858
Bug ID: 25858
Summary: Missed optimization: `subq x, ...` and `sbbq $0, ...`
not combined
Product: new-bugs
Version: 3.7
Hardware: PC
OS: All
Status: NEW
Severity: enhancement
Priority: P
Component: new bugs
Assignee: unassignedb...@nondot.org
Reporter: schnet...@gmail.com
CC: llvm-bugs@lists.llvm.org
Classification: Unclassified
I see this code generated:
{{{
pushq %rbp
movq %rsp, %rbp
movq (%rsi), %rax
movq 8(%rsi), %rcx
subq 8(%rdx), %rcx
subq (%rdx), %rax
sbbq $0, %rcx
movq %rax, (%rdi)
movq %rcx, 8(%rdi)
movq %rdi, %rax
popq %rbp
retq
}}}
Note the two instructions {subq 8(%rdx), %rcx} and {sbbq $0, %rcx} -- they
could be combined to {sbbq 8(%rdx), %rcx}.
This is the bitcode that generated the instructions above:
{{{
define void @julia_-_22617(%WideUInt* sret, %WideUInt*, %WideUInt*) #0 {
top:
%3 = bitcast %WideUInt* %1 to i64*
%4 = load i64, i64* %3, align 8
%5 = bitcast %WideUInt* %2 to i64*
%6 = load i64, i64* %5, align 8
%7 = sub i64 %4, %6
%8 = call { i64, i1 } @llvm.usub.with.overflow.i64(i64 %4, i64 %6)
%9 = extractvalue { i64, i1 } %8, 1
%10 = getelementptr inbounds %WideUInt, %WideUInt* %1, i64 0, i32 1
%11 = load i64, i64* %10, align 8
%12 = getelementptr inbounds %WideUInt, %WideUInt* %2, i64 0, i32 1
%13 = load i64, i64* %12, align 8
%14 = sub i64 %11, %13
%.neg1 = sext i1 %9 to i64
%15 = add i64 %14, %.neg1
%16 = insertvalue %WideUInt undef, i64 %7, 0
%17 = insertvalue %WideUInt %16, i64 %15, 1
store %WideUInt %17, %WideUInt* %0, align 8
ret void
}
}}}
The root of the issue is of course the duplication of the {sub} instruction and
the {llvm.usub.with.overflow} intrinsic.
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