https://llvm.org/bugs/show_bug.cgi?id=26762
Bug ID: 26762
Summary: [AVX512] Masked instruction selection gets confused by
bitcasts
Product: libraries
Version: trunk
Hardware: PC
OS: All
Status: NEW
Severity: normal
Priority: P
Component: Backend: X86
Assignee: [email protected]
Reporter: [email protected]
CC: [email protected]
Classification: Unclassified
Creating a VPMOVZX by zero extend and then masking it correctly creates a
masked instruction:
define <16 x i16> @zext_mask_16x8_to_16x16(<16 x i8> %a, <16 x i1> %mask) {
%ext = zext <16 x i8> %a to <16 x i16>
%ret = select <16 x i1> %mask, <16 x i16> %ext, <16 x i16> zeroinitializer
ret <16 x i16> %ret
}
vpsllw $7, %xmm1, %xmm1
vpmovb2m %xmm1, %k1
vpmovzxbw %xmm0, %ymm0 {%k1} {z}
retq
But creating a VPMOVZX by a bitcasted shuffle fails to merge the mask:
define <16 x i16> @zext_mask_16x8_to_16x16(<16 x i8> %a, <16 x i1> %mask) {
%x = shufflevector <16 x i8> %a, <16 x i8> zeroinitializer, <32 x i32> <i32
0, i32 16, i32 1, i32 16, i32 2, i32 16, i32 3, i32 16, i32 4, i32 16, i32 5,
i32 16, i32 6, i32 16, i32 7, i32 16, i32 8, i32 16, i32 9, i32 16, i32 10, i32
16, i32 11, i32 16, i32 12, i32 16, i32 13, i32 16, i32 14, i32 16, i32 15, i32
16>
%bc = bitcast <32 x i8> %x to <16 x i16>
%ret = select <16 x i1> %mask, <16 x i16> %bc, <16 x i16> zeroinitializer
ret <16 x i16> %ret
}
vpsllw $7, %xmm1, %xmm1
vpmovb2m %xmm1, %k1
vpmovzxbw %xmm0, %ymm0
vmovdqu16 %ymm0, %ymm0 {%k1} {z}
retq
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