https://llvm.org/bugs/show_bug.cgi?id=27925
Bug ID: 27925
Summary: [InstCombine] eliminate bitcasts around bitwise logic
ops when one input type and output type match
Product: libraries
Version: trunk
Hardware: PC
OS: All
Status: NEW
Severity: normal
Priority: P
Component: Scalar Optimizations
Assignee: [email protected]
Reporter: [email protected]
CC: [email protected]
Classification: Unclassified
define <4 x i32> @bitcasts(<4 x i32> %a, <8 x i16> %b) {
%bc1 = bitcast <4 x i32> %a to <2 x i64>
%bc2 = bitcast <8 x i16> %b to <2 x i64>
%and = and <2 x i64> %bc2, %bc1
%bc3 = bitcast <2 x i64> %and to <4 x i32>
ret <4 x i32> %bc3
}
By transforming the 'and' to <4 x i32> type, we eliminate 2 bitcasts:
define <4 x i32> @bitcasts(<4 x i32> %a, <8 x i16> %b) {
%bc2 = bitcast <8 x i16> %b to <4 x i32>
%and = and <4 x i32> %a, %bc2
ret <4 x i32> %and
}
Should this be limited to vector types?
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